Correct configuration of SDRAM in Sharc DSPs #48

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sedurCode wants to merge 1 commit into OpenMixerProject:main from sedurCode:initSDRAM

sedurCode commented Jan 12, 2026

Here I have changed the configuration of the SDRAM on the Sharc DSPs.

The DSROPT frequency was rounded up, leading to incorrect timing.
tRAS 7 cycles instead of 6
Disable sdram clock1
No burst stop
data bus width is 8, not 16


          Correct some of the options in the SDRAMInit code in system.c

4c4756b

borzel requested a review from xn--nding-jua

January 12, 2026 16:01

borzel added this to the OpenX32 v0.3 milestone

borzel added the bug label

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