drivers: i2s: Adding new i2s driver for PSE84

drivers/clock_control/clock_control_ifx_peri_clock.c

@@ -26,6 +26,7 @@
 	struct ifx_cat1_resource_inst hw_resource;
 	struct ifx_cat1_clock clock;
 	uint16_t divider;
+	uint8_t frac_divider;
 	CySCB_Type *reg_addr;
 };
 
@@ -44,6 +45,7 @@
 #define _IFX_CAT1_SCB0_PCLK_CLOCK    PCLK_SCB0_CLOCK_SCB_EN
 #define _IFX_CAT1_SCB1_PCLK_CLOCK    PCLK_SCB1_CLOCK_SCB_EN
 #define _IFX_CAT1_SCB5_PCLK_CLOCK    PCLK_SCB5_CLOCK_SCB_EN
+#define _IFX_CAT1_TDM0_PCLK_CLOCK    PCLK_TDM0_CLK_IF_SRSS0
 #endif
 
 en_clk_dst_t ifx_cat1_scb_get_clock_index(uint32_t block_num)
@@ -70,20 +72,73 @@
 	return clk;
 }
 
+en_clk_dst_t ifx_cat1_tcpwm_get_clock_index(uint32_t block_num, uint32_t channel)
+{
+	en_clk_dst_t clk;
+
+	if (block_num == 0) {
+		/* block_num 0 is 32-bit tcpwm instances */
+		clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_TCPWM0_PCLK_CLOCK0 + channel);
+	} else {
+		/* block_num 1 is 16-bit tcwpm instances */
+		clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_TCPWM1_PCLK_CLOCK0 + channel);
+	}
+
+	return clk;
+}
+
+en_clk_dst_t ifx_cat1_tdm_get_clock_index(uint32_t block_num, uint32_t channel)
+{
+	en_clk_dst_t clk;
+
+	if (block_num == 0) {
+		clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_TDM0_PCLK_CLOCK + channel);
+	} else {
+		__ASSERT(false, "Unsupported TDM block number");
+	}
+
+	return clk;
+}
+
 static int ifx_cat1_peri_clock_init(const struct device *dev)
 {
 	struct ifx_cat1_peri_clock_data *const data = dev->data;
+	en_clk_dst_t clk_idx;
 
 	if (data->hw_resource.type == IFX_RSC_SCB) {
-		en_clk_dst_t clk_idx = ifx_cat1_scb_get_clock_index(data->hw_resource.block_num);
-
-		ifx_cat1_utils_peri_pclk_set_divider(clk_idx, &data->clock, data->divider - 1);
-		ifx_cat1_utils_peri_pclk_assign_divider(clk_idx, &data->clock);
-		ifx_cat1_utils_peri_pclk_enable_divider(clk_idx, &data->clock);
+		clk_idx = ifx_cat1_scb_get_clock_index(data->hw_resource.block_num);
+		if (CY_RSLT_SUCCESS != ifx_cat1_utils_peri_pclk_set_divider(clk_idx, &data->clock, data->divider - 1))
+		{
+			return -EIO;
+		}
+	} else if (data->hw_resource.type == IFX_RSC_TCPWM) {
+		clk_idx = ifx_cat1_tcpwm_get_clock_index(
+			data->hw_resource.block_num, data->hw_resource.channel_num);
+
+		if (CY_RSLT_SUCCESS != ifx_cat1_utils_peri_pclk_set_divider(clk_idx, &data->clock, data->divider - 1))
+		{
+			return -EIO;
+		}
+	} else if (data->hw_resource.type == IFX_RSC_TDM) {
+		clk_idx = ifx_cat1_tdm_get_clock_index(data->hw_resource.block_num, data->hw_resource.channel_num);
+		if (CY_RSLT_SUCCESS != ifx_cat1_utils_peri_pclk_set_frac_divider(clk_idx,
+			&data->clock, data->divider - 1, data->frac_divider))
+		{
+			return -EIO;
+		}
 	} else {
 		return -EINVAL;
 	}
 
+	if (CY_RSLT_SUCCESS != ifx_cat1_utils_peri_pclk_assign_divider(clk_idx, &data->clock))
+	{
+		return -EIO;
+	}
+	if (CY_RSLT_SUCCESS != ifx_cat1_utils_peri_pclk_enable_divider(clk_idx, &data->clock))
+	{
+		return -EIO;
+	}
+
 	return 0;
 }
 
@@ -106,10 +161,12 @@
 
 #define INFINEON_CAT1_PERI_CLOCK_INIT(n)                                                           \
 	static struct ifx_cat1_peri_clock_data ifx_cat1_peri_clock##n##_data = {                   \
-		PERI_CLOCK_INIT(n).divider = DT_INST_PROP(n, clock_div),                           \
+		.divider = DT_INST_PROP(n, clock_div),                                             \
+		.frac_divider = DT_INST_PROP_OR(n, div_frac_value, 0),                             \
 		.hw_resource = {.type = DT_INST_PROP(n, resource_type),                            \
-				.block_num = DT_INST_PROP(n, resource_instance)},                  \
-	};                                                                                         \
+				.block_num = DT_INST_PROP(n, resource_instance),                   \
+				.channel_num = DT_INST_PROP_OR(n, resource_channel, 0)},           \
+		PERI_CLOCK_INIT(n)};                                                               \
                                                                                                    \
 	DEVICE_DT_INST_DEFINE(n, &ifx_cat1_peri_clock_init, NULL, &ifx_cat1_peri_clock##n##_data,  \
 			      NULL, PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL);

drivers/i2s/CMakeLists.txt

@@ -9,6 +9,7 @@ zephyr_library_sources(i2s_common.c)
 # zephyr-keep-sorted-start
 zephyr_library_sources_ifdef(CONFIG_I2S_AMBIQ i2s_ambiq.c)
 zephyr_library_sources_ifdef(CONFIG_I2S_ESP32 i2s_esp32.c)
+zephyr_library_sources_ifdef(CONFIG_I2S_INFINEON i2s_ifx_cat1_pdl.c)
 zephyr_library_sources_ifdef(CONFIG_I2S_LITEX i2s_litex.c)
 zephyr_library_sources_ifdef(CONFIG_I2S_MCUX_FLEXCOMM i2s_mcux_flexcomm.c)
 zephyr_library_sources_ifdef(CONFIG_I2S_MCUX_SAI i2s_mcux_sai.c)

drivers/i2s/Kconfig.ifx_cat1

@@ -0,0 +1,27 @@
+# Infineon CAT1 I2S configuration options
+
+# Copyright (c) 2025 Infineon Technologies AG,
+# or an affiliate of Infineon Technologies AG.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config I2S_INFINEON
+	bool "Infineon CAT1 I2S driver"
+	default y
+	depends on DT_HAS_INFINEON_I2S_ENABLED
+	select USE_INFINEON_I2S
+	select PINCTRL
+	help
+	  This option enables the I2S driver.
+
+if I2S_INFINEON
+
+config I2S_INFINEON_RX_QUEUE_SIZE
+	int "RX queue length"
+	default 8
+
+config I2S_INFINEON_TX_QUEUE_SIZE
+	int "TX queue length"
+	default 8
+
+endif # I2S_INFINEON