x86-64 Virtual Address Translator in Rust

A simple command-line program written in Rust to simulate the x86-64 4-level paging mechanism, converting a virtual memory address into its corresponding physical memory address.

About The Project

Modern operating systems use virtual memory to provide security, stability, and flexibility. The CPU doesn't access RAM directly; instead, it uses virtual addresses that are translated into physical addresses by the Memory Management Unit (MMU). On the x86-64 architecture, this translation is typically done via a four-level page table hierarchy.

This project is an educational tool designed to demystify this process. It provides a clear, hands-on simulation of how the CPU "walks" the page tables—from the PML4 down to the final Page Table—to resolve a physical address. It is not an OS component but a standalone simulation running in user space.

Key Features

• Simulates the 4-level paging hierarchy: PML4, PDPT, Page Directory, and Page Table.
• Parses a 48-bit virtual address into its constituent indices and offset.
• Walks the page table structures to find the corresponding physical page frame.
• Demonstrates manual, page-aligned memory allocation in Rust to represent the simulated physical RAM.

How It Works

The translation process follows the rules of the x86-64 architecture:

1. Virtual Address Breakdown: A 48-bit virtual address is split into five parts:

   • Bits 39-47: A 9-bit index for the PML4 table.
   • Bits 30-38: A 9-bit index for the Page Directory Pointer Table (PDPT).
   • Bits 21-29: A 9-bit index for the Page Directory (PD).
   • Bits 12-20: A 9-bit index for the Page Table (PT).
   • Bits 0-11: A 12-bit offset within the final physical page frame.

2. Page Table Walk: The simulation begins with the physical address of the PML4 table (which would normally be stored in the CR3 register).

   • It uses the PML4 index to find an entry in the PML4 table. This entry points to the physical address of a PDPT.
   • It then uses the PDPT index to find an entry in that PDPT, which points to a Page Directory.
   • This process is repeated for the Page Directory and the Page Table.

3. Final Calculation: The final entry in the Page Table points to the physical address of a 4 KiB Page Frame. The 12-bit offset from the virtual address is added to this base address to get the final physical address.

Click to see a visual diagram of the process

graph TD
    subgraph "CPU & Virtual Address"
        VA[Virtual Address<br/>0x201ABC]
        VA_PARTS["| PML4 Index: 0 | PDPT Index: 0 | PD Index: 1 | PT Index: 1 | Offset: 0xABC |"]
        CR3["CR3 Register<br/>(Physical address of PML4: 0x1000)"]
        VA --> VA_PARTS
    end

    subgraph "Physical Memory (Simulated RAM)"
        PML4["<b>1. PML4 Table</b><br/>(at address 0x1000)<br/> ... <br/> Entry[0] points to 0x2000 <br/> ..."]
        PDPT["<b>2. PDPT</b><br/>(at address 0x2000)<br/> ... <br/> Entry[0] points to 0x3000 <br/> ..."]
        PD["<b>3. Page Directory</b><br/>(at address 0x3000)<br/> ... <br/> Entry[1] points to 0x4000 <br/> ..."]
        PT["<b>4. Page Table</b><br/>(at address 0x4000)<br/> ... <br/> Entry[1] points to 0x8000 <br/> ..."]
        PF["<b>5. Page Frame</b><br/>(at address 0x8000)"]
    end

    subgraph "Final Calculation"
        PA[Final Physical Address<br/><b>0x8ABC</b>]
    end

    %% Connections
    CR3 -- "Initiates lookup at" --> PML4
    VA_PARTS -- "PML4 Index [0]" --> PML4
    PML4 -- "Follows the pointer" --> PDPT
    VA_PARTS -- "PDPT Index [0]" --> PDPT
    PDPT -- "Follows the pointer" --> PD
    VA_PARTS -- "PD Index [1]" --> PD
    PD -- "Follows the pointer" --> PT
    VA_PARTS -- "PT Index [1]" --> PT
    PT -- "Finds the Page Frame address" --> PF

    PF -- "Page Frame Address (0x8000)" --> PA
    VA_PARTS -- "Offset (0xABC)" --> PA

Loading

Note: If the diagram above does not render correctly, you can copy the code into an online renderer like the Mermaid Live Editor.

When you run

You should see the following output, demonstrating the successful translation of the hardcoded virtual address:

Attempting to translate virtual address: 0x201abc

Success!
  Virtual Address:  0x201abc
  -> Physical Address: 0x8abc

Code Overview

• main.rs: The main application file. It contains:
  • Data Structures: PageTableFlags, PageTableEntry, and PageTable structs that model the paging structures.
  • Translation Logic: The translate_virtual_to_physical function, which performs the core page table walk.
  • Simulation Setup: The main function, which allocates aligned memory for our simulated RAM and sets up the page table hierarchy for the demonstration.