[Feature] Support the link overrides between dataSPM and tiles.

[BenkangPeng]

This PR supports the link overrides between dataSPM and tiles.

[tancheng]

Using -1 to indicate SPM sounds fine to me. However, how we decide which tile connects to SPM at beginning? i.e., which ones connects/existence are true?

CgraRTL.py has the left and bottom tiles connecting to SPM:

VectorCGRA/cgra/CgraRTL.py

Lines 249 to 253 in 87ab489

	if i % width == 0 or i // width == 0:
	s.tile[i].to_mem_raddr //= s.data_mem.recv_raddr[width + i // width - 1 if i >= width else i % width]
	s.tile[i].from_mem_rdata //= s.data_mem.send_rdata[width + i // width - 1 if i >= width else i % width]
	s.tile[i].to_mem_waddr //= s.data_mem.recv_waddr[width + i // width - 1 if i >= width else i % width]
	s.tile[i].to_mem_wdata //= s.data_mem.recv_wdata[width + i // width - 1 if i >= width else i % width]

However, we don't have such default connections in arch.yaml or CgraTemplateRTL. How should we make such connections as default, but leveraging your -1 with existence: false to remove the connect?

[tancheng]

else:#cgra_idx_x = 0 -> else: #cgra_idx_x == 0

[tancheng]

Instead of rows, can we initialize SPM ports with

VectorCGRA/cgra/CgraRTL.py

Lines 70 to 71 in 87ab489

	data_mem_num_rd_tiles = height + width - 1
	data_mem_num_wr_tiles = height + width - 1