[Feature] Enable picking the simplest cgra from multi-cgras for the following synthesis and layout.

[BenkangPeng]

This PR enables picking the simplest cgra(which has the least number of FUs) for testing, verilog-generating and the following synthesis and layout.

[BenkangPeng]

The functionality has been verified:
MeshMultiCgraTemplateRTL_test.py::test_simplified_multi_cgra generated the verilog: CgraTemplateRTL_pickled.txt with arch_override.yaml:

tile_defaults:
  num_registers: 16
  fu_types: ["add", "mul", "div", "fadd", "fmul", "fdiv", "logic", "cmp", "sel", "type_conv", "vfmul", "fadd_fadd", "fmul_fadd", "grant", "loop_control", "phi", "constant", "mem", "return", "mem_indexed", "alloca", "shift"]
tile_overrides:
- cgra_x: 0
  cgra_y: 0
  tile_x: 0
  tile_y: 1
  fu_types: ["add", "mem"]
  existence: true

We can observe that the generated CGRA's tile (0,1) only contains AdderRTL and MemUnitRTL, which indicates that test_simplified_multi_cgra has selected the simplest CGRA.