feat: Enable MemUnit Fusion in Combo FUs

[yuqisun]

• Added SeqAdderMemRTL test to validate memory interface propagation in combo FUs.
• Introduced design document outlining the context, goals, and decisions for enabling MemUnit fusion.
• Updated TileRTL to detect and connect memory ports for combo FUs containing MemUnitRTL.
• Modified functional unit classes (TwoSeqCombo, TwoPrlCombo, ThreeCombo, FourCombo) to propagate memory signals using OR logic.
• Created specifications for functional units to ensure proper memory interface behavior.
• Implemented tests to verify that combo FUs with MemUnit are correctly detected and connected in TileRTL.

[yuqisun]

Hi @tancheng ,

Can ignore this PR for now, testing Spec-Driven Development to see if it can handle and help us accelerate dev.

Thanks,

[Copilot]

Pull request overview

This PR enables MemUnit fusion in combo functional units by allowing combo FUs to propagate memory interface signals from their internal components. Previously, combo FUs forced memory ports to zero, preventing useful fusion patterns like address computation combined with memory loads.

Key changes:

• Modified combo FU classes (TwoSeqCombo, TwoPrlCombo, ThreeCombo, FourCombo) to propagate memory signals using OR logic instead of tying them to zero
• Updated TileRTL to detect combo FUs containing MemUnitRTL via a helper function and class attributes
• Added SeqAdderMemRTL as an example combo FU with MemUnit, including comprehensive tests

Reviewed changes

Copilot reviewed 18 out of 18 changed files in this pull request and generated no comments.

Show a summary per file

File	Description
tile/TileRTL.py	Added _fu_contains_mem_unit helper function and updated memory port connection logic to detect combo FUs with MemUnit
tile/test/TileRTL_test.py	Added test_tile_combo_fu_with_memunit to verify combo FUs with MemUnit are properly detected and connected
fu/basic/TwoSeqCombo.py	Replaced hardcoded zero memory ports with OR-based propagation from internal FUs
fu/basic/TwoPrlCombo.py	Replaced hardcoded zero memory ports with OR-based propagation from internal FUs
fu/basic/ThreeCombo.py	Replaced hardcoded zero memory ports with OR-based propagation from internal FUs
fu/basic/FourCombo.py	Replaced hardcoded zero memory ports with OR-based propagation from internal FUs
fu/double/SeqAdderMemRTL.py	Created combo FU combining AdderRTL and MemUnitRTL with contains_mem_unit class attribute
fu/double/test/SeqAdderMemRTL_test.py	Added unit tests for SeqAdderMemRTL including memory interface validation
openspec/*	Added design documentation, specifications, and task tracking for the MemUnit fusion feature

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