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Merged
fpistm merged 4 commits into from
Dec 6, 2025
Merged

chore(wl3): update to latest STM32CubeWL3 v1.3.1 #2869

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68f4949
system(wl3) update STM32WL3x HAL Drivers to v1.3.1
fpistm Dec 5, 2025
a60b18f
system(wl3): update STM32WL3x CMSIS Drivers to v1.3.1
fpistm Dec 5, 2025
4418057
fix(wl3): HAL and LL warnings
fpistm Sep 23, 2025
b9131c2
feat(wl3): add __libc_init_array call to startup
fpistm Sep 23, 2025
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56 changes: 56 additions & 0 deletions system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h
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Expand Up @@ -4042,6 +4042,7 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */
/* ============================================================================================================================*/
/*===================== SPI =====================*/
/* ============================================================================================================================*/
#define SPI_I2S_SUPPORT /*!< I2S support */

/* ===================================================== CR1 =====================================================*/
#define SPI_CR1_BIDIMODE_Pos (15UL) /*!<SPI CR1: BIDIMODE (Bit 15) */
Expand Down Expand Up @@ -4255,6 +4256,59 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */
#define SPI_TXCRCR_TXCRC_14 (0x4000U << SPI_TXCRCR_TXCRC_Pos)
#define SPI_TXCRCR_TXCRC_15 (0x8000U << SPI_TXCRCR_TXCRC_Pos)

/* ===================================================== I2SCFGR =====================================================*/
#define SPI_I2SCFGR_ASTRTEN_Pos (12UL) /*!<SPI I2SCFGR: ASTRTEN (Bit 12) */
#define SPI_I2SCFGR_ASTRTEN_Msk (0x1000UL) /*!< SPI I2SCFGR: ASTRTEN (Bitfield-Mask: 0x01) */
#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
#define SPI_I2SCFGR_I2SMOD_Pos (11UL) /*!<SPI I2SCFGR: I2SMOD (Bit 11) */
#define SPI_I2SCFGR_I2SMOD_Msk (0x800UL) /*!< SPI I2SCFGR: I2SMOD (Bitfield-Mask: 0x01) */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
#define SPI_I2SCFGR_I2SE_Pos (10UL) /*!<SPI I2SCFGR: I2SE (Bit 10) */
#define SPI_I2SCFGR_I2SE_Msk (0x400UL) /*!< SPI I2SCFGR: I2SE (Bitfield-Mask: 0x01) */
#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
#define SPI_I2SCFGR_I2SCFG_Pos (8UL) /*!<SPI I2SCFGR: I2SCFG (Bit 8) */
#define SPI_I2SCFGR_I2SCFG_Msk (0x300UL) /*!< SPI I2SCFGR: I2SCFG (Bitfield-Mask: 0x03) */
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos)
#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos)
#define SPI_I2SCFGR_PCMSYNC_Pos (7UL) /*!<SPI I2SCFGR: PCMSYNC (Bit 7) */
#define SPI_I2SCFGR_PCMSYNC_Msk (0x80UL) /*!< SPI I2SCFGR: PCMSYNC (Bitfield-Mask: 0x01) */
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
#define SPI_I2SCFGR_I2SSTD_Pos (4UL) /*!<SPI I2SCFGR: I2SSTD (Bit 4) */
#define SPI_I2SCFGR_I2SSTD_Msk (0x30UL) /*!< SPI I2SCFGR: I2SSTD (Bitfield-Mask: 0x03) */
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos)
#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos)
#define SPI_I2SCFGR_CKPOL_Pos (3UL) /*!<SPI I2SCFGR: CKPOL (Bit 3) */
#define SPI_I2SCFGR_CKPOL_Msk (0x8UL) /*!< SPI I2SCFGR: CKPOL (Bitfield-Mask: 0x01) */
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
#define SPI_I2SCFGR_DATLEN_Pos (1UL) /*!<SPI I2SCFGR: DATLEN (Bit 1) */
#define SPI_I2SCFGR_DATLEN_Msk (0x6UL) /*!< SPI I2SCFGR: DATLEN (Bitfield-Mask: 0x03) */
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos)
#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos)
#define SPI_I2SCFGR_CHLEN_Pos (0UL) /*!<SPI I2SCFGR: CHLEN (Bit 0) */
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL) /*!< SPI I2SCFGR: CHLEN (Bitfield-Mask: 0x01) */
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk

/* ===================================================== I2SPR =====================================================*/
#define SPI_I2SPR_MCKOE_Pos (9UL) /*!<SPI I2SPR: MCKOE (Bit 9) */
#define SPI_I2SPR_MCKOE_Msk (0x200UL) /*!< SPI I2SPR: MCKOE (Bitfield-Mask: 0x01) */
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
#define SPI_I2SPR_ODD_Pos (8UL) /*!<SPI I2SPR: ODD (Bit 8) */
#define SPI_I2SPR_ODD_Msk (0x100UL) /*!< SPI I2SPR: ODD (Bitfield-Mask: 0x01) */
#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
#define SPI_I2SPR_I2SDIV_Pos (0UL) /*!<SPI I2SPR: I2SDIV (Bit 0) */
#define SPI_I2SPR_I2SDIV_Msk (0xffUL) /*!< SPI I2SPR: I2SDIV (Bitfield-Mask: 0xff) */
#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
#define SPI_I2SPR_I2SDIV_0 (0x1U << SPI_I2SPR_I2SDIV_Pos)
#define SPI_I2SPR_I2SDIV_1 (0x2U << SPI_I2SPR_I2SDIV_Pos)
#define SPI_I2SPR_I2SDIV_2 (0x4U << SPI_I2SPR_I2SDIV_Pos)
#define SPI_I2SPR_I2SDIV_3 (0x8U << SPI_I2SPR_I2SDIV_Pos)
#define SPI_I2SPR_I2SDIV_4 (0x10U << SPI_I2SPR_I2SDIV_Pos)
#define SPI_I2SPR_I2SDIV_5 (0x20U << SPI_I2SPR_I2SDIV_Pos)
#define SPI_I2SPR_I2SDIV_6 (0x40U << SPI_I2SPR_I2SDIV_Pos)
#define SPI_I2SPR_I2SDIV_7 (0x80U << SPI_I2SPR_I2SDIV_Pos)


/* ============================================================================================================================*/
Expand Down Expand Up @@ -11373,6 +11427,8 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI3)

/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI3))

/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Expand Down
2 changes: 1 addition & 1 deletion system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3x.h
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Expand Up @@ -89,7 +89,7 @@
*/
#define __STM32WL3x_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32WL3x_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32WL3x_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WL3x_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32WL3x_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WL3x_CMSIS_VERSION ((__STM32WL3x_CMSIS_VERSION_MAIN << 24U)\
|(__STM32WL3x_CMSIS_VERSION_SUB1 << 16U)\
Expand Down
61 changes: 43 additions & 18 deletions system/Drivers/CMSIS/Device/ST/STM32WL3x/Release_Notes.html
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Expand Up @@ -60,11 +60,35 @@ <h1 id="purpose">Purpose</h1>
<section id="update-history" class="col-sm-12 col-lg-8">
<h1>Update history</h1>
<div class="collapse">
<input type="checkbox" id="collapse-section5" checked aria-hidden="true">
<input type="checkbox" id="collapse-section6" checked aria-hidden="true">
<label for="collapse-section6" aria-hidden="true"> <strong>V1.3.1 /
20-November-2025</strong> </label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>Added missing I2S support on WL3Rx devices (stm32wl3rx.h)</li>
</ul>
<h2 id="known-limitations">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
<h2 id="development-toolchains-and-compilers">Development Toolchains and
Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
</ul>
<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
<ul>
<li>STM32WL3xx devices</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true">
<label for="collapse-section5" aria-hidden="true"> <strong>V1.3.0 /
29-October-2025</strong> </label>
<div>
<h2 id="main-changes">Main Changes</h2>
<h2 id="main-changes-1">Main Changes</h2>
<ul>
<li>Added support to STM32WL3Rx product line.</li>
<li>[LCSC] LCSC_VER register removed from the accessible register list,
Expand All @@ -74,16 +98,17 @@ <h2 id="main-changes">Main Changes</h2>
<li>[MRSUBG] RSSI_FLT bit #3 renamed to
<code>FREEZE_SYNC_ON_SYNC_OOK_PEAK_DECAY</code></li>
</ul>
<h2 id="known-limitations">Known Limitations</h2>
<h2 id="known-limitations-1">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
<h2 id="development-toolchains-and-compilers">Development Toolchains and
Compilers</h2>
<h2 id="development-toolchains-and-compilers-1">Development Toolchains
and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
</ul>
<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
<h2 id="supported-devices-and-boards-1">Supported Devices and
boards</h2>
<ul>
<li>STM32WL3xx devices</li>
</ul>
Expand All @@ -94,7 +119,7 @@ <h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
<label for="collapse-section3" aria-hidden="true"> <strong>V1.2.0 /
04-June-2025</strong> </label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Documentation based on jQuery 1.7.1 removed</li>
</ul>
Expand All @@ -104,17 +129,17 @@ <h2 id="contents">Contents</h2>
<li>Renamed some interrupt to improve clarity and consistency</li>
<li>Added FQCY_BAND_ID bits definition for RF_INFO_OUT register</li>
</ul>
<h2 id="known-limitations-1">Known Limitations</h2>
<h2 id="known-limitations-2">Known Limitations</h2>
<ul>
<li>CMSIS devices files are delivered “as is” and have not been fully
validated</li>
</ul>
<h2 id="development-toolchains-and-compilers-1">Development Toolchains
<h2 id="development-toolchains-and-compilers-2">Development Toolchains
and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
</ul>
<h2 id="supported-devices-and-boards-1">Supported Devices and
<h2 id="supported-devices-and-boards-2">Supported Devices and
boards</h2>
<ul>
<li>STM32WL3xx devices</li>
Expand All @@ -126,7 +151,7 @@ <h2 id="supported-devices-and-boards-1">Supported Devices and
<label for="collapse-section2" aria-hidden="true"> <strong>V1.1.0 /
05-February-2025</strong> </label>
<div>
<h2 id="main-changes-2">Main Changes</h2>
<h2 id="main-changes-3">Main Changes</h2>
<h3 id="release">Release</h3>
<ul>
<li>Release of CMSIS for STM32WL3xx devices</li>
Expand All @@ -135,17 +160,17 @@ <h2 id="contents-1">Contents</h2>
<ul>
<li>CMSIS devices files for STM32WL3xx</li>
</ul>
<h2 id="known-limitations-2">Known Limitations</h2>
<h2 id="known-limitations-3">Known Limitations</h2>
<ul>
<li>CMSIS devices files are delivered “as is” and have not been fully
validated</li>
</ul>
<h2 id="development-toolchains-and-compilers-2">Development Toolchains
<h2 id="development-toolchains-and-compilers-3">Development Toolchains
and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
</ul>
<h2 id="supported-devices-and-boards-2">Supported Devices and
<h2 id="supported-devices-and-boards-3">Supported Devices and
boards</h2>
<ul>
<li>STM32WL3xx devices</li>
Expand All @@ -157,7 +182,7 @@ <h2 id="supported-devices-and-boards-2">Supported Devices and
<label for="collapse-section1" aria-hidden="true"> <strong>V1.0.0 /
30-October-2024</strong> </label>
<div>
<h2 id="main-changes-3">Main Changes</h2>
<h2 id="main-changes-4">Main Changes</h2>
<h3 id="first-release">First Release</h3>
<ul>
<li>First Official Release of CMSIS for STM32WL33x devices</li>
Expand All @@ -166,17 +191,17 @@ <h2 id="contents-2">Contents</h2>
<ul>
<li>CMSIS devices files for STM32WL33x</li>
</ul>
<h2 id="known-limitations-3">Known Limitations</h2>
<h2 id="known-limitations-4">Known Limitations</h2>
<ul>
<li>CMSIS devices files are delivered “as is” and have not been fully
validated</li>
</ul>
<h2 id="development-toolchains-and-compilers-3">Development Toolchains
<h2 id="development-toolchains-and-compilers-4">Development Toolchains
and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
</ul>
<h2 id="supported-devices-and-boards-3">Supported Devices and
<h2 id="supported-devices-and-boards-4">Supported Devices and
boards</h2>
<ul>
<li>STM32WL33x devices</li>
Expand Down
2 changes: 1 addition & 1 deletion system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
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Expand Up @@ -23,7 +23,7 @@
* STM32WB0: 1.4.0
* STM32WBA: 1.8.0
* STM32WL: 1.3.0
* STM32WL3: 1.3.0
* STM32WL3: 1.3.1

Release notes of each STM32YYxx CMSIS available here:

Expand Down
2 changes: 1 addition & 1 deletion system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h
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Expand Up @@ -49,7 +49,7 @@ extern "C" {
*/
#define __STM32WL3X_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32WL3X_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32WL3X_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WL3X_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32WL3X_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WL3X_HAL_VERSION ((__STM32WL3X_HAL_VERSION_MAIN << 24U)\
|(__STM32WL3X_HAL_VERSION_SUB1 << 16U)\
Expand Down
18 changes: 12 additions & 6 deletions system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h
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Expand Up @@ -53,18 +53,20 @@ extern "C" {
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#if defined (I2C1) || defined (I2C2)
#if defined (I2C1)
#define I2C_FASTMODEPLUS_PA0 SYSCFG_I2C_FMP_CTRL_I2C1_PA0_FMP /*!< Enable Fast Mode Plus on PA0 */
#define I2C_FASTMODEPLUS_PA1 SYSCFG_I2C_FMP_CTRL_I2C1_PA1_FMP /*!< Enable Fast Mode Plus on PA1 */
#define I2C_FASTMODEPLUS_PB6 SYSCFG_I2C_FMP_CTRL_I2C1_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_I2C_FMP_CTRL_I2C1_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define I2C_FASTMODEPLUS_PB10 SYSCFG_I2C_FMP_CTRL_I2C1_PB10_FMP /*!< Enable Fast Mode Plus on PB10 */
#define I2C_FASTMODEPLUS_PB11 SYSCFG_I2C_FMP_CTRL_I2C1_PB11_FMP /*!< Enable Fast Mode Plus on PB11 */
#endif /* I2C1 */
#if defined(I2C2)
#define I2C_FASTMODEPLUS_PA6 SYSCFG_I2C_FMP_CTRL_I2C2_PA6_FMP /*!< Enable Fast Mode Plus on PA6 */
#define I2C_FASTMODEPLUS_PA7 SYSCFG_I2C_FMP_CTRL_I2C2_PA7_FMP /*!< Enable Fast Mode Plus on PA7 */
#define I2C_FASTMODEPLUS_PA13 SYSCFG_I2C_FMP_CTRL_I2C2_PA13_FMP /*!< Enable Fast Mode Plus on PA13 */
#define I2C_FASTMODEPLUS_PA14 SYSCFG_I2C_FMP_CTRL_I2C2_PA14_FMP /*!< Enable Fast Mode Plus on PA14 */
#endif /* I2C1 || I2C2 */
#endif /* I2C2 */
/**
* @}
*/
Expand Down Expand Up @@ -128,18 +130,22 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);

#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)

#if defined(I2C1) || defined(I2C2)
#if defined(I2C1)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ( \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA0)) == I2C_FASTMODEPLUS_PA0) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA1)) == I2C_FASTMODEPLUS_PA1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB10)) == I2C_FASTMODEPLUS_PB10) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB11)) == I2C_FASTMODEPLUS_PB11) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB11)) == I2C_FASTMODEPLUS_PB11) )
#endif /* I2C1 */

#if defined(I2C2)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ( \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA6)) == I2C_FASTMODEPLUS_PA6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA7)) == I2C_FASTMODEPLUS_PA7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA13)) == I2C_FASTMODEPLUS_PA13) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA14)) == I2C_FASTMODEPLUS_PA14))
#endif /* I2C1 || I2C2 */
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA14)) == I2C_FASTMODEPLUS_PA14) )
#endif /* I2C2 */

/**
* @}
Expand Down
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