VerilogWrapper and Standard Library #87

unlsycn · 2025-10-10T09:57:13Z

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Copilot

Pull request overview

This pull request introduces VerilogWrapper functionality for instantiating external Verilog modules, reorganizes the standard library package structure, and adds various API improvements including Queue implementation, type utilities, and width query methods.

Key Changes:

Adds VerilogWrapper trait and API for external Verilog module integration with parameter passing support
Refactors package structure: me.jiuyang.zaozi.testlib → me.jiuyang.testlib and me.jiuyang.zaozi.stdlib → me.jiuyang.stdlib
Implements Queue with DesignWare Building Blocks backend, Decoupled interface, and type conversion utilities

Reviewed changes

Copilot reviewed 63 out of 69 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
zaozi/src/Api.scala	Adds VerilogWrapper trait, VerilogParameter, and VerilogWrapperApi; adds GetWidth trait for querying bit widths
zaozi/src/default/VerilogWrapperApi.scala	Implements VerilogWrapper API with extmodule creation and instantiation support
zaozi/src/default/BaseGeneratorApi.scala	Extracts common instance creation and MLIR bytecode dumping logic into BaseGeneratorHelper
zaozi/src/magic/macros/Generator.scala	Updates @Generator macro to support both Generator and VerilogWrapper traits
stdlib/src/dwbb/Queue.scala	Adds DwbbFifo VerilogWrapper for DW_fifo_s1_sf with QueueImpl given instance
stdlib/src/Decoupled.scala	Adds DecoupledIO and ValidIO interfaces with HasFire trait
stdlib/src/TypeUtils.scala	Adds HardwareDataType alias and TypeUtilsApi for asBits/asTypeOf conversions
testlib/src/ZaoziTest.scala	Updates package from me.jiuyang.zaozi.testlib to me.jiuyang.testlib
.scalafix.conf	Adds Scalafix configuration for import organization and code style rules

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.scalafix.conf

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

Copilot

Pull request overview

Copilot reviewed 51 out of 54 changed files in this pull request and generated 10 comments.

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Copilot · 2026-01-06T06:38:13Z

zaozi/src/default/MonoConnect.scala

 import java.lang.foreign.Arena

 // TODO: split LHS & RHS into two different trait? this might help for Vec static accessing assignment.
+// TODO: Const cannot be SINK


The TODO comment on line 15 suggests using "Const" when it should probably say "Const cannot be SINK" or clarify that constants cannot be used as sink (left-hand side) in assignments. The current phrasing "Const cannot be SINK" is unclear - consider expanding this to "TODO: Constants should not be allowed as assignment targets (SINK)".

Copilot · 2026-01-06T06:38:13Z

zaozi/src/magic/macros/Generator.scala

          // a bit of dirty but quotes does not expose the SingletonTypeTree
          if selfOpt.exists(_.tpt.toString().startsWith("SingletonTypeTree")) =>


The comment about "a bit of dirty but quotes does not expose the SingletonTypeTree" on line 19 contains a grammatical error. It should be "a bit dirty" (without "of") or "a bit of a hack".

zaozi/src/Api.scala

Copilot · 2026-01-06T06:38:14Z

stdlib/src/dwbb/Queue.scala

+  ): Wire[QueueIO[D]] =
+    val fifo    = DwbbFifo.instantiate(
+      DwbbFifoParameter(
+        // XXX: any way not to actually create an op?


The comment on lines 93-94 uses a non-standard comment format "XXX:" which typically indicates a critical issue or temporary workaround. Consider using "TODO:" or "FIXME:" for consistency with the rest of the codebase, or clarify what "XXX" means in this context.

Suggested change

// XXX: any way not to actually create an op?

// TODO: Find a way not to actually create an op here, if possible.

circtlib/src/capi/dialect/firrtl/given_AttributeApi.scala

Copilot · 2026-01-06T06:38:14Z

zaozi/src/Api.scala

+trait GetWidth[D <: Data, R <: Referable[D]]:
+  extension (ref: R)
+    def width(
+      using Arena,
+      Context
+    ): Int


The width method is added to several APIs (BitsApi, BoolApi, UIntApi, SIntApi, RecordApi, BundleApi, VecApi) but not documented. Consider adding scaladoc comments explaining what the width method returns, especially since it's a new public API that users will interact with.

Copilot · 2026-01-06T06:38:14Z

zaozi/src/reftpe/Referable.scala

+  // Ideally, we can get all attribute from MLIR but the Scala type itself
+  def getType = _tpe


The getType and getElementType methods are newly exposed public APIs but lack documentation. These methods expose internal implementation details (_tpe, _elementType) and should have clear documentation explaining their purpose, return values, and when users should call them.

zaozi/src/default/VerilogWrapperApi.scala

Copilot · 2026-01-06T06:38:15Z

zaozi/src/Api.scala

+  def moduleName(parameter: PARAM): String =
+    s"${verilogModuleName(parameter)}_${verilogParameter(parameter).hashCode.toHexString}"


The moduleName implementation uses hashCode.toHexString to ensure uniqueness based on verilog parameters. However, hashCode can have collisions - two different VerilogParameter instances could potentially have the same hashCode, leading to module name conflicts. Consider using a more robust mechanism like a cryptographic hash or a counter-based approach for generating unique module names.

Copilot · 2026-01-06T06:38:15Z

zaozi/src/valuetpe/Vec.scala

  private[zaozi] val _elementType: E
  private[zaozi] val _count:       Int

+  def getElementType = _elementType


The getElementType method is exposed but lacks documentation. Users need to understand what this method returns and when it should be used.

unlsycn force-pushed the stdlib branch from 26b0dcd to 076d5a0 Compare October 10, 2025 09:58

unlsycn marked this pull request as draft October 10, 2025 09:59

unlsycn force-pushed the stdlib branch 3 times, most recently from c12df9c to 4301af5 Compare October 12, 2025 06:08

unlsycn force-pushed the stdlib branch from 4301af5 to c378619 Compare December 22, 2025 00:53

unlsycn force-pushed the stdlib branch 2 times, most recently from a23f9de to 80f55b5 Compare January 4, 2026 13:58

unlsycn changed the title ~~[WIP] Standard Library~~ [WIP] VerilogWrapper and Standard Library Jan 4, 2026

unlsycn force-pushed the stdlib branch 3 times, most recently from 243f89e to 576f339 Compare January 5, 2026 03:33

unlsycn changed the title ~~[WIP] VerilogWrapper and Standard Library~~ Bump to CIRCT 1.138.0 Jan 5, 2026

unlsycn marked this pull request as ready for review January 5, 2026 03:37

unlsycn force-pushed the stdlib branch 2 times, most recently from 6722d7a to 1802d56 Compare January 5, 2026 03:52

unlsycn changed the title ~~Bump to CIRCT 1.138.0~~ VerilogWrapper and Standard Library Jan 5, 2026

unlsycn force-pushed the stdlib branch from 1802d56 to 6714586 Compare January 5, 2026 04:02

unlsycn requested a review from Copilot January 5, 2026 04:03

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unlsycn force-pushed the stdlib branch 3 times, most recently from 678e24e to 7cd7a34 Compare January 6, 2026 03:24

unlsycn added 6 commits January 6, 2026 11:40

style: add scalafix configuration

57a75a0

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

build: move testlib and stdlib into separate packages

c7b1244

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

fix(zaozi): correct context of locate and valname

807b5b5

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

fix(dynamic): fix typo in contextual parameter summon

812b03e

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

refactor(zaozi): TypeImpl APIs should be private

be54364

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

feat(zaozi): add GetWidth API to hardware types

545524f

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

unlsycn added 8 commits January 6, 2026 11:40

feat(circtlib): implement ExtModuleApi

9bae115

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

feat(zaozi): expose some fields publicly

7a43a4e

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

feat(stdlib): add TypeUtils to handle with generic

0c02093

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

fix(circtlib): simplify getParamDeclAttribute and add boolean support

37d278f

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

feat(zaozi): implement VerilogWrapper

3dc4ac5

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

feat(stdlib): add Decoupled

ca43b81

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

feat(stdlib): implement Queue

54cc441

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

fix(generator): destructure type parameters as TypeTree

e55d0b6

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

unlsycn force-pushed the stdlib branch from cc13cac to c66b3e2 Compare January 6, 2026 03:46

unlsycn added 3 commits January 6, 2026 12:02

fix(dynamic): substitute nested type args

5f67ecb

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

test(lit): enchance MultipleInstance test

442c0b6

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

ci: enable stdlib lit tests

c66b3e2

Signed-off-by: unlsycn <unlsycn@unlsycn.com>

unlsycn requested a review from Copilot January 6, 2026 06:34

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VerilogWrapper and Standard Library #87

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		// a bit of dirty but quotes does not expose the SingletonTypeTree
		if selfOpt.exists(_.tpt.toString().startsWith("SingletonTypeTree")) =>

	// XXX: any way not to actually create an op?
	// TODO: Find a way not to actually create an op here, if possible.

		// Ideally, we can get all attribute from MLIR but the Scala type itself
		def getType = _tpe

		def moduleName(parameter: PARAM): String =
		s"${verilogModuleName(parameter)}_${verilogParameter(parameter).hashCode.toHexString}"

VerilogWrapper and Standard Library #87

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unlsycn commented Oct 10, 2025

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