[DO NOT MERGER]Revert "Add a API for querying GVT active from kernel" #24
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By the Spec all CNL Y skus are 2+2, i.e. GT2.
This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
v2: Add kernel commit id for reference.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
This got lost on rebase, I believe Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
As far as I understand, IS_9XX should return true for it. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
No functional change. Just organizing the code so it gets clear for future platforms. Paulo deserves credits becuase he was the one that just noticed this IS_9XX was in the wrong position after CNL patches got introduced. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
It is safe to submit the full struct even on older kernels as such kernels do not process the full struct. Without this change it becomes quite challenging to extned the submit struct. Freedreno has no special treatment too. See git commits - freedreno: sync uapi header - freedreno: add fence fd support Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
drmMalloc will zero out the memory for us Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
These are just wrappers using the amdgpu device handle. Acked-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This just sends chunks to the kernel API for a single command stream. This should provide a more future proof and extensible API for command submission. v2: use amdgpu_bo_list_handle, add two helper functions to access bo and context internals. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
On ChromeOS devices, readdir() processes the directory in the following order: -NAME- -TYPE- . n/a .. n/a vgem n/a card1 DRM_BUS_PLATFORM renderD129 DRM_BUS_PLATFORM card0 DRM_BUS_PCI renderD128 DRM_BUS_PCI controlD64 DRM_BUS_PCI In drmGetDevices2, after drmProcessPlatformDevice fails for /dev/dri/card1, we don't process the remaining directory entries. As such, Vulkan fails to initialize since Mesa uses drmGetDevices2. To fix this, continue if drmProcessPlatformDevice fails. Fixes: 7b1f37f ("xf86drm: Add platform and host1x bus support") Reviewed-by: Emil Velikov <emil.velikov@collabora.com> [Emil: correct the host1x platforms as well] Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Analogous to previous commit (and the rest of the codebase), simply discard the device if we cannot parse it. Fixes: f8484cc ("xf86drm: Add USB support") Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
GCC 7 started warning when a switch case has neither a `break` nor a "fallthrough" comment. Let's be explicit that we meant to fall through here. Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
raven doesn't support UVD decode Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
raven doesn't support VCE Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
`pipe` cannot be non-null, so the label reduces to a simple return. Then, there is no point initialising `pipe` just to overwrite it before anyone reads it. Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Rob Clark <robdclark@gmail.com>
`ring` cannot be non-null, so the label reduces to a simple return. Then, there is no point initialising `ring` just to overwrite it before anyone reads it. Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
there is race issue between two threads on amdgpu_bo_reference and amdgpu_bo_import, this patch tends to fix it by moving the pthread_mutex_lock out of bo_free_internal and move to bo_reference to cover the update_reference part. The mutex_unlock in bo_import should also cover bo refcount increasement. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
since bo_reference and bo_internal_free are all only used by bo_free, so we just merge them together Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher at amd.com> Acked-by: Christian König <christian.koenig@amd.com>
Fixes: 7d8c946 Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Define two macros to avoid building errors. Fixes: 7e6bf88 (amdgpu: move asic id table to a separate file) Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Look up BOs from the name table using the name parameter instead of req.handle (which at this point is always zero). Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com> Reviewed-by: Daniel Stone <daniels@collabora.com>
Taken from the drm-next pull for 4.17-rc1 (694f54f680f7), and manually
reconciled:
core:
- Dropped DRM_MODE_TYPE_ALL and DRM_MODE_FLAG_ALL; these are purely
internal details of the bits accepted by the currently running
kernel, and can not be generally relied on by userspace
- Add HDCP flags
- Note CTM entry representation is sign-magnitude format, not
two's-complement
amdgpu:
- Add QUERY_STATE2 context op
- Add VCN firmware version query
etnaviv:
- Add more GPU feature flags
i915:
- Add caps, params and ioctls for PMU / perf-stream
- Add support for explicit fencing
nouveau:
- Add TILE_COMP layout
vc4:
- Add perfmon ioctls
virtgpu:
- Add capset-fix param
vmware:
- Add handle-close ioctl and explicit-fencing support
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Nouveau has made a very deliberate choice to hide its actual kernel ABI behind libdrm. i915 is no longer out of date. Signed-off-by: Daniel Stone <daniels@collabora.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
In trying to integrate the new gralloc_handle.h with the
drm_hwcomposer, I started seeing the following compilation
errors:
In file included from external/drm_hwcomposer/platformdrmgeneric.cpp:28:
external/libdrm/android/gralloc_handle.h:108:9: error: cannot initialize return object of type 'native_handle_t *' (aka 'native_handle *') with an lvalue of type 'struct gralloc_handle_t *'
return handle;
^~~~~~
1 error generated.
This seems to be due to the gralloc_handle_create() definition
needs to return a native_handle_t * type, rather then a
gralloc_handle_t *, which is what the code actually returns.
After talking w/ Rob Herring, having the code return the
native handle should be the proper fix, so that is what
this patch changes.
Cc: Chih-Wei Huang <cwhuang@android-x86.org>
Cc: Stefan Schake <stschake@gmail.com>
Cc: Robert Foss <robert.foss@collabora.com>
Cc: Sean Paul <seanpaul@google.com>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com>
128 is the maximum number of cards that the kernel can support at the moment. Change-Id: I155b7b21635306d8ecc440b85fb8954501ab5599 Signed-off-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
Based on kernel commit '672e314b21dc ("drm/i915/kbl: Add KBL GT2 sku")'
v2: name change M -> ULX, add enumeration in KBL ULX
v3: add entry to IS_KABYLAKE
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Fixes memory leaks. Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Add the PCI IDs and the basic code to enable ICL. This is the current
PCI ID list in our documentation.
Kernel commit: d55cb4fa2cf0 ("drm/i915/icl: Add the ICL PCI IDs")
v2: Michel provided a fix to IS_9XX that was broken by rebase bot.
v3: Fix double definition of PCI IDs, update IDs according to bspec
and keep them in the same order and rebase (Lucas)
Cc: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
In mesa/gallium, a pipe_fence can outlive the pipe_context it was created from. But to wait on the fence we need to know the submit- queue (ie. the fd_pipe). The most straightforward way to fix this is to add reference counting to the fd_pipe and let the fence hold a reference to the pipe (rather than hanging on to the context, which might have been destroyed before the fence). Signed-off-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Close the file descriptors under lock as well. v2: close fds after removing from hash table Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
…tries in hash table Analogous to the mesa commit of the same name. Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Fixes memory leak on module unload. Analogous to mesa commit of the same name. Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Kishore Kadiyala <kishore.kadiyala@intel.com>
JIRA : None Test : Travis CI checks getting triggered
Export necessary header files used by other components for Android, such as libva intel-driver, gralloc, hwcomposer, etc. Signed-off-by: li zhuangzhi <zhuangzhi.li@intel.com>
Jira: None. Test: Build passes on Android and no warnings reported. Signed-off-by: renchenglei <chenglei.ren@intel.com>
access userdata is kernel feature for IPC purpose this is necesarry when usage like video deinterlace Jira: None Tests: Android boot and deinterlace video playback
Add new iris driver, remove deprecated ilo driver. Jira: None Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
remove amdgpu.ids for android which would conflict with same file in android aosp drm Change-Id: I0b7995cef552b1b21d365e045d2c564a1f8987fa Tracked-On: OAM-73497 Signed-off-by: Jenny Cao <jenny.q.cao@intel.com>
This changes help to support Virgl(Virtual 3D GPU) for guest virtual machines. Tracked-On: OAM-88714 Signed-off-by: Jin, Zhi <zhi.jin@intel.com>
Tracked-On: OAM-88729 Signed-off-by: yifang ma <yifangx.ma@intel.com>
Add a API for querying if GVT is active in kernel via the IOCTL GETPARAM Tests: Work well for both GVT-d and GVT-g Tracked-On: OAM-91485 Signed-off-by: Shaofeng Tang <shaofeng.tang@intel.com>
sysopenci
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Aug 10, 2020
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Autobuild started from pull-request-changes on this PR.
FAILURE: CheckBug Bad comments/Bugs
For more information, see: /absp/builders/celadon-autobuild/builds/2522
This reverts commit 443de4b.
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This reverts commit 443de4b.