vcpu: Handle Intel VMX limitation for intr_shadow import #1014
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Intel VMX rejects setting VM_REG_GUEST_INTR_SHADOW to non-zero values while AMD SVM accepts any value. As per [1], the interrupt shadow is transient state, cleared after one instruction. Ignore EINVAL when attempting to set intr_shadow=true on Intel, as the state loss is benign. In the worst case an interrupt arrives one instruction early. This fixes oxidecomputer#1013 [1]: Intel SDM Volume 3C, Section 26.6.1 and 27.7.1 around "Interruptibility State" https://cdrdv2-public.intel.com/825750/326019-sdm-vol-3c.pdf Signed-off-by: Amey Narkhede <ameynarkhede03@gmail.com>
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Intel VMX rejects setting
VM_REG_GUEST_INTR_SHADOWto non-zero values while AMD SVM accepts any value. As per [1], the interrupt shadow is transient state, cleared after one instruction.Ignore
EINVALwhen attempting to setintr_shadow=trueon Intel, as the state loss is benign. In the worst case an interrupt arrives one instruction early. This fixes #1013[1]: Intel SDM Volume 3C, Section 26.6.1 and 27.7.1 around
"Interruptibility State"
https://cdrdv2-public.intel.com/825750/326019-sdm-vol-3c.pdf