Fine-tune inline target_feature attributes

Yields a 12-25% performance boost for “small” (1 KiB) payloads.

Intel Sapphire Rapids is ~25%, AMD Genoa is ~15%,
Apple M3 Ultra is ~12%, and AWS Graviton 4 is ~8%.

Author: onethumb

src/algorithm.rs

@@ -29,7 +29,7 @@ use crate::{crc32, crc64};
 )]
 #[cfg_attr(
     all(target_arch = "x86_64", feature = "vpclmulqdq"),
-    target_feature(enable = "sse2,sse4.1,pclmulqdq,avx2,vpclmulqdq")
+    target_feature(enable = "avx2,vpclmulqdq,avx512f,avx512vl")
 )]
 #[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
 pub unsafe fn update<T: ArchOps, W: EnhancedCrcWidth>(
@@ -120,6 +120,10 @@ where
     any(target_arch = "x86", target_arch = "x86_64"),
     target_feature(enable = "sse2,sse4.1,pclmulqdq")
 )]
+#[cfg_attr(
+    all(target_arch = "x86_64", feature = "vpclmulqdq"),
+    target_feature(enable = "avx2,vpclmulqdq,avx512f,avx512vl")
+)]
 #[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
 unsafe fn process_large_aligned<T: ArchOps, W: EnhancedCrcWidth>(
     bytes: &[u8],

src/arch/mod.rs

@@ -33,6 +33,15 @@ pub(crate) mod x86;
 /// # Safety
 /// May use native CPU features
 #[inline]
+#[cfg_attr(
+    any(target_arch = "x86", target_arch = "x86_64"),
+    target_feature(enable = "sse2,sse4.1,pclmulqdq")
+)]
+#[cfg_attr(
+    all(target_arch = "x86_64", feature = "vpclmulqdq"),
+    target_feature(enable = "avx2,vpclmulqdq,avx512f,avx512vl")
+)]
+#[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
 pub(crate) unsafe fn update(state: u64, bytes: &[u8], params: CrcParams) -> u64 {
     #[cfg(target_arch = "aarch64")]
     {

src/structs.rs

@@ -47,6 +47,7 @@ pub struct CrcState<T> {
 pub(crate) struct Calculator {}
 
 impl CrcCalculator for Calculator {
+    #[inline(always)]
     fn calculate(state: u64, data: &[u8], params: CrcParams) -> u64 {
         unsafe { arch::update(state, data, params) }
     }