Use conditional compilation for XOR3 ops

Provides measurably better performance.

Author: onethumb

src/arch/aarch64.rs

@@ -258,20 +258,27 @@ impl ArchOps for AArch64Ops {
     }
 
     #[inline]
-    #[cfg_attr(target_feature = "sha3", target_feature(enable = "neon,sha3"))]
-    #[cfg_attr(not(target_feature = "sha3"), target_feature(enable = "neon"))]
+    #[cfg(target_feature = "sha3")]
+    #[target_feature(enable = "neon,sha3")]
     unsafe fn xor3_vectors(
         &self,
         a: Self::Vector,
         b: Self::Vector,
         c: Self::Vector,
     ) -> Self::Vector {
-        if is_aarch64_feature_detected!("sha3") {
-            // Use native 3-way XOR instruction when available
-            return veor3q_u8(a, b, c);
-        }
-
-        // Fall back to two XOR operations
+        veor3q_u8(a, b, c)
+    }
+    
+    #[inline]
+    #[cfg(not(target_feature = "sha3"))]
+    #[target_feature(enable = "neon")]
+    unsafe fn xor3_vectors(
+        &self,
+        a: Self::Vector,
+        b: Self::Vector,
+        c: Self::Vector,
+    ) -> Self::Vector {
+        // Fallback for when SHA3 is not available
         veorq_u8(veorq_u8(a, b), c)
     }
 }

src/arch/x86.rs

@@ -226,29 +226,30 @@ impl ArchOps for X86Ops {
     unsafe fn carryless_mul_11(&self, a: Self::Vector, b: Self::Vector) -> Self::Vector {
         _mm_clmulepi64_si128(a, b, 0x11)
     }
-
+    
     #[inline]
-    #[cfg_attr(
-        any(feature = "vpclmulqdq", feature = "avx512"),
-        target_feature(enable = "avx512f,avx512vl")
-    )]
-    #[cfg_attr(
-        all(not(feature = "vpclmulqdq"), not(feature = "avx512")),
-        target_feature(enable = "sse2,sse4.1")
-    )]
+    #[cfg(any(feature = "vpclmulqdq", feature = "avx512"))]
+    #[target_feature(enable = "avx512f,avx512vl")]
     unsafe fn xor3_vectors(
         &self,
         a: Self::Vector,
         b: Self::Vector,
         c: Self::Vector,
     ) -> Self::Vector {
-        #[cfg(any(feature = "vpclmulqdq", feature = "avx512"))]
-        if is_x86_feature_detected!("avx512f") && is_x86_feature_detected!("avx512vl") {
-            return _mm_ternarylogic_epi64(
-                a, b, c, 0x96, // XOR3
-            );
-        }
+        _mm_ternarylogic_epi64(
+            a, b, c, 0x96, // XOR3
+        )
+    }
 
+    #[inline]
+    #[cfg(not(any(feature = "vpclmulqdq", feature = "avx512")))]
+    #[target_feature(enable = "sse2,sse4.1")]
+    unsafe fn xor3_vectors(
+        &self,
+        a: Self::Vector,
+        b: Self::Vector,
+        c: Self::Vector,
+    ) -> Self::Vector {
         // x86 doesn't have native XOR3 in SSE, use two XORs
         _mm_xor_si128(_mm_xor_si128(a, b), c)
     }