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UART: Add input data FIFO
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‎source/comp/uart_fifo.vhd‎

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-- The MIT License (MIT)
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--
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-- Copyright (c) 2015 Jakub Cabal
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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-- SOFTWARE.
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--
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-- Website: https://github.com/jakubcabal/uart_for_fpga
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.MATH_REAL.ALL;
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entity UART_FIFO is
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Generic (
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DATA_WIDTH : integer := 8;
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FIFO_DEPTH : integer := 256
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);
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Port (
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CLK : in std_logic; -- system clock
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RST : in std_logic; -- high active synchronous reset
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-- FIFO WRITE INTERFACE
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DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
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WR_EN : in std_logic;
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FULL : out std_logic;
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-- FIFO READ INTERFACE
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DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
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DATA_VLD : out std_logic;
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RD_EN : in std_logic;
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EMPTY : out std_logic
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);
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end UART_FIFO;
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architecture FULL of UART_FIFO is
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constant addr_width : integer := integer(ceil(log2(real(FIFO_DEPTH))));
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signal wr_addr : unsigned(addr_width-1 downto 0);
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signal wr_ready : std_logic;
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signal rd_addr : unsigned(addr_width-1 downto 0);
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signal rd_ready : std_logic;
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signal full_sig : std_logic;
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signal empty_sig : std_logic;
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type bram_type is array(FIFO_DEPTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
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signal bram : bram_type := (others => (others => '0'));
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begin
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wr_ready <= WR_EN AND NOT full_sig AND NOT RST;
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rd_ready <= RD_EN AND NOT empty_sig AND NOT RST;
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FULL <= full_sig;
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EMPTY <= empty_sig;
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-- -------------------------------------------------------------------------
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-- BRAM AND DATA VALID FLAG GENERATOR
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-- -------------------------------------------------------------------------
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bram_mem : process (CLK)
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begin
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if (rising_edge(CLK)) then
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if (wr_ready = '1') then
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bram(to_integer(wr_addr)) <= DATA_IN;
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end if;
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DATA_OUT <= bram(to_integer(rd_addr));
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end if;
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end process;
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data_vld_flag_gen : process (CLK)
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begin
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if (rising_edge(CLK)) then
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DATA_VLD <= rd_ready;
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end if;
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end process;
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-- -------------------------------------------------------------------------
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-- FIFO WRITE ADDRESS COUNTER
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-- -------------------------------------------------------------------------
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wr_addr_cnt : process (CLK)
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begin
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if (rising_edge(CLK)) then
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if (RST = '1') then
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wr_addr <= (others => '0');
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elsif (wr_ready = '1') then
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wr_addr <= wr_addr + 1;
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end if;
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end if;
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end process;
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-- -------------------------------------------------------------------------
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-- FIFO READ ADDRESS COUNTER
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-- -------------------------------------------------------------------------
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rd_addr_cnt : process (CLK)
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begin
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if (rising_edge(CLK)) then
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if (RST = '1') then
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rd_addr <= (others => '0');
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elsif (rd_ready = '1') then
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rd_addr <= rd_addr + 1;
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end if;
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end if;
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end process;
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-- -------------------------------------------------------------------------
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-- FULL FLAG GENERATOR
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-- -------------------------------------------------------------------------
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full_flag_gen : process (rd_addr, wr_addr)
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begin
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if (rd_addr = (wr_addr+1)) then
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full_sig <= '1';
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else
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full_sig <= '0';
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end if;
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end process;
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-- -------------------------------------------------------------------------
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-- EMPTY FLAG GENERATOR
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-- -------------------------------------------------------------------------
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empty_flag_gen : process (rd_addr, wr_addr)
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begin
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if (rd_addr = wr_addr) then
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empty_sig <= '1';
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else
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empty_sig <= '0';
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end if;
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end process;
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end FULL;

‎source/comp/uart_fifo_testbench.vhd‎

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-- The MIT License (MIT)
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--
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-- Copyright (c) 2015 Jakub Cabal
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
6+
-- of this software and associated documentation files (the "Software"), to deal
7+
-- in the Software without restriction, including without limitation the rights
8+
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9+
-- copies of the Software, and to permit persons to whom the Software is
10+
-- furnished to do so, subject to the following conditions:
11+
--
12+
-- The above copyright notice and this permission notice shall be included in
13+
-- all copies or substantial portions of the Software.
14+
--
15+
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16+
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17+
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18+
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19+
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20+
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21+
-- SOFTWARE.
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--
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-- Website: https://github.com/jakubcabal/uart_for_fpga
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity UART_FIFO_TESTBENCH is
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end UART_FIFO_TESTBENCH;
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architecture FULL of UART_FIFO_TESTBENCH is
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signal CLK : std_logic := '0';
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signal RST : std_logic := '0';
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signal data_in : std_logic_vector(7 downto 0);
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signal wr_en : std_logic;
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signal data_out : std_logic_vector(7 downto 0);
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signal data_vld : std_logic;
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signal rd_en : std_logic;
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signal full : std_logic;
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signal empty : std_logic;
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constant clk_period : time := 20 ns;
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begin
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utt: entity work.UART_FIFO
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generic map (
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DATA_WIDTH => 8,
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FIFO_DEPTH => 32
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)
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port map (
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CLK => CLK,
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RST => RST,
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-- FIFO WRITE INTERFACE
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DATA_IN => data_in,
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WR_EN => wr_en,
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FULL => full,
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-- FIFO READ INTERFACE
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DATA_OUT => data_out,
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DATA_VLD => data_vld,
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RD_EN => rd_en,
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EMPTY => empty
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);
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clk_process : process
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begin
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CLK <= '0';
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wait for clk_period/2;
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CLK <= '1';
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wait for clk_period/2;
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end process;
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rst_process : process
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begin
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RST <= '1';
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wait for 40 ns;
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RST <= '0';
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wait;
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end process;
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read_test : process
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begin
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rd_en <= '0';
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wait until (rising_edge(CLK) and RST='0' and empty='0');
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for i in 1 to 20 loop
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rd_en <= '1';
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wait until (rising_edge(CLK) and RST='0' and empty='0');
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end loop;
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rd_en <= '0';
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wait for 800 ns;
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wait until (rising_edge(CLK) and RST='0' and empty='0');
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for i in 21 to 70 loop
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rd_en <= '1';
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wait until (rising_edge(CLK) and RST='0' and empty='0');
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end loop;
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rd_en <= '0';
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wait;
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end process;
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write_test : process
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begin
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data_in <= (others => '0');
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wr_en <= '0';
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wait until (rising_edge(CLK) and RST='0' and full='0');
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wr_en <= '1';
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for i in 1 to 11 loop
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data_in <= std_logic_vector(to_unsigned(i, data_in'length));
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wait until (rising_edge(CLK) and RST='0' and full='0');
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end loop;
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wr_en <= '0';
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wait for 200 ns;
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wait until (rising_edge(CLK) and RST='0' and full='0');
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wr_en <= '1';
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for i in 12 to 70 loop
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data_in <= std_logic_vector(to_unsigned(i, data_in'length));
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wait until (rising_edge(CLK) and RST='0' and full='0');
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end loop;
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wr_en <= '0';
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wait;
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end process;
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end FULL;

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