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Add support for Hygon Platform QoS features

Description

Hygon CPUs support Platform QoS features (PQoS Version V1.0) described
in the AMD Platform QoS specification.

The changes add Platform QoS features support for Hygon CPUs.

Affected parts

  • library
  • pqos utility
  • rdtset utility
  • other: (please specify)

Motivation and Context

Add Platform QoS features support for Hygon CPUs.

Hygon CPUs support Platform QoS features (PQoS Version V1.0) described
in the AMD Platform QoS specification [1].

Following Platform QoS sub-features are available on Hygon CPUs if the
underlying hardware supports it:

  • L3 Cache Occupancy Monitoring (CMT)
  • L3 External Memory Bandwidth Monitoring (MBM)
  • L3 Cache Allocation Enforcement (CAT)
  • Code and Data Prioritization (CDP)
  • Memory Bandwidth Enforcement/Allocation (MBA)

[1] AMD Platform QoS Extensions, Rev 1.03:
https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/other/56375_1_03_PUB.pdf

How Has This Been Tested?

  1. Passed all tests in intel-cmt-cat/unit-test on Hygon platforms.
  2. Run most pqos tests described below on Hygon platforms:
    https://github.com/intel/intel-cmt-cat/wiki/Usage-Examples

Types of changes

  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to not work as expected)

Checklist:

  • My code follows the code style of this project.
  • My change requires a change to the documentation.
  • I have updated the documentation accordingly.

From Intel RDT spec[1] and AMD Platform QoS spec[2]:
If the CPU platform supports CPUID.0FH.01H:EAX, CPUID.0FH.01H:EAX[7:0]
returns MBM counter length (width) as offset from 24.

But in hw_cap_mon_discover(), the MBM counter length is calculated with
incorrect 7-bits bitmask (0x7f).

Fix the issue with 8-bits bitmask (0xff) for MBM counter length.

[1] Intel Architectures SDM, Vol.3B, 19.18 Intel RDT Monitoring:
https://cdrdv2.intel.com/v1/dl/getContent/671200

[2] AMD Platform QoS Extensions, Rev 1.03:
https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/other/56375_1_03_PUB.pdf

Fixes: 050f8c6 ("lib: detect MBM counter length")
Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
Hygon CPUs support Platform QoS features (PQoS Version V1.0) described
in the AMD Platform QoS specification[1].

Following Platform QoS sub-features are available on Hygon CPUs if the
underlying hardware supports it:
 - L3 Cache Occupancy Monitoring (CMT)
 - L3 External Memory Bandwidth Monitoring (MBM)
 - L3 Cache Allocation Enforcement (CAT)
 - Code and Data Prioritization (CDP)
 - Memory Bandwidth Enforcement/Allocation (MBA)

[1] AMD Platform QoS Extensions, Rev 1.03:
https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/other/56375_1_03_PUB.pdf

Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
Add PQOS_VENDOR id Python interface for Hygon Platform QoS features.

Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
The default base MBM counter length (width) is 24 bits. Currently, Hygon
CPU does not support the CPUID 0xF.[ECX=1]:EAX to adjust the counter
length. But the Hygon CPU supports wider counter with the fixed width of
32 bits.

Set the default MBM counter length to 32 bit by adjusting the offset to 8
bits for Hygon.

Hygon future products will implement CPUID 0xF.[ECX=1]:EAX.

Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
@ajherdri
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Hi Xiaochen,
Thanks for the contribution! We are reviewing and will get back to you soon.
Thanks,
~Andrew

@shenxiaochen
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Author

Hi Xiaochen, Thanks for the contribution! We are reviewing and will get back to you soon. Thanks, ~Andrew

Hi Andrew,
My honor to contribute to this project again! Thank you and the team for helping review this PR.

Note: Please help review #299 as well. The code base of this PR is on top of #299 which is a trivial bug fixing.

Best regards,
Xiaochen

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Pull request overview

This PR adds Platform QoS (Quality of Service) feature support for Hygon CPUs, which implement AMD's PQoS specification v1.0. The changes enable the intel-cmt-cat library and utilities to recognize and handle Hygon processors alongside Intel and AMD processors.

Key changes:

  • Introduces a new vendor identifier PQOS_VENDOR_HYGON throughout the codebase
  • Updates vendor detection logic to identify Hygon CPUs via CPUID signature
  • Extends AMD-specific code paths to include Hygon, as Hygon follows AMD's PQoS specification
  • Implements Hygon-specific counter length handling for monitoring capabilities

Reviewed changes

Copilot reviewed 9 out of 9 changed files in this pull request and generated 3 comments.

Show a summary per file
File Description
lib/pqos.h Adds PQOS_VENDOR_HYGON enum value and updates API documentation
lib/cpuinfo.c Implements Hygon CPU detection and configuration initialization
lib/hw_cap.c Adds Hygon-specific handling for monitoring counter length
lib/cap.c Routes Hygon CPUs to AMD discovery functions for MBA capability
lib/api.c Assigns AMD-specific MBA functions for Hygon vendor
lib/python/pqos/native_struct.py Adds Python binding for PQOS_VENDOR_HYGON constant
lib/python/pqos/cpuinfo.py Adds "HYGON" string mapping for vendor identification
pqos/alloc.c Updates display logic to use AMD-style naming for Hygon
rdtset/rdt.c Extends AMD-specific MBA and display logic to include Hygon

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2 participants