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Fix fpga ddr calib #13

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Merged
ligenxxxx merged 4 commits into from
Oct 21, 2025
Merged

Fix fpga ddr calib #13

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7a35124
fix fpga ddr calib
ligenxxxx Aug 27, 2025
513ac04
optimize menu mode timing
ligenxxxx Sep 1, 2025
cdd8f45
Merge branch 'get-rtc6715-rssi-per-100/120-ms' into fix_fpga_ddr_calib
ligenxxxx Sep 1, 2025
2b3223d
Merge branch 'master' into fix_fpga_ddr_calib
ligenxxxx Oct 21, 2025
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Binary file modified mkapp/hal/HDZGOGGLE_RX.bin
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Binary file modified mkapp/hal/HDZGOGGLE_VA.bin
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2 changes: 1 addition & 1 deletion mkapp/hal/ver.txt
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Original file line number Diff line number Diff line change
@@ -1 +1 @@
77-182
76-184
5 changes: 4 additions & 1 deletion src/core/app_state.c
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Expand Up @@ -79,6 +79,7 @@ void app_exit_menu() {
}

void app_switch_to_analog() {
system_exec("aww 0x0300b084 0x00001555"); // Set vdpo clock driver strength to level 2. Refer datasheet 12.7.5.11
Analog_Module_Power(0, 1);

if (GOGGLE_VER_2) {
Expand Down Expand Up @@ -112,6 +113,7 @@ void app_switch_to_analog() {
system_script(REC_STOP_LIVE);
}
void app_switch_to_av_in() {
system_exec("aww 0x0300b084 0x00001555"); // Set vdpo clock driver strength to level 2. Refer datasheet 12.7.5.11
Analog_Module_Power(0, 0);

Source_AV(0);
Expand All @@ -134,6 +136,7 @@ void app_switch_to_av_in() {
}

void app_switch_to_hdmi_in() {
system_exec("aww 0x0300b084 0x00001555"); // Set vdpo clock driver strength to level 2. Refer datasheet 12.7.5.11
Analog_Module_Power(0, 0);

Source_HDMI_in();
Expand Down Expand Up @@ -171,7 +174,7 @@ void app_switch_to_hdmi_in() {
// false = user selected from auto scan page
void app_switch_to_hdzero(bool is_default) {
int ch;

system_exec("aww 0x0300b084 0x00001555"); // Set vdpo clock driver strength to level 2. Refer datasheet 12.7.5.11
Analog_Module_Power(0, 0);

if (is_default) {
Expand Down
13 changes: 9 additions & 4 deletions src/driver/hardware.c
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Original file line number Diff line number Diff line change
Expand Up @@ -475,7 +475,12 @@ void vclk_phase_set(video_source_t source, uint8_t reg_8d_sel) {
else
I2C_Write(ADDR_FPGA, 0x8d, (vclk_phase[source] >> 24) & 0xff);

I2C_Write(ADDR_FPGA, 0x8e, (vclk_phase[source] >> 16) & 0xff);
if (source == VIDEO_SOURCE_HDZERO_IN_720P60_50 || source == VIDEO_SOURCE_HDZERO_IN_720P90) {
I2C_Write(ADDR_FPGA, 0x8e, 0x01);
} else {
I2C_Write(ADDR_FPGA, 0x8e, (vclk_phase[source] >> 16) & 0xff);
}

I2C_Write(ADDR_AL, 0x14, (vclk_phase[source] >> 8) & 0xff);

IT66121_set_phase(vclk_phase[source] & 3, 0);
Expand Down Expand Up @@ -532,9 +537,9 @@ void pclk_phase_set(video_source_t source) {
LOGI("pclk_phase_set %d", pclk_phase[source]);
// bit[0] hdmi in
if (source == VIDEO_SOURCE_HDMI_IN_1080P50 || source == VIDEO_SOURCE_HDMI_IN_1080P60 || source == VIDEO_SOURCE_HDMI_IN_1080POTHER) {
IT66021_Set_Pclk((pclk_phase[source] >> 0) & 1, 1);
IT66021_Set_Pclk((pclk_phase[source] >> 0) & 1);
} else {
IT66021_Set_Pclk((pclk_phase[source] >> 0) & 1, 2);
IT66021_Set_Pclk((pclk_phase[source] >> 0) & 1);
}

// bit[1] analog in
Expand Down Expand Up @@ -611,7 +616,7 @@ void Display_UI_init() {
I2C_Write(ADDR_FPGA, 0x84, 0x11);

OLED_SetTMG(0);
system_exec("aww 0x0300b084 0x00015565"); // Set vdpo clock driver strength to level 2. Refer datasheet 12.7.5.11
system_exec("aww 0x0300b084 0x00002aaa"); // Set vdpo clock driver strength to level 2. Refer datasheet 12.7.5.11

if (GOGGLE_VER_2)
I2C_Write(ADDR_FPGA, 0xa7, 0x00);
Expand Down
8 changes: 2 additions & 6 deletions src/driver/it66021.c
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Expand Up @@ -340,10 +340,6 @@ void IT66021_edid() {
I2C_L_Write(0x49, 0xc0, 0x04);
}

void IT66021_Set_Pclk(int inv, int dly) {
IT66021_Mask_WR(0, 0x0f, 0x03, 0x00);
if (inv)
I2C_L_Write(ADDR_IT66021, 0x50, 0xA0 + dly);
else
I2C_L_Write(ADDR_IT66021, 0x50, 0xB0 + dly);
void IT66021_Set_Pclk(int inv) {
I2C_L_Write(ADDR_IT66021, 0x50, 0xB0);
}
2 changes: 1 addition & 1 deletion src/driver/it66021.h
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Expand Up @@ -14,7 +14,7 @@ void IT66021_Set_CSMatrix(int cs);
int IT66021_Get_PCLKFREQ();
void IT66021_edid();

void IT66021_Set_Pclk(int inv, int dly);
void IT66021_Set_Pclk(int inv);

#ifdef __cplusplus
}
Expand Down