v1.0

First release of SECDA.

Contains

• Vivado and Vivado HLS archived project folders for VM and SA accelerators

• PYNQ Z1 FPGA bitmaps for VM and SA accelerators

• Sample Input data to drive testbench simulation and for standalone accelerator unit tests

• Sample tflite models, input images and class labels

• Note: some tflite models and input images were obtained from Tensorflow hub