add delay line library #15

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karthisrinivasan wants to merge 3 commits into asyncvlsi:main from karthisrinivasan:main

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karthisrinivasan commented Dec 6, 2025

normal buffer
weak buffer
recursive asymmetric (both cases - fast-0-slow-1 and fast-1-slow-0)
2x double-reuse-of-symmetric-delay style (fast-0-slow-1 only)

karthisrinivasan added 3 commits

December 1, 2025 19:31


          export xor2 cell in treegates

0a65920


          Merge branch 'main' of https://github.com/karthisrinivasan/stdlib

e58ead5


          delay line library

d76030a

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