docs/library/spi_engine: update docs

Inserted documentation for SDI/SDO lane mask registers;
Updated Configuration Write Instruction;
Updated parameter from NUM_OF_SDI to NUM_OF_SDIO.

Signed-off-by: Carlos Souza <carlos.souza@analog.com>

Author: caosjr

docs/library/spi_engine/axi_spi_engine.rst

@@ -116,11 +116,11 @@ If an application attempts to read data while the FIFO is empty undefined data
 is returned and the state of the FIFO remains unmodified.
 It is possible to read the first entry in the SDI FIFO without removing it by
 reading from the SDI_FIFO_PEEK register.
-It is important to point out that each read represents one lane of the SPI. So,
-for ``NUM_OF_SDI`` lanes it is necessary to read ``NUM_OF_SDI`` times. Reading
+It is important to point out that each read represents one active lane of the SPI.
+So, for ``N`` active lanes it is necessary to read ``N`` times. Reading
 always starts from lane 0.
 The number of valid entries in the SDI FIFO register can be queried by reading
-the SDI_FIFO_LEVEL register. This value must be a multiple of ``NUM_OF_SDI``.
+the SDI_FIFO_LEVEL register. This value must be a multiple of ``NUM_OF_SDIO``.
 
 Data can be inserted into the SDO FIFO by writing to the SDO_FIFO register
 **only the valid lanes**. For example, if there are 4 lanes and just 2 of them

docs/library/spi_engine/control-interface.rst

@@ -76,7 +76,7 @@ Signal Pins
      - ``sdi_valid``
      - Input
      - Valid signal of the SDI stream
-   * - [(NUM_OF_SDI*DATA_WIDTH-1):0]
+   * - [(NUM_OF_SDIO*DATA_WIDTH-1):0]
      - ``sdi_data``
      - Input
      - Data signal of the SDI stream

docs/library/spi_engine/instruction-format.rst

@@ -4,7 +4,8 @@ SPI Engine Instruction Set Specification
 ================================================================================
 
 The SPI Engine instruction set is a 16-bit instruction set of which 13-bits are
-currently allocated (bits 15,11,10 are always 0).
+currently allocated (bits 15 and 11 are always 0). Bit 10 is only being used by
+the :ref:`spi_engine write-configuration-instruction`.
 
 Instructions
 --------------------------------------------------------------------------------
@@ -165,6 +166,8 @@ prescaled).
      - Chip-select
      - The new chip-select configuration.
 
+.. _spi_engine write-configuration-instruction:
+
 Configuration Write Instruction
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -192,7 +195,7 @@ Configuration Write Instruction
      - 1
      - 0
      - rv
-     - rv
+     - rg
      - rg
      - rg
      - v
@@ -222,10 +225,11 @@ with a new value.
      - Register
      - Configuration register address:
 
-       - 2'b00 = :ref:`spi_engine prescaler-configuration-register`.
-       - 2'b01 = :ref:`spi_engine spi-configuration-register`.
-       - 2'b10 = :ref:`spi_engine dynamic-transfer-length-register`.
-       - 2'b11 = :ref:`spi_engine spi-lane-mask-register`.
+       - 3'b000 = :ref:`spi_engine prescaler-configuration-register`.
+       - 3'b001 = :ref:`spi_engine spi-configuration-register`.
+       - 3'b010 = :ref:`spi_engine dynamic-transfer-length-register`.
+       - 3'b011 = :ref:`spi_engine sdi-lane-mask-register`.
+       - 3'b100 = :ref:`spi_engine sdo-lane-mask-register`.
    * - v
      - Value
      - New value for the configuration register.
@@ -471,15 +475,36 @@ bus behavior.
        - When 1, data is sampled on the trailing edge and updated on the
          leading edge.
 
+.. _spi_engine sdi-lane-mask-register:
+
+SDI Lane Mask Register
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This register configures the SDI mask that defines which lanes are active
+(active-high). The user must define a mask that contains up to ``NUM_OF_SDIO``
+lanes (the number of activated lanes cannot be bigger than the number of lanes).
+For now, it is possible to have up to 8 lanes due to the instruction size.
+
+.. list-table::
+   :widths: 10 15 50
+   :header-rows: 1
+
+   * - Bits
+     - Name
+     - Description
+   * - [7:0]
+     - SDI lane mask
+     - Only bits set to 1 have their respective lane active.
+
 
-.. _spi_engine spi-lane-mask-register:
+.. _spi_engine sdo-lane-mask-register:
 
-SPI Lane Mask Register
+SDO Lane Mask Register
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-This register configures the mask that defines which lanes are active
-(active-high). The user must define a mask that contains up to ``NUM_OF_SDI``
-lanes (the number of activated lanes cannot be bigger than the numer of lanes).
+This register configures the SDO mask that defines which lanes are active
+(active-high). The user must define a mask that contains up to ``NUM_OF_SDIO``
+lanes (the number of activated lanes cannot be bigger than the number of lanes).
 For now, it is possible to have up to 8 lanes due to the instruction size.
 
 .. list-table::
@@ -490,7 +515,7 @@ For now, it is possible to have up to 8 lanes due to the instruction size.
      - Name
      - Description
    * - [7:0]
-     - Lane mask
+     - SDO lane mask
      - Only bits set to 1 have their respective lane active.
 
 .. _spi_engine prescaler-configuration-register:

docs/library/spi_engine/spi_engine_execution.rst

@@ -40,8 +40,8 @@ Configuration Parameters
    * - DATA_WIDTH
      - Data width of the parallel data stream. Will define the transaction's
        granularity. Supported values: 8/16/24/32
-   * - NUM_OF_SDI
-     - Number of multiple SDI lines, (min: 1, max: 8)
+   * - NUM_OF_SDIO
+     - Number of multiple SDI/SDO lines, (min: 1, max: 8)
 
 Signal and Interface Pins
 --------------------------------------------------------------------------------

docs/library/spi_engine/spi_engine_interconnect.rst

@@ -40,8 +40,8 @@ Configuration Parameters
 
    * - DATA_WIDTH
      - Data width of the parallel SDI/SDO data interfaces.
-   * - NUM_OF_SDI
-     - Number of SDI lines on the physical SPI interface.
+   * - NUM_OF_SDIO
+     - Number of SDI/SDO lines on the physical SPI interface.
 
 
 Signal and Interface Pins

docs/library/spi_engine/spi_engine_offload.rst

@@ -45,8 +45,8 @@ Configuration Parameters
    * - DATA_WIDTH
      - Data width of the parallel data stream. Will define the transaction's
        granularity. Supported values: 8/16/24/32
-   * - NUM_OF_SDI
-     - Number of multiple SDI lines, (min: 1, max: 8)
+   * - NUM_OF_SDIO
+     - Number of multiple SDI/SDO lines, (min: 1, max: 8)
    * - SDO_STREAMING
      - Enables the s_axis_sdo interface. This allows for sourcing the SDO data
        stream from a DMA or other similar sources, useful for DACs.