library/spi_engine: improve SDI FIFO mode

Every read returns a valid data for an active lane. It is
not necessary to perform N reads everytime.

Signed-off-by: Carlos Souza <carlos.souza@analog.com>

Author: caosjr

library/spi_engine/axi_spi_engine/axi_spi_engine.v

@@ -136,6 +136,7 @@ module axi_spi_engine #(
   localparam PCORE_VERSION = 'h010600;
   localparam S_AXI = 0;
   localparam UP_FIFO = 1;
+  localparam max_num_of_reads = NUM_OF_SDI-1;
 
   wire clk;
   wire rstn;
@@ -157,11 +158,14 @@ module axi_spi_engine #(
   wire sdo_fifo_in_valid;
 
   wire [31:0] sdi_fifo_level;
+  reg  [NUM_OF_SDI*DATA_WIDTH/8-1:0] sdi_fifo_tkeep_int;
+  wire [NUM_OF_SDI*DATA_WIDTH/8-1:0] sdi_fifo_tkeep;
   wire sdi_fifo_almost_full;
   wire up_sdi_fifo_almost_full;
 
   wire [DATA_WIDTH-1:0] sdi_fifo_out_data;
   wire sdi_fifo_out_ready;
+  reg  find_next_valid_fifo_value;
   wire sdi_fifo_out_valid;
 
   wire [7:0] sync_fifo_data;
@@ -316,14 +320,6 @@ module axi_spi_engine #(
     end
   end
 
-  always @(posedge clk) begin
-    if (rstn == 1'b0) begin
-      up_rack_ff <= 'd0;
-    end else begin
-      up_rack_ff <= up_rreq_s;
-    end
-  end
-
   reg [7:0] offload_sdo_mem_address_width = OFFLOAD0_SDO_MEM_ADDRESS_WIDTH;
   reg [7:0] offload_cmd_mem_address_width = OFFLOAD0_CMD_MEM_ADDRESS_WIDTH;
   reg [7:0] sdi_fifo_address_width = SDI_FIFO_ADDRESS_WIDTH;
@@ -470,6 +466,20 @@ module axi_spi_engine #(
 
   assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
 
+  integer i;
+  always @(posedge spi_clk) begin
+    if (!spi_resetn) begin
+      sdi_fifo_tkeep_int <= {(NUM_OF_SDI*DATA_WIDTH/8){1'b1}};
+    end else begin
+      if (cmd_valid && cmd_data[15:8] == 8'h23) begin
+         for (i = 0; i < NUM_OF_SDI; i = i + 1) begin
+          sdi_fifo_tkeep_int[i*DATA_WIDTH/8+:DATA_WIDTH/8] <= {DATA_WIDTH/8{cmd_data[i]}};
+         end
+      end
+    end
+  end
+  assign sdi_fifo_tkeep = sdi_fifo_tkeep_int;
+
   util_axis_fifo_asym #(
     .ASYNC_CLK(ASYNC_SPI_CLK),
     .S_DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
@@ -479,7 +489,7 @@ module axi_spi_engine #(
     .ALMOST_EMPTY_THRESHOLD(1),
     .ALMOST_FULL_THRESHOLD(1),
     .TLAST_EN(0),
-    .TKEEP_EN(0),
+    .TKEEP_EN(1),
     .REDUCED_FIFO(0)
   ) i_sdi_fifo(
     .s_axis_aclk(spi_clk),
@@ -489,13 +499,13 @@ module axi_spi_engine #(
     .s_axis_data(sdi_data),
     .s_axis_room(),
     .s_axis_tlast(),
-    .s_axis_tkeep(),
+    .s_axis_tkeep(sdi_fifo_tkeep),
     .s_axis_full(),
     .s_axis_almost_full(sdi_fifo_almost_full),
 
     .m_axis_aclk(clk),
     .m_axis_aresetn(up_sw_resetn),
-    .m_axis_ready(sdi_fifo_out_ready),
+    .m_axis_ready(sdi_fifo_out_ready || find_next_valid_fifo_value),
     .m_axis_valid(sdi_fifo_out_valid),
     .m_axis_data(sdi_fifo_out_data),
     .m_axis_tlast(),
@@ -504,6 +514,41 @@ module axi_spi_engine #(
     .m_axis_empty(),
     .m_axis_almost_empty());
 
+  assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
+
+  reg [3:0] sdi_out_counter;
+  reg find_next_valid_fifo_value;
+  always @(posedge clk) begin
+    if (rstn == 1'b0) begin
+      up_rack_ff <= 'd0;
+    end else begin
+      if (sdi_fifo_out_ready || find_next_valid_fifo_value) begin
+        up_rack_ff <= sdi_fifo_out_valid;
+      end else begin
+        up_rack_ff <= up_rreq_s;
+      end
+    end
+  end
+
+  //the current logic is considering that there is only one active lane in the set of lanes
+  always @(posedge clk) begin
+    if (!up_sw_resetn) begin
+      find_next_valid_fifo_value <= 1'b0;
+      sdi_out_counter <= 4'hf;
+    end else if (sdi_fifo_out_ready) begin
+      find_next_valid_fifo_value <= ~sdi_fifo_out_valid; //only in the next cycle it is possible to check if it is necessary a new read
+      sdi_out_counter <= sdi_fifo_out_valid ? 4'hf : 0;
+    end else begin
+      if (!sdi_fifo_out_valid && sdi_out_counter < max_num_of_reads) begin
+        find_next_valid_fifo_value <= 1'b1;
+        sdi_out_counter <= sdi_out_counter + 1'b1;
+      end else begin
+        find_next_valid_fifo_value <= 1'b0;
+        sdi_out_counter <= 4'hf;
+      end
+    end
+  end
+
   generate if (ASYNC_SPI_CLK) begin
 
     // synchronization FIFO for the SYNC interface

library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg_data_assemble.v

@@ -81,6 +81,7 @@ always @(posedge clk) begin
             count_active_lanes = 0;
             i = 0;
             j <= 0;
+            mask_index <= 0;
             for (i = 0; i < NUM_OF_SDI; i = i + 1) begin
                 count_active_lanes = count_active_lanes + current_cmd[i];
             end