UNIVERSITY OF WEST ATTICA
SCHOOL OF ENGINEERING
DEPARTMENT OF COMPUTER ENGINEERING AND INFORMATICS

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Digital Circuit Design

Sequential Circuits

Vasileios Evangelos Athanasiou
Student ID: 19390005

GitHub · LinkedIn

Supervisor: Athanasios Milidonis, Postdoctoral Researcher

UNIWA Profile · LinkedIn

Athens, May 2023

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Project Overview

The project focuses on modeling, simulating, and verifying sequential logic circuits using VHDL.
Each circuit is implemented using a clear architectural style and is accompanied by a testbench to validate its behavior under different timing and control conditions.

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Table of Contents

Section	Folder / File	Description
1	assign/	Laboratory assignment material
1.1	assign/Lab4a_UniWA-BSc-DSD_VHDL#2a.pdf	Laboratory exercise description (English)
1.2	assign/Εργαστήριο4α_ΠΑΔΑ-ΣΨΣ_VHDL.pdf	Laboratory exercise description (Greek)
2	docs/	Theoretical documentation on sequential circuits
2.1	docs/Sequential-Circuits.txt	Sequential circuits theory and explanations (English)
2.2	docs/Ακολουθιακά-Κυκλώματα.txt	Sequential circuits theory and explanations (Greek)
3	src/	VHDL source code and testbenches
3.1	src/latch.vhd	Latch implementation
3.2	src/latch_tb.vhd	Latch testbench
3.3	src/flipflop.vhd	Flip-Flop implementation
3.4	src/flipflop_tb.vhd	Flip-Flop testbench
3.5	src/myRegister.vhd	Register implementation
3.6	src/myRegister_tb.vhd	Register testbench
3.7	src/shift4.vhd	4-bit Shift Register
3.8	src/shift4_tb.vhd	4-bit Shift Register testbench
3.9	src/shiftn.vhd	N-bit Shift Register
3.10	src/shiftn_tb.vhd	N-bit Shift Register testbench
3.11	src/upcount.vhd	Up Counter implementation
3.12	src/upcount_tb.vhd	Up Counter testbench
4	README.md	Repository overview and usage instructions

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Implemented Circuits

1. Latch

A basic D-latch where the output Q follows the input D when the Enable (EN) signal is high ('1').
When EN is low ('0'), the output retains its previous value.

2. Flip-Flop

A standard D Flip-Flop that transfers the value of input D to output Q only on the rising edge (0 → 1 transition) of the clock signal (CLK).

3. Flip-Flop with Asynchronous Reset

A D Flip-Flop featuring an asynchronous active-low reset (Rstn).
When Rstn = '0', the output Q is immediately forced to '0', independent of the clock or data inputs.

4. 4-Bit Register

A 4-bit register implemented using flip-flops with a clear (clr) input.
It supports:

• Parallel data loading
• Clearing of all bits on the rising edge of the clock

5. Up-Counter (0 to 3)

A small synchronous up-counter that increments its value from 0 to 3 on each rising clock edge.
A synchronous reset returns the counter to 0.

6. Shift Register

A 4-bit shift register with serial input (Sin).
When the Enable signal is active, bits are shifted serially through the register on each clock pulse.

7. Shift Register with Parallel Loading

A generic N-bit shift register (default: 8-bit) supporting:

• Serial shifting
• Parallel data loading

Parallel loading is activated when the Load signal is high, allowing all bits to be loaded simultaneously.

Simulation & Verification

All circuits are verified using testbenches that stimulate:

• Clock behavior
• Reset and control signals
• Data transitions

Waveform analysis ensures correct sequential behavior and timing compliance.

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Installation & Setup Guide

This repository contains VHDL implementations of fundamental digital logic circuits along with testbenches for functional verification using ModelSim Altera Starter Edition.
The project is intended for digital circuit design education and laboratory exercises.

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Prerequisites

1. Operating System

Supported platforms:

• Windows (recommended – best ModelSim support)
• Linux
• macOS (may require legacy or alternative simulators)

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2. VHDL Simulation Software

ModelSim Altera Starter Edition (Recommended)

This project was developed and verified using:

• ModelSim Altera Starter Edition
• Provided by Intel FPGA (formerly Altera)

Capabilities used:

• VHDL-2008 compatible simulation
• Waveform visualization
• Testbench execution

Note: Newer systems may use ModelSim Intel FPGA Edition or Questa Intel FPGA Starter as replacements.

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3. Text Editor / IDE (Optional but Recommended)

For editing and reviewing VHDL files:

• Visual Studio Code + VHDL extension
• Notepad++
• Vim / Emacs
• ModelSim built-in editor

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4. Knowledge Prerequisites

To understand and modify the project, basic knowledge of:

• Digital logic design
• VHDL syntax and semantics
• Dataflow architecture
• Testbench-driven verification
• Combinational circuits (adders, multiplexers, decoders)

is recommended.

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Installation / Setup

1. Clone the Repository

Using Git:

git clone https://github.com/Digital-Circuit-Design/Sequential-Circuits.git

Alternative (Without Git)

• Open the repository URL in your browser
• Click Code → Download ZIP
• Extract the ZIP file to a local directory

2. Install ModelSim

1. Download ModelSim Altera Starter Edition (or Intel FPGA equivalent)
2. Complete installation following vendor instructions
3. Verify installation by launching ModelSim successfully

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Project Setup in ModelSim

1. Create a New Project

1. Open ModelSim
2. Select File → New → Project
3. Set:
   • Project Name (e.g. VHDL_Lab)
   • Project Location (your cloned repository path)
4. Choose Create Project

2. Add VHDL Source Files

1. In the Add Items to Project window:
   • Select Add Existing File
2. Navigate to the src/ directory
3. Add:
   • All *.vhd files (designs and testbenches)
4. Finish project creation

3. Compile the Project

1. In the Project tab:
   • Select Compile → Compile All
2. Ensure:
   • No syntax errors
   • Successful compilation messages in the transcript

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Simulation & Verification

1. View Waveforms

1. In the simulation window:
   • Add signals to the waveform
2. Run simulation:

run -all

3. Verify:
   • Correct logical behavior
   • Expected outputs for each test case

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Open the Documentation

1. Navigate to the docs/ directory
2. Open the report corresponding to your preferred language:
   • English: Sequential-Circuits.txt
   • Greek: Ακολουθιακά-Κυκλώματα.txt