W8D2: Chen Yongshan

W12D1/W12D1 Arch notes 陈永杉.md

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+## Arch W2D1 notes
+
+###### 陈永杉
+
+### Review : out of order
+
+-Dynamic type: Tomasulo with reorder buffer
+
+-Static: conde movement (achieved in compiler)
+
+### Distributed Computing System
+
+##### Shared memory and Snoopy Protocol
+
+While multi-processer with private cache use one public mem, would in case of coherence. Which means, on data could have more than one copies in different caches and in memory. And they may can't keep same during the multi-processer execution.
+
+Under the Share Memory Polymer:
+
+after adding the cache, 
+
+different processer: non-coherence
+
+between cache and memory: inconsistency
+
+Even write through can't solve the problem that difference between copies in different cache.
+
+Solution: Snoopy (distributed) / Directory-based (centralized)
+
+### Snoopy Protocol
+
+every copy has three types:
+
+invalidate: has no copy/ has a wrong copy
+
+shared: read only
+
+exclusive: can read and write, is the only copy of the newest data.
+
+and with data fresh or write back, copies would change in these three types.
+
+### consistency problem
+
+suppose there are two programs:
+
+```
+a=0;
+...
+a=1;
+if(a==0) then
+  ex. pi;
+```
+
+```
+b=0;
+...
+b=1;
+if(b==0) then
+ex. pj;
+```
+
+if both $a==0$ and $b==0$ ?
+
+consistency requires different watcher can see it in the same order.
+
+### improvement of ESI
+
+add a new type "modify" , into MESI
+

W15D2/Arch W15D2 notes.md

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+## Arch W15D2 notes
+
+###### 陈永杉
+
+#### abstract
+
+<img src="cys W15D2 1.jpg">
+
+#### 1 pipeline
+
+Memory Trace :  memories touched while loop executed.
+
+Cache: calculate the situation of cache after code execution or the miss rate of cache.
+
+pipeline: 
+
+(base): instruction status at cartain time
+
+(forwarding): how to reduce nop/stall 
+
+if code with loop without jump predict, then we need to add nops. And how will it react with jump predictor. 
+
+#### 2 RAID
+
+RAID0: link the disks into a bigger one.
+
+RAID1: make two teams of disks be mirror of each other.
+
+#### 3 consistency
+
+"transetion" : how to make sure each operation of the whole issue must be finished at the continuity way (rollback)
+
+consistency model: contract between software and Memory.
+
+(weak consistency ): add sync. only suit partical size is huge situation. Only make sure consistency at the consistency check point.
+
+add absolute physical time temp to every data before give out.
+
+Sequential consistency: every processers can see the same order from public memory.
+
+Causal model: only make sure causality. 
+
+Cohenrence: others should see change to data in time.
+
+Weak memory model
+
+PiperamRam model: all ram operation must be FIFO. make oricesser kill at same time possible. (a bit more loose)
+
+<img src="cys W15D2 2.jpg">
+
+intel TSX
+
+first add doesn't affected by xbegin. 
+
+addm: if confliex heppens, then abort at once, won't submit to memory.
+
+if x0 or x1 is replaced before xend, then the whole issue would jump to abort without condition. 

W8D2/W8D2 Arch notes 陈永杉.md

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+## Arch W8D2 notes
+
+###### 陈永杉
+
+### Cache
+
+-virtual vs. physical
+
+for after we adding the virtual memory into the archtecture, we need to add an interpretater unit into the structure.
+
+##### question:
+
+Shall we add the interpretater unit into between the cache and the core or between the cache and the memory?
+
+<img src="W8D2_cys_1.jpg">
+
+for we need to search for the page information in the memory, so the cost of the interpretation will be about $n\times 100 circles$.
+
+to optimize it, we can add a cache of PT $i.e. TLB$ (translation lookside Buffer), to backup the page info in it , to accelerate the interpretation time.
+
+The cost of the two structures would be:
+
+physical cache:
+
+hit:100+1 circle;
+
+miss: 100+1+100 circle (which less than 3%)
+
+virtual cache:
+
+hit: 1 circle;
+
+miss:1+100+100 circle.
+
+It's obvious that the virtual cache would be better.
+
+Choosing virtual cache, we come up with:
+
+##### question:
+
+Synonymous/Alias
+
+$\textbf{Q1}$ While we switch processes, for they has the same virtual address, we need to differ them.
+
+one possible sulotion: add a process tag into it. (PID+tag)
+
+another:  take the address into one mva, decided by the OS.
+
+$\textbf{Q2}$ If two datas in one virtual cache were mapped into one phycial address, then there will be two backups of one data in the cache, which would cause the sameness question.
+
+sulotion: .
+
+1. go to 8K byte page size;
+
+   in this way, the length of index is longer than the length of the page size, so two virtual address must be mapped into one same index.
+
+2. go to 2 way set associative cache
+
+   similar with the sulotion .
+
+3. SoftWare (Compiler&OS) guarantee that VA[13]=PA[13].(force the highest bite same)
+
+   we have  # order, which directly give orders to the compiler.
+
+<img src="W8D2_cys_2.jpg">
+
+difference between malloc and mmap:
+
+malloc ask for physical space, while mmap only want to insert a new address in the PT for already exist data.