From d547234de141f23e400997b4d1a5b4e84e399ddf Mon Sep 17 00:00:00 2001 From: Tim Pambor Date: Sat, 6 Dec 2025 10:35:25 +0100 Subject: [PATCH 1/2] dts: arm: st: add reset for lptim Add resets property to lptim binding and define resets for all lptim instances in device tree files for STM32 MCUs. Signed-off-by: Tim Pambor --- dts/arm/st/g0/stm32g0.dtsi | 1 + dts/arm/st/g4/stm32g4.dtsi | 1 + dts/arm/st/h5/stm32h5.dtsi | 2 ++ dts/arm/st/h5/stm32h562.dtsi | 4 ++++ dts/arm/st/h7/stm32h7.dtsi | 1 + dts/arm/st/h7rs/stm32h7rs.dtsi | 1 + dts/arm/st/l0/stm32l0.dtsi | 1 + dts/arm/st/l4/stm32l4.dtsi | 2 ++ dts/arm/st/l5/stm32l5.dtsi | 1 + dts/arm/st/u0/stm32u0.dtsi | 2 ++ dts/arm/st/u0/stm32u073.dtsi | 1 + dts/arm/st/u5/stm32u5.dtsi | 4 ++++ dts/arm/st/wb/stm32wb.dtsi | 1 + dts/arm/st/wba/stm32wba.dtsi | 2 ++ dts/arm/st/wl/stm32wl.dtsi | 1 + dts/bindings/timer/st,stm32-lptim.yaml | 2 -- 16 files changed, 25 insertions(+), 2 deletions(-) diff --git a/dts/arm/st/g0/stm32g0.dtsi b/dts/arm/st/g0/stm32g0.dtsi index dc80d3e7fd37b..4763ce6b18376 100644 --- a/dts/arm/st/g0/stm32g0.dtsi +++ b/dts/arm/st/g0/stm32g0.dtsi @@ -259,6 +259,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1, 31)>; + resets = <&rctl STM32_RESET(APB1L, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi index db6fdb69828e1..e9f1c6b989aa6 100644 --- a/dts/arm/st/g4/stm32g4.dtsi +++ b/dts/arm/st/g4/stm32g4.dtsi @@ -416,6 +416,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1, 31)>; + resets = <&rctl STM32_RESET(APB1L, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi index 292af871786e8..df4223b03662a 100644 --- a/dts/arm/st/h5/stm32h5.dtsi +++ b/dts/arm/st/h5/stm32h5.dtsi @@ -231,6 +231,7 @@ lptim1: timers@44004400 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB3, 11)>; + resets = <&rctl STM32_RESET(APB3, 11)>; #address-cells = <1>; #size-cells = <0>; reg = <0x44004400 0x400>; @@ -242,6 +243,7 @@ lptim2: timers@40009400 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1_2, 5)>; + resets = <&rctl STM32_RESET(APB1H, 5)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40009400 0x400>; diff --git a/dts/arm/st/h5/stm32h562.dtsi b/dts/arm/st/h5/stm32h562.dtsi index 000910368b13f..7a58acabc34fa 100644 --- a/dts/arm/st/h5/stm32h562.dtsi +++ b/dts/arm/st/h5/stm32h562.dtsi @@ -81,6 +81,7 @@ lptim3: timers@44004800 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB3, 12)>; + resets = <&rctl STM32_RESET(APB3, 12)>; #address-cells = <1>; #size-cells = <0>; reg = <0x44004800 0x400>; @@ -92,6 +93,7 @@ lptim4: timers@44004c00 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB3, 13)>; + resets = <&rctl STM32_RESET(APB3, 13)>; #address-cells = <1>; #size-cells = <0>; reg = <0x44004c00 0x400>; @@ -103,6 +105,7 @@ lptim5: timers@44005000 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB3, 14)>; + resets = <&rctl STM32_RESET(APB3, 14)>; #address-cells = <1>; #size-cells = <0>; reg = <0x44005000 0x400>; @@ -114,6 +117,7 @@ lptim6: timers@44005400 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB3, 15)>; + resets = <&rctl STM32_RESET(APB3, 15)>; #address-cells = <1>; #size-cells = <0>; reg = <0x44005400 0x400>; diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi index af3247ea7a16c..584ab1451b3cc 100644 --- a/dts/arm/st/h7/stm32h7.dtsi +++ b/dts/arm/st/h7/stm32h7.dtsi @@ -932,6 +932,7 @@ lptim1: timers@40002400 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1, 9)>; + resets = <&rctl STM32_RESET(APB1L, 9)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40002400 0x400>; diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi index b01aeb433dede..ece4ef0b3bae6 100644 --- a/dts/arm/st/h7rs/stm32h7rs.dtsi +++ b/dts/arm/st/h7rs/stm32h7rs.dtsi @@ -868,6 +868,7 @@ lptim1: timers@40002400 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1, 9)>; + resets = <&rctl STM32_RESET(APB1L, 9)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40002400 0x400>; diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi index fa22dbb826cd4..7ecb011008cce 100644 --- a/dts/arm/st/l0/stm32l0.dtsi +++ b/dts/arm/st/l0/stm32l0.dtsi @@ -311,6 +311,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1, 31)>; + resets = <&rctl STM32_RESET(APB1, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi index 151695dee6e81..dc1bd71264240 100644 --- a/dts/arm/st/l4/stm32l4.dtsi +++ b/dts/arm/st/l4/stm32l4.dtsi @@ -490,6 +490,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1, 31)>; + resets = <&rctl STM32_RESET(APB1L, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; @@ -504,6 +505,7 @@ #size-cells = <0>; reg = <0x40009400 0x400>; clocks = <&rcc STM32_CLOCK(APB1_2, 5)>; + resets = <&rctl STM32_RESET(APB1H, 5)>; interrupts = <66 1>; interrupt-names = "wakeup"; status = "disabled"; diff --git a/dts/arm/st/l5/stm32l5.dtsi b/dts/arm/st/l5/stm32l5.dtsi index 10904ece03685..523650830a3ac 100644 --- a/dts/arm/st/l5/stm32l5.dtsi +++ b/dts/arm/st/l5/stm32l5.dtsi @@ -331,6 +331,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1, 31)>; + resets = <&rctl STM32_RESET(APB1L, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; diff --git a/dts/arm/st/u0/stm32u0.dtsi b/dts/arm/st/u0/stm32u0.dtsi index 0ac94e17b1a34..e082dd5a2f6fc 100644 --- a/dts/arm/st/u0/stm32u0.dtsi +++ b/dts/arm/st/u0/stm32u0.dtsi @@ -582,6 +582,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1, 31)>; + resets = <&rctl STM32_RESET(APB1L, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; @@ -593,6 +594,7 @@ lptim2: timers@40009400 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1, 30)>; + resets = <&rctl STM32_RESET(APB1L, 30)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40009400 0x400>; diff --git a/dts/arm/st/u0/stm32u073.dtsi b/dts/arm/st/u0/stm32u073.dtsi index 8122543d95554..bf26420d71160 100644 --- a/dts/arm/st/u0/stm32u073.dtsi +++ b/dts/arm/st/u0/stm32u073.dtsi @@ -25,6 +25,7 @@ lptim3: timers@40009000 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1, 26)>; + resets = <&rctl STM32_RESET(APB1L, 26)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40009000 0x400>; diff --git a/dts/arm/st/u5/stm32u5.dtsi b/dts/arm/st/u5/stm32u5.dtsi index c031b7109cafe..7aea280d7bc1d 100644 --- a/dts/arm/st/u5/stm32u5.dtsi +++ b/dts/arm/st/u5/stm32u5.dtsi @@ -432,6 +432,7 @@ #size-cells = <0>; reg = <0x46004400 0x400>; clocks = <&rcc STM32_CLOCK(APB3, 11)>; + resets = <&rctl STM32_RESET(APB3, 11)>; interrupts = <67 1>; interrupt-names = "wakeup"; status = "disabled"; @@ -443,6 +444,7 @@ #size-cells = <0>; reg = <0x40009400 0x400>; clocks = <&rcc STM32_CLOCK(APB1_2, 5)>; + resets = <&rctl STM32_RESET(APB1H, 5)>; interrupts = <68 0>; interrupt-names = "global"; status = "disabled"; @@ -454,6 +456,7 @@ #size-cells = <0>; reg = <0x46004800 0x400>; clocks = <&rcc STM32_CLOCK(APB3, 12)>; + resets = <&rctl STM32_RESET(APB3, 12)>; interrupts = <98 0>; interrupt-names = "global"; status = "disabled"; @@ -465,6 +468,7 @@ #size-cells = <0>; reg = <0x46004c00 0x400>; clocks = <&rcc STM32_CLOCK(APB3, 13)>; + resets = <&rctl STM32_RESET(APB3, 13)>; interrupts = <110 0>; interrupt-names = "global"; status = "disabled"; diff --git a/dts/arm/st/wb/stm32wb.dtsi b/dts/arm/st/wb/stm32wb.dtsi index e1aba8b9c1352..28dc4ea9e08d5 100644 --- a/dts/arm/st/wb/stm32wb.dtsi +++ b/dts/arm/st/wb/stm32wb.dtsi @@ -457,6 +457,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1, 31)>; + resets = <&rctl STM32_RESET(APB1L, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; diff --git a/dts/arm/st/wba/stm32wba.dtsi b/dts/arm/st/wba/stm32wba.dtsi index cbbdfea666858..020001e4285a3 100644 --- a/dts/arm/st/wba/stm32wba.dtsi +++ b/dts/arm/st/wba/stm32wba.dtsi @@ -520,6 +520,7 @@ #size-cells = <0>; reg = <0x46004400 0x400>; clocks = <&rcc STM32_CLOCK(APB7, 11)>; + resets = <&rctl STM32_RESET(APB7, 11)>; interrupts = <49 1>; interrupt-names = "wakeup"; status = "disabled"; @@ -531,6 +532,7 @@ #size-cells = <0>; reg = <0x40009400 0x400>; clocks = <&rcc STM32_CLOCK(APB1_2, 5)>; + resets = <&rctl STM32_RESET(APB1H, 5)>; interrupts = <50 1>; interrupt-names = "wakeup"; status = "disabled"; diff --git a/dts/arm/st/wl/stm32wl.dtsi b/dts/arm/st/wl/stm32wl.dtsi index b94439ee83de6..078d46e9d1f4a 100644 --- a/dts/arm/st/wl/stm32wl.dtsi +++ b/dts/arm/st/wl/stm32wl.dtsi @@ -205,6 +205,7 @@ lptim1: timers@40007c00 { compatible = "st,stm32-lptim"; clocks = <&rcc STM32_CLOCK(APB1, 31)>; + resets = <&rctl STM32_RESET(APB1L, 31)>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007c00 0x400>; diff --git a/dts/bindings/timer/st,stm32-lptim.yaml b/dts/bindings/timer/st,stm32-lptim.yaml index 31e4ea0e8efd3..43b9e311f6636 100644 --- a/dts/bindings/timer/st,stm32-lptim.yaml +++ b/dts/bindings/timer/st,stm32-lptim.yaml @@ -15,8 +15,6 @@ compatible: "st,stm32-lptim" include: - name: st,stm32-timers.yaml property-blocklist: - # 'resets' property is not supported yet - - resets - st,prescaler - st,countermode From e818917e9491fa5cb7b269091aabcd1912a29a53 Mon Sep 17 00:00:00 2001 From: Tim Pambor Date: Sat, 6 Dec 2025 10:36:42 +0100 Subject: [PATCH 2/2] drivers: timer: stm32_lptim: add reset support Add support for resetting the LPTIM peripheral to its default state on initialization. This ensures that any previous configurations do not interfere with the new settings. Signed-off-by: Tim Pambor --- drivers/timer/stm32_lptim_timer.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/timer/stm32_lptim_timer.c b/drivers/timer/stm32_lptim_timer.c index 6a8fdd6b29fb5..86994fa9a9521 100644 --- a/drivers/timer/stm32_lptim_timer.c +++ b/drivers/timer/stm32_lptim_timer.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -38,6 +39,8 @@ static const struct stm32_pclken lptim_clk[] = STM32_DT_INST_CLOCKS(0); static const struct device *const clk_ctrl = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); +static const struct reset_dt_spec lptim_reset = RESET_DT_SPEC_INST_GET(0); + /* * Assumptions and limitations: * @@ -559,6 +562,9 @@ static int sys_clock_driver_init(void) } #endif + /* Reset timer to default state using RCC */ + (void)reset_line_toggle_dt(&lptim_reset); + #if DT_PROP(DT_NODELABEL(stm32_lp_tick_source), st_timeout) uint32_t timeout = DT_PROP(DT_NODELABEL(stm32_lp_tick_source), st_timeout);