dts: arm: nxp: nxp_ke1xz.dtsi: tsi0 & tsi1 nodes added

TSI (Touch Sensing IP) is now supported by DT
for the Kinetis KE1x family
dts: nxp_ke1xz, nxp_ke17z and nxp_ke17z512.dtsi
Tested on freedom boards

Signed-off-by: Michael Galda <michael.galda@nxp.com>
Signed-off-by: Hake Huang <hake.huang@nxp.com>

Author: hakehuang

dts/arm/nxp/nxp_ke17z.dtsi

@@ -47,6 +47,14 @@
 			};
 		};
 
+		tsi1: tsi@40047000 {
+			compatible = "nxp,tsi";
+			reg = <0x40047000 0x1000>;
+			status = "okay";
+			interrupts = <25 0>;
+			clocks = <&scg KINETIS_SCG_BUS_CLK>;
+		};
+
 		/* Remove rtc, it doesn't exist on KE17Z */
 		/delete-node/ rtc@4003d000;
 	};

dts/arm/nxp/nxp_ke17z512.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -61,5 +61,23 @@
 			clocks = <&scg KINETIS_SCG_BUS_CLK>;
 			status = "disabled";
 		};
+
+		scg@40064000 {
+			/delete-node/ lpfll_clk;
+
+			lpfll_clk: lpfll_clk {
+				compatible = "fixed-clock";
+				clock-frequency = <96000000>;
+				#clock-cells = <0>;
+			};
+		};
+
+		tsi1: tsi@40047000 {
+			compatible = "nxp,tsi";
+			reg = <0x40047000 0x1000>;
+			status = "okay";
+			interrupts = <25 0>;
+			clocks = <&scg KINETIS_SCG_BUS_CLK>;
+		};
 	};
 };

dts/arm/nxp/nxp_ke1xz.dtsi

@@ -90,9 +90,16 @@
 				#clock-cells = <0>;
 			};
 
+			lpfll_clk: lpfll_clk {
+				compatible = "fixed-clock";
+				clock-frequency = <72000000>;
+				#clock-cells = <0>;
+			};
+
 			core_clk: core_clk {
 				compatible = "fixed-factor-clock";
-				clocks = <&firc_clk>;
+				#clocks = <&firc_clk>;
+				clocks = <&lpfll_clk>;
 				clock-div = <1>;
 				#clock-cells = <0>;
 			};
@@ -117,6 +124,13 @@
 				clock-div = <1>;
 				#clock-cells = <0>;
 			};
+
+			flldiv2_clk: flldiv2_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&lpfll_clk>;
+				clock-div = <2>;
+				#clock-cells = <0>;
+			};
 		};
 
 		pcc: pcc@40065000 {
@@ -511,6 +525,49 @@
 			interrupts = <23 0>;
 			clocks = <&pcc 0x168 KINETIS_PCC_SRC_FIRC_ASYNC>;
 		};
+
+		pit0: pit@40037000 {
+			compatible = "nxp,pit";
+			reg = <0x40037000 0x1000>;
+			clocks = <&pcc 0x1a8 KINETIS_PCC_SRC_FIRC_ASYNC>;
+			interrupts = <22 0>;
+			max-load-value = <0xffffffff>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pit0_channel0: pit0_channel@0 {
+				compatible = "nxp,pit-channel";
+				reg = <0>;
+				status = "disabled";
+			};
+
+			pit0_channel1: pit0_channel@1 {
+				compatible = "nxp,pit-channel";
+				reg = <1>;
+				status = "disabled";
+			};
+
+			pit0_channel2: pit0_channel@2 {
+				compatible = "nxp,pit-channel";
+				reg = <2>;
+				status = "disabled";
+			};
+
+			pit0_channel3: pit0_channel@3 {
+				compatible = "nxp,pit-channel";
+				reg = <3>;
+				status = "disabled";
+			};
+		};
+
+		tsi0: tsi@40045000 {
+			compatible = "nxp,tsi";
+			reg = <0x40045000 0x1000>;
+			status = "okay";
+			interrupts = <24 0>;
+			clocks = <&scg KINETIS_SCG_BUS_CLK>;
+		};
 	};
 };
 

dts/arm/nxp/nxp_ke1xz64.dtsi

@@ -0,0 +1,67 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_ke1xz.dtsi>
+
+/delete-node/ &sram_l;
+/delete-node/ &sram_u;
+
+/* Remove non-supported peripherals on 64kB silicon */
+/delete-node/ &ftm2;
+/delete-node/ &lpi2c1;
+/delete-node/ &lpspi1;
+/delete-node/ &edma;
+/delete-node/ &flexio;
+
+/ {
+	chosen {
+		zephyr,flash-controller = &ftfa;
+	};
+
+	/* Fix sram_l and sram_u, they have different addr and size on KE16Z */
+	sram_l: memory@1ffff800 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x1ffff800 DT_SIZE_K(2)>;
+		zephyr,memory-region = "SRAML";
+	};
+
+	sram_u: memory@20000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20000000 DT_SIZE_K(6)>;
+		zephyr,memory-region = "SRAMU";
+	};
+
+	soc {
+		/* Remove ftfe, it doesn't exist on KE16Z */
+		/delete-node/ ftfe;
+
+		ftfa: flash-controller@40020000 {
+			compatible = "nxp,kinetis-ftfa";
+			reg = <0x40020000 0x1000>;
+			interrupts = <5 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0 DT_SIZE_K(64)>;
+				erase-block-size = <DT_SIZE_K(1)>;
+				write-block-size = <8>;
+			};
+		};
+
+		scg@40064000 {
+			/delete-node/ lpfll_clk;
+
+			lpfll_clk: lpfll_clk {
+				compatible = "fixed-clock";
+				clock-frequency = <48000000>;
+				#clock-cells = <0>;
+			};
+		};
+	};
+};