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[AArch64][GlobalISel] Add patterns for scalar float-to-int conversions
1 parent bc5441b commit fb752c5

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3 files changed

+63
-108
lines changed

3 files changed

+63
-108
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6835,6 +6835,21 @@ multiclass FPToIntegerPats<SDNode to_int, SDNode to_int_sat, SDNode to_int_sat_g
68356835
def : Pat<(i64 (to_int_sat (round f64:$Rn), i64)),
68366836
(!cast<Instruction>(INST # UXDr) f64:$Rn)>;
68376837

6838+
let Predicates = [HasFullFP16] in {
6839+
def : Pat<(i32 (to_int_sat_gi (round f16:$Rn))),
6840+
(!cast<Instruction>(INST # UWHr) f16:$Rn)>;
6841+
def : Pat<(i64 (to_int_sat_gi (round f16:$Rn))),
6842+
(!cast<Instruction>(INST # UXHr) f16:$Rn)>;
6843+
}
6844+
def : Pat<(i32 (to_int_sat_gi (round f32:$Rn))),
6845+
(!cast<Instruction>(INST # UWSr) f32:$Rn)>;
6846+
def : Pat<(i64 (to_int_sat_gi (round f32:$Rn))),
6847+
(!cast<Instruction>(INST # UXSr) f32:$Rn)>;
6848+
def : Pat<(i32 (to_int_sat_gi (round f64:$Rn))),
6849+
(!cast<Instruction>(INST # UWDr) f64:$Rn)>;
6850+
def : Pat<(i64 (to_int_sat_gi (round f64:$Rn))),
6851+
(!cast<Instruction>(INST # UXDr) f64:$Rn)>;
6852+
68386853
// For global-isel we can use register classes to determine
68396854
// which FCVT instruction to use.
68406855
let Predicates = [HasFPRCVT] in {

‎llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll‎

Lines changed: 24 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -98,8 +98,7 @@ define i32 @testmswh(half %a) {
9898
;
9999
; CHECK-GI-LABEL: testmswh:
100100
; CHECK-GI: // %bb.0: // %entry
101-
; CHECK-GI-NEXT: frintm h0, h0
102-
; CHECK-GI-NEXT: fcvtzs w0, h0
101+
; CHECK-GI-NEXT: fcvtms w0, h0
103102
; CHECK-GI-NEXT: ret
104103
entry:
105104
%r = call half @llvm.floor.f16(half %a)
@@ -124,8 +123,7 @@ define i64 @testmsxh(half %a) {
124123
;
125124
; CHECK-GI-LABEL: testmsxh:
126125
; CHECK-GI: // %bb.0: // %entry
127-
; CHECK-GI-NEXT: frintm h0, h0
128-
; CHECK-GI-NEXT: fcvtzs x0, h0
126+
; CHECK-GI-NEXT: fcvtms x0, h0
129127
; CHECK-GI-NEXT: ret
130128
entry:
131129
%r = call half @llvm.floor.f16(half %a)
@@ -141,8 +139,7 @@ define i32 @testmsws(float %a) {
141139
;
142140
; CHECK-GI-LABEL: testmsws:
143141
; CHECK-GI: // %bb.0: // %entry
144-
; CHECK-GI-NEXT: frintm s0, s0
145-
; CHECK-GI-NEXT: fcvtzs w0, s0
142+
; CHECK-GI-NEXT: fcvtms w0, s0
146143
; CHECK-GI-NEXT: ret
147144
entry:
148145
%r = call float @llvm.floor.f32(float %a)
@@ -158,8 +155,7 @@ define i64 @testmsxs(float %a) {
158155
;
159156
; CHECK-GI-LABEL: testmsxs:
160157
; CHECK-GI: // %bb.0: // %entry
161-
; CHECK-GI-NEXT: frintm s0, s0
162-
; CHECK-GI-NEXT: fcvtzs x0, s0
158+
; CHECK-GI-NEXT: fcvtms x0, s0
163159
; CHECK-GI-NEXT: ret
164160
entry:
165161
%r = call float @llvm.floor.f32(float %a)
@@ -175,8 +171,7 @@ define i32 @testmswd(double %a) {
175171
;
176172
; CHECK-GI-LABEL: testmswd:
177173
; CHECK-GI: // %bb.0: // %entry
178-
; CHECK-GI-NEXT: frintm d0, d0
179-
; CHECK-GI-NEXT: fcvtzs w0, d0
174+
; CHECK-GI-NEXT: fcvtms w0, d0
180175
; CHECK-GI-NEXT: ret
181176
entry:
182177
%r = call double @llvm.floor.f64(double %a)
@@ -192,8 +187,7 @@ define i64 @testmsxd(double %a) {
192187
;
193188
; CHECK-GI-LABEL: testmsxd:
194189
; CHECK-GI: // %bb.0: // %entry
195-
; CHECK-GI-NEXT: frintm d0, d0
196-
; CHECK-GI-NEXT: fcvtzs x0, d0
190+
; CHECK-GI-NEXT: fcvtms x0, d0
197191
; CHECK-GI-NEXT: ret
198192
entry:
199193
%r = call double @llvm.floor.f64(double %a)
@@ -296,8 +290,7 @@ define i32 @testpswh(half %a) {
296290
;
297291
; CHECK-GI-LABEL: testpswh:
298292
; CHECK-GI: // %bb.0: // %entry
299-
; CHECK-GI-NEXT: frintp h0, h0
300-
; CHECK-GI-NEXT: fcvtzs w0, h0
293+
; CHECK-GI-NEXT: fcvtps w0, h0
301294
; CHECK-GI-NEXT: ret
302295
entry:
303296
%r = call half @llvm.ceil.f16(half %a)
@@ -322,8 +315,7 @@ define i64 @testpsxh(half %a) {
322315
;
323316
; CHECK-GI-LABEL: testpsxh:
324317
; CHECK-GI: // %bb.0: // %entry
325-
; CHECK-GI-NEXT: frintp h0, h0
326-
; CHECK-GI-NEXT: fcvtzs x0, h0
318+
; CHECK-GI-NEXT: fcvtps x0, h0
327319
; CHECK-GI-NEXT: ret
328320
entry:
329321
%r = call half @llvm.ceil.f16(half %a)
@@ -339,8 +331,7 @@ define i32 @testpsws(float %a) {
339331
;
340332
; CHECK-GI-LABEL: testpsws:
341333
; CHECK-GI: // %bb.0: // %entry
342-
; CHECK-GI-NEXT: frintp s0, s0
343-
; CHECK-GI-NEXT: fcvtzs w0, s0
334+
; CHECK-GI-NEXT: fcvtps w0, s0
344335
; CHECK-GI-NEXT: ret
345336
entry:
346337
%r = call float @llvm.ceil.f32(float %a)
@@ -356,8 +347,7 @@ define i64 @testpsxs(float %a) {
356347
;
357348
; CHECK-GI-LABEL: testpsxs:
358349
; CHECK-GI: // %bb.0: // %entry
359-
; CHECK-GI-NEXT: frintp s0, s0
360-
; CHECK-GI-NEXT: fcvtzs x0, s0
350+
; CHECK-GI-NEXT: fcvtps x0, s0
361351
; CHECK-GI-NEXT: ret
362352
entry:
363353
%r = call float @llvm.ceil.f32(float %a)
@@ -373,8 +363,7 @@ define i32 @testpswd(double %a) {
373363
;
374364
; CHECK-GI-LABEL: testpswd:
375365
; CHECK-GI: // %bb.0: // %entry
376-
; CHECK-GI-NEXT: frintp d0, d0
377-
; CHECK-GI-NEXT: fcvtzs w0, d0
366+
; CHECK-GI-NEXT: fcvtps w0, d0
378367
; CHECK-GI-NEXT: ret
379368
entry:
380369
%r = call double @llvm.ceil.f64(double %a)
@@ -390,8 +379,7 @@ define i64 @testpsxd(double %a) {
390379
;
391380
; CHECK-GI-LABEL: testpsxd:
392381
; CHECK-GI: // %bb.0: // %entry
393-
; CHECK-GI-NEXT: frintp d0, d0
394-
; CHECK-GI-NEXT: fcvtzs x0, d0
382+
; CHECK-GI-NEXT: fcvtps x0, d0
395383
; CHECK-GI-NEXT: ret
396384
entry:
397385
%r = call double @llvm.ceil.f64(double %a)
@@ -418,7 +406,6 @@ define i32 @testzswh(half %a) {
418406
;
419407
; CHECK-GI-LABEL: testzswh:
420408
; CHECK-GI: // %bb.0: // %entry
421-
; CHECK-GI-NEXT: frintz h0, h0
422409
; CHECK-GI-NEXT: fcvtzs w0, h0
423410
; CHECK-GI-NEXT: ret
424411
entry:
@@ -444,7 +431,6 @@ define i64 @testzsxh(half %a) {
444431
;
445432
; CHECK-GI-LABEL: testzsxh:
446433
; CHECK-GI: // %bb.0: // %entry
447-
; CHECK-GI-NEXT: frintz h0, h0
448434
; CHECK-GI-NEXT: fcvtzs x0, h0
449435
; CHECK-GI-NEXT: ret
450436
entry:
@@ -461,7 +447,6 @@ define i32 @testzsws(float %a) {
461447
;
462448
; CHECK-GI-LABEL: testzsws:
463449
; CHECK-GI: // %bb.0: // %entry
464-
; CHECK-GI-NEXT: frintz s0, s0
465450
; CHECK-GI-NEXT: fcvtzs w0, s0
466451
; CHECK-GI-NEXT: ret
467452
entry:
@@ -478,7 +463,6 @@ define i64 @testzsxs(float %a) {
478463
;
479464
; CHECK-GI-LABEL: testzsxs:
480465
; CHECK-GI: // %bb.0: // %entry
481-
; CHECK-GI-NEXT: frintz s0, s0
482466
; CHECK-GI-NEXT: fcvtzs x0, s0
483467
; CHECK-GI-NEXT: ret
484468
entry:
@@ -495,7 +479,6 @@ define i32 @testzswd(double %a) {
495479
;
496480
; CHECK-GI-LABEL: testzswd:
497481
; CHECK-GI: // %bb.0: // %entry
498-
; CHECK-GI-NEXT: frintz d0, d0
499482
; CHECK-GI-NEXT: fcvtzs w0, d0
500483
; CHECK-GI-NEXT: ret
501484
entry:
@@ -512,7 +495,6 @@ define i64 @testzsxd(double %a) {
512495
;
513496
; CHECK-GI-LABEL: testzsxd:
514497
; CHECK-GI: // %bb.0: // %entry
515-
; CHECK-GI-NEXT: frintz d0, d0
516498
; CHECK-GI-NEXT: fcvtzs x0, d0
517499
; CHECK-GI-NEXT: ret
518500
entry:
@@ -540,8 +522,7 @@ define i32 @testaswh(half %a) {
540522
;
541523
; CHECK-GI-LABEL: testaswh:
542524
; CHECK-GI: // %bb.0: // %entry
543-
; CHECK-GI-NEXT: frinta h0, h0
544-
; CHECK-GI-NEXT: fcvtzs w0, h0
525+
; CHECK-GI-NEXT: fcvtas w0, h0
545526
; CHECK-GI-NEXT: ret
546527
entry:
547528
%r = call half @llvm.round.f16(half %a)
@@ -566,8 +547,7 @@ define i64 @testasxh(half %a) {
566547
;
567548
; CHECK-GI-LABEL: testasxh:
568549
; CHECK-GI: // %bb.0: // %entry
569-
; CHECK-GI-NEXT: frinta h0, h0
570-
; CHECK-GI-NEXT: fcvtzs x0, h0
550+
; CHECK-GI-NEXT: fcvtas x0, h0
571551
; CHECK-GI-NEXT: ret
572552
entry:
573553
%r = call half @llvm.round.f16(half %a)
@@ -583,8 +563,7 @@ define i32 @testasws(float %a) {
583563
;
584564
; CHECK-GI-LABEL: testasws:
585565
; CHECK-GI: // %bb.0: // %entry
586-
; CHECK-GI-NEXT: frinta s0, s0
587-
; CHECK-GI-NEXT: fcvtzs w0, s0
566+
; CHECK-GI-NEXT: fcvtas w0, s0
588567
; CHECK-GI-NEXT: ret
589568
entry:
590569
%r = call float @llvm.round.f32(float %a)
@@ -600,8 +579,7 @@ define i64 @testasxs(float %a) {
600579
;
601580
; CHECK-GI-LABEL: testasxs:
602581
; CHECK-GI: // %bb.0: // %entry
603-
; CHECK-GI-NEXT: frinta s0, s0
604-
; CHECK-GI-NEXT: fcvtzs x0, s0
582+
; CHECK-GI-NEXT: fcvtas x0, s0
605583
; CHECK-GI-NEXT: ret
606584
entry:
607585
%r = call float @llvm.round.f32(float %a)
@@ -617,8 +595,7 @@ define i32 @testaswd(double %a) {
617595
;
618596
; CHECK-GI-LABEL: testaswd:
619597
; CHECK-GI: // %bb.0: // %entry
620-
; CHECK-GI-NEXT: frinta d0, d0
621-
; CHECK-GI-NEXT: fcvtzs w0, d0
598+
; CHECK-GI-NEXT: fcvtas w0, d0
622599
; CHECK-GI-NEXT: ret
623600
entry:
624601
%r = call double @llvm.round.f64(double %a)
@@ -634,8 +611,7 @@ define i64 @testasxd(double %a) {
634611
;
635612
; CHECK-GI-LABEL: testasxd:
636613
; CHECK-GI: // %bb.0: // %entry
637-
; CHECK-GI-NEXT: frinta d0, d0
638-
; CHECK-GI-NEXT: fcvtzs x0, d0
614+
; CHECK-GI-NEXT: fcvtas x0, d0
639615
; CHECK-GI-NEXT: ret
640616
entry:
641617
%r = call double @llvm.round.f64(double %a)
@@ -662,8 +638,7 @@ define i32 @testnswh(half %a) {
662638
;
663639
; CHECK-GI-LABEL: testnswh:
664640
; CHECK-GI: // %bb.0: // %entry
665-
; CHECK-GI-NEXT: frintn h0, h0
666-
; CHECK-GI-NEXT: fcvtzs w0, h0
641+
; CHECK-GI-NEXT: fcvtns w0, h0
667642
; CHECK-GI-NEXT: ret
668643
entry:
669644
%r = call half @llvm.roundeven.f16(half %a)
@@ -688,8 +663,7 @@ define i64 @testnsxh(half %a) {
688663
;
689664
; CHECK-GI-LABEL: testnsxh:
690665
; CHECK-GI: // %bb.0: // %entry
691-
; CHECK-GI-NEXT: frintn h0, h0
692-
; CHECK-GI-NEXT: fcvtzs x0, h0
666+
; CHECK-GI-NEXT: fcvtns x0, h0
693667
; CHECK-GI-NEXT: ret
694668
entry:
695669
%r = call half @llvm.roundeven.f16(half %a)
@@ -705,8 +679,7 @@ define i32 @testnsws(float %a) {
705679
;
706680
; CHECK-GI-LABEL: testnsws:
707681
; CHECK-GI: // %bb.0: // %entry
708-
; CHECK-GI-NEXT: frintn s0, s0
709-
; CHECK-GI-NEXT: fcvtzs w0, s0
682+
; CHECK-GI-NEXT: fcvtns w0, s0
710683
; CHECK-GI-NEXT: ret
711684
entry:
712685
%r = call float @llvm.roundeven.f32(float %a)
@@ -722,8 +695,7 @@ define i64 @testnsxs(float %a) {
722695
;
723696
; CHECK-GI-LABEL: testnsxs:
724697
; CHECK-GI: // %bb.0: // %entry
725-
; CHECK-GI-NEXT: frintn s0, s0
726-
; CHECK-GI-NEXT: fcvtzs x0, s0
698+
; CHECK-GI-NEXT: fcvtns x0, s0
727699
; CHECK-GI-NEXT: ret
728700
entry:
729701
%r = call float @llvm.roundeven.f32(float %a)
@@ -739,8 +711,7 @@ define i32 @testnswd(double %a) {
739711
;
740712
; CHECK-GI-LABEL: testnswd:
741713
; CHECK-GI: // %bb.0: // %entry
742-
; CHECK-GI-NEXT: frintn d0, d0
743-
; CHECK-GI-NEXT: fcvtzs w0, d0
714+
; CHECK-GI-NEXT: fcvtns w0, d0
744715
; CHECK-GI-NEXT: ret
745716
entry:
746717
%r = call double @llvm.roundeven.f64(double %a)
@@ -756,8 +727,7 @@ define i64 @testnsxd(double %a) {
756727
;
757728
; CHECK-GI-LABEL: testnsxd:
758729
; CHECK-GI: // %bb.0: // %entry
759-
; CHECK-GI-NEXT: frintn d0, d0
760-
; CHECK-GI-NEXT: fcvtzs x0, d0
730+
; CHECK-GI-NEXT: fcvtns x0, d0
761731
; CHECK-GI-NEXT: ret
762732
entry:
763733
%r = call double @llvm.roundeven.f64(double %a)

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