[AArch64] Add non-saturating roundeven+fpto[su]i tests

Author: valadaptive

llvm/test/CodeGen/AArch64/round-conv.ll

@@ -250,6 +250,16 @@ entry:
   ret i32 %conv
 }
 
+; CHECK-LABEL: testnsws:
+; CHECK: fcvtns w0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
+define i32 @testnsws(float %a) {
+entry:
+  %call = call float @llvm.roundeven.f32(float %a)
+  %conv = fptosi float %call to i32
+  ret i32 %conv
+}
+
 ; CHECK-LABEL: testasxs:
 ; CHECK: fcvtas x0, s0
 ; CHECK-NOT: frintx {{s[0-9]+}}, s0
@@ -260,6 +270,16 @@ entry:
   ret i64 %conv
 }
 
+; CHECK-LABEL: testnsxs:
+; CHECK: fcvtns x0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
+define i64 @testnsxs(float %a) {
+entry:
+  %call = call float @llvm.roundeven.f32(float %a)
+  %conv = fptosi float %call to i64
+  ret i64 %conv
+}
+
 ; CHECK-LABEL: testaswd:
 ; CHECK: fcvtas w0, d0
 ; CHECK-NOT: frintx {{d[0-9]+}}, d0
@@ -270,6 +290,16 @@ entry:
   ret i32 %conv
 }
 
+; CHECK-LABEL: testnswd:
+; CHECK: fcvtns w0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
+define i32 @testnswd(double %a) {
+entry:
+  %call = call double @llvm.roundeven.f64(double %a)
+  %conv = fptosi double %call to i32
+  ret i32 %conv
+}
+
 ; CHECK-LABEL: testasxd:
 ; CHECK: fcvtas x0, d0
 ; CHECK-NOT: frintx {{d[0-9]+}}, d0
@@ -280,6 +310,16 @@ entry:
   ret i64 %conv
 }
 
+; CHECK-LABEL: testnsxd:
+; CHECK: fcvtns x0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
+define i64 @testnsxd(double %a) {
+entry:
+  %call = call double @llvm.roundeven.f64(double %a)
+  %conv = fptosi double %call to i64
+  ret i64 %conv
+}
+
 ; CHECK-LABEL: testauws:
 ; CHECK: fcvtau w0, s0
 ; CHECK-NOT: frintx {{s[0-9]+}}, s0
@@ -290,6 +330,16 @@ entry:
   ret i32 %conv
 }
 
+; CHECK-LABEL: testnuws:
+; CHECK: fcvtnu w0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
+define i32 @testnuws(float %a) {
+entry:
+  %call = call float @llvm.roundeven.f32(float %a)
+  %conv = fptoui float %call to i32
+  ret i32 %conv
+}
+
 ; CHECK-LABEL: testauxs:
 ; CHECK: fcvtau x0, s0
 ; CHECK-NOT: frintx {{s[0-9]+}}, s0
@@ -300,6 +350,16 @@ entry:
   ret i64 %conv
 }
 
+; CHECK-LABEL: testnuxs:
+; CHECK: fcvtnu x0, s0
+; CHECK-NOT: frintx {{s[0-9]+}}, s0
+define i64 @testnuxs(float %a) {
+entry:
+  %call = call float @llvm.roundeven.f32(float %a)
+  %conv = fptoui float %call to i64
+  ret i64 %conv
+}
+
 ; CHECK-LABEL: testauwd:
 ; CHECK: fcvtau w0, d0
 ; CHECK-NOT: frintx {{d[0-9]+}}, d0
@@ -310,6 +370,16 @@ entry:
   ret i32 %conv
 }
 
+; CHECK-LABEL: testnuwd:
+; CHECK: fcvtnu w0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
+define i32 @testnuwd(double %a) {
+entry:
+  %call = call double @llvm.roundeven.f64(double %a)
+  %conv = fptoui double %call to i32
+  ret i32 %conv
+}
+
 ; CHECK-LABEL: testauxd:
 ; CHECK: fcvtau x0, d0
 ; CHECK-NOT: frintx {{d[0-9]+}}, d0
@@ -320,6 +390,16 @@ entry:
   ret i64 %conv
 }
 
+; CHECK-LABEL: testnuxd:
+; CHECK: fcvtnu x0, d0
+; CHECK-NOT: frintx {{d[0-9]+}}, d0
+define i64 @testnuxd(double %a) {
+entry:
+  %call = call double @llvm.roundeven.f64(double %a)
+  %conv = fptoui double %call to i64
+  ret i64 %conv
+}
+
 declare float @floorf(float) nounwind readnone
 declare double @floor(double) nounwind readnone
 declare float @ceilf(float) nounwind readnone
@@ -328,3 +408,5 @@ declare float @truncf(float) nounwind readnone
 declare double @trunc(double) nounwind readnone
 declare float @roundf(float) nounwind readnone
 declare double @round(double) nounwind readnone
+declare float @llvm.roundeven.f32(float)
+declare double @llvm.roundeven.f64(double)