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Add PMP CSR access infrastructure
Provide helper functions for runtime-indexed access to PMP control and status registers alongside existing compile-time CSR macros. RISC-V CSR instructions encode register addresses as immediate values in the instruction itself, making dynamic selection impossible through simple arithmetic. These helpers use switch-case dispatch to map runtime indices to specific CSR instructions while preserving type safety. This enables PMP register management code to iterate over regions without knowing exact register numbers at compile-time, supporting features with multiple registers of the same type. PMP implementation is now included in the build system to make these helpers and future PMP functionality available at link time.
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‎arch/riscv/build.mk‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ LDFLAGS += --gc-sections
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ARFLAGS = r
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LDSCRIPT = $(ARCH_DIR)/riscv32-qemu.ld
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73-
HAL_OBJS := boot.o hal.o muldiv.o
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HAL_OBJS := boot.o hal.o muldiv.o pmp.o
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HAL_OBJS := $(addprefix $(BUILD_KERNEL_DIR)/,$(HAL_OBJS))
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deps += $(HAL_OBJS:%.o=%.o.d)
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‎arch/riscv/hal.h‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,25 @@ extern uint32_t _stack_bottom, _stack_top; /* Bottom/top of the STACK memory */
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*/
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#define write_csr(reg, val) ({ asm volatile("csrw " #reg ", %0" ::"rK"(val)); })
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/* Read CSR by numeric address (for dynamic register selection).
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* Used when CSR number is not known at compile-time (e.g., PMP registers).
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* @csr_num : CSR address as a compile-time constant.
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*/
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#define read_csr_num(csr_num) \
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({ \
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uint32_t __tmp; \
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asm volatile("csrr %0, %1" : "=r"(__tmp) : "i"(csr_num)); \
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__tmp; \
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})
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/* Write CSR by numeric address (for dynamic register selection).
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* Used when CSR number is not known at compile-time (e.g., PMP registers).
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* @csr_num : CSR address as a compile-time constant.
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* @val : The 32-bit value to write.
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*/
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#define write_csr_num(csr_num, val) \
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({ asm volatile("csrw %0, %1" ::"i"(csr_num), "rK"(val)); })
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3150
/* Globally enable or disable machine-level interrupts by setting mstatus.MIE.
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* @enable : Non-zero to enable, zero to disable.
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* Returns the previous state of the interrupt enable bit (1 if enabled, 0 if

‎arch/riscv/pmp.c‎

Lines changed: 143 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,149 @@
77
#include <hal.h>
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#include <sys/memprot.h>
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#include "csr.h"
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#include "private/error.h"
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/* PMP CSR Access Helpers
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*
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* RISC-V CSR instructions require compile-time constant addresses encoded in
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* the instruction itself. These helpers use switch-case dispatch to provide
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* runtime indexed access to PMP configuration and address registers.
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*
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* - pmpcfg0-3: Four 32-bit configuration registers (16 regions, 8 bits each)
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* - pmpaddr0-15: Sixteen address registers for TOR (Top-of-Range) mode
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*/
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/* Read PMP configuration register by index (0-3) */
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static uint32_t read_pmpcfg(uint8_t idx)
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{
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switch (idx) {
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case 0:
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return read_csr_num(CSR_PMPCFG0);
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case 1:
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return read_csr_num(CSR_PMPCFG1);
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case 2:
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return read_csr_num(CSR_PMPCFG2);
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case 3:
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return read_csr_num(CSR_PMPCFG3);
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default:
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return 0;
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}
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}
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/* Write PMP configuration register by index (0-3) */
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static void write_pmpcfg(uint8_t idx, uint32_t val)
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{
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switch (idx) {
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case 0:
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write_csr_num(CSR_PMPCFG0, val);
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break;
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case 1:
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write_csr_num(CSR_PMPCFG1, val);
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break;
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case 2:
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write_csr_num(CSR_PMPCFG2, val);
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break;
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case 3:
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write_csr_num(CSR_PMPCFG3, val);
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break;
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}
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}
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/* Read PMP address register by index (0-15) */
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static uint32_t read_pmpaddr(uint8_t idx)
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{
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switch (idx) {
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case 0:
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return read_csr_num(CSR_PMPADDR0);
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case 1:
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return read_csr_num(CSR_PMPADDR1);
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case 2:
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return read_csr_num(CSR_PMPADDR2);
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case 3:
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return read_csr_num(CSR_PMPADDR3);
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case 4:
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return read_csr_num(CSR_PMPADDR4);
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case 5:
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return read_csr_num(CSR_PMPADDR5);
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case 6:
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return read_csr_num(CSR_PMPADDR6);
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case 7:
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return read_csr_num(CSR_PMPADDR7);
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case 8:
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return read_csr_num(CSR_PMPADDR8);
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case 9:
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return read_csr_num(CSR_PMPADDR9);
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case 10:
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return read_csr_num(CSR_PMPADDR10);
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case 11:
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return read_csr_num(CSR_PMPADDR11);
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case 12:
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return read_csr_num(CSR_PMPADDR12);
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case 13:
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return read_csr_num(CSR_PMPADDR13);
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case 14:
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return read_csr_num(CSR_PMPADDR14);
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case 15:
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return read_csr_num(CSR_PMPADDR15);
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default:
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return 0;
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}
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}
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/* Write PMP address register by index (0-15) */
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static void write_pmpaddr(uint8_t idx, uint32_t val)
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{
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switch (idx) {
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case 0:
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write_csr_num(CSR_PMPADDR0, val);
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break;
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case 1:
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write_csr_num(CSR_PMPADDR1, val);
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break;
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case 2:
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write_csr_num(CSR_PMPADDR2, val);
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break;
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case 3:
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write_csr_num(CSR_PMPADDR3, val);
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break;
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case 4:
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write_csr_num(CSR_PMPADDR4, val);
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break;
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case 5:
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write_csr_num(CSR_PMPADDR5, val);
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break;
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case 6:
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write_csr_num(CSR_PMPADDR6, val);
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break;
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case 7:
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write_csr_num(CSR_PMPADDR7, val);
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break;
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case 8:
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write_csr_num(CSR_PMPADDR8, val);
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break;
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case 9:
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write_csr_num(CSR_PMPADDR9, val);
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break;
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case 10:
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write_csr_num(CSR_PMPADDR10, val);
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break;
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case 11:
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write_csr_num(CSR_PMPADDR11, val);
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break;
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case 12:
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write_csr_num(CSR_PMPADDR12, val);
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break;
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case 13:
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write_csr_num(CSR_PMPADDR13, val);
144+
break;
145+
case 14:
146+
write_csr_num(CSR_PMPADDR14, val);
147+
break;
148+
case 15:
149+
write_csr_num(CSR_PMPADDR15, val);
150+
break;
151+
}
152+
}
10153

11154
/* Static Memory Pools for Boot-time PMP Initialization
12155
*

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