Handle U-mode ecall for syscall dispatch

Adds exception handler for U-mode ecall instructions to dispatch
system calls. Defines ISR frame register indices as an enum and uses
them to extract syscall number and arguments from the saved register
context, returning results through the same mechanism.

This design enables privilege separation by allowing user-mode tasks
to request kernel services without direct access to privileged
operations, addressing the security issue where tasks could bypass
isolation by executing in M-mode.

Author: HeatCrab

arch/riscv/hal.c

@@ -42,6 +42,45 @@
  */
 #define ISR_STACK_FRAME_SIZE 128
 
+/* ISR frame register indices (as 32-bit word offsets from isr_sp).
+ * This layout matches the stack frame created by _isr in boot.c.
+ * Indices are in word offsets (divide byte offset by 4).
+ */
+enum {
+    FRAME_RA = 0,      /* x1  - Return Address */
+    FRAME_GP = 1,      /* x3  - Global Pointer */
+    FRAME_TP = 2,      /* x4  - Thread Pointer */
+    FRAME_T0 = 3,      /* x5  - Temporary register 0 */
+    FRAME_T1 = 4,      /* x6  - Temporary register 1 */
+    FRAME_T2 = 5,      /* x7  - Temporary register 2 */
+    FRAME_S0 = 6,      /* x8  - Saved register 0 / Frame Pointer */
+    FRAME_S1 = 7,      /* x9  - Saved register 1 */
+    FRAME_A0 = 8,      /* x10 - Argument/Return 0 */
+    FRAME_A1 = 9,      /* x11 - Argument/Return 1 */
+    FRAME_A2 = 10,     /* x12 - Argument 2 */
+    FRAME_A3 = 11,     /* x13 - Argument 3 */
+    FRAME_A4 = 12,     /* x14 - Argument 4 */
+    FRAME_A5 = 13,     /* x15 - Argument 5 */
+    FRAME_A6 = 14,     /* x16 - Argument 6 */
+    FRAME_A7 = 15,     /* x17 - Argument 7 / Syscall Number */
+    FRAME_S2 = 16,     /* x18 - Saved register 2 */
+    FRAME_S3 = 17,     /* x19 - Saved register 3 */
+    FRAME_S4 = 18,     /* x20 - Saved register 4 */
+    FRAME_S5 = 19,     /* x21 - Saved register 5 */
+    FRAME_S6 = 20,     /* x22 - Saved register 6 */
+    FRAME_S7 = 21,     /* x23 - Saved register 7 */
+    FRAME_S8 = 22,     /* x24 - Saved register 8 */
+    FRAME_S9 = 23,     /* x25 - Saved register 9 */
+    FRAME_S10 = 24,    /* x26 - Saved register 10 */
+    FRAME_S11 = 25,    /* x27 - Saved register 11 */
+    FRAME_T3 = 26,     /* x28 - Temporary register 3 */
+    FRAME_T4 = 27,     /* x29 - Temporary register 4 */
+    FRAME_T5 = 28,     /* x30 - Temporary register 5 */
+    FRAME_T6 = 29,     /* x31 - Temporary register 6 */
+    FRAME_MCAUSE = 30, /* Machine Cause CSR */
+    FRAME_EPC = 31     /* Machine Exception PC (mepc) */
+};
+
 /* Global variable to hold the new stack pointer for pending context switch.
  * When a context switch is needed, hal_switch_stack() saves the current SP
  * and stores the new SP here. The ISR epilogue then uses this value.
@@ -321,19 +360,43 @@ uint32_t do_trap(uint32_t cause, uint32_t epc, uint32_t isr_sp)
     } else { /* Synchronous Exception */
         uint32_t code = MCAUSE_GET_CODE(cause);
 
+        /* Handle ecall from U-mode - system calls */
+        if (code == MCAUSE_ECALL_UMODE) {
+            /* Advance mepc past the ecall instruction (4 bytes) */
+            uint32_t new_epc = epc + 4;
+            write_csr(mepc, new_epc);
+
+            /* Extract syscall arguments from ISR frame */
+            uint32_t *f = (uint32_t *) isr_sp;
+
+            int syscall_num = f[FRAME_A7];
+            void *arg1 = (void *) f[FRAME_A0];
+            void *arg2 = (void *) f[FRAME_A1];
+            void *arg3 = (void *) f[FRAME_A2];
+
+            /* Dispatch to syscall handler */
+            extern int syscall(int num, void *arg1, void *arg2, void *arg3);
+            int retval = syscall(syscall_num, arg1, arg2, arg3);
+
+            /* Store return value and updated PC */
+            f[FRAME_A0] = (uint32_t) retval;
+            f[FRAME_EPC] = new_epc;
+
+            return isr_sp;
+        }
+
         /* Handle ecall from M-mode - used for yielding in preemptive mode */
         if (code == MCAUSE_ECALL_MMODE) {
             /* Advance mepc past the ecall instruction (4 bytes) */
             uint32_t new_epc = epc + 4;
             write_csr(mepc, new_epc);
 
             /* Also update mepc in the ISR frame on the stack!
-             * The ISR epilogue will restore mepc from the frame (offset 31*4 =
-             * 124 bytes). If we don't update the frame, mret will jump back to
-             * the ecall instruction!
+             * The ISR epilogue will restore mepc from the frame. If we don't
+             * update the frame, mret will jump back to the ecall instruction!
              */
-            uint32_t *isr_frame = (uint32_t *) isr_sp;
-            isr_frame[31] = new_epc;
+            uint32_t *f = (uint32_t *) isr_sp;
+            f[FRAME_EPC] = new_epc;
 
             /* Invoke dispatcher for context switch - parameter 0 = from ecall,
              * don't increment ticks.