Merge pull request #85688 from swiftlang/jepa-main4

AnthonyLatsis · web-flow · commit 403bb36f8e22 · 2025-12-01T10:50:20.000Z
Address some issues building against LLVM next
diff --git a/lib/IRGen/GenCoro.cpp b/lib/IRGen/GenCoro.cpp
@@ -289,7 +289,7 @@ class GetDeallocThroughFn {
     ///   TaskAllocator Allocator;
     /// }
     struct PrivateLayout {
-      enum Kind {
+      enum Kind : uint8_t {
         Old32Bit,
         Old64Bit,
         New32BitSansEscalation,
diff --git a/lib/IRGen/IRGen.cpp b/lib/IRGen/IRGen.cpp
@@ -1145,8 +1145,7 @@ swift::createTargetMachine(const IRGenOptions &Opts, ASTContext &Ctx,
   }
 
   std::string Error;
-  const Target *Target =
-      TargetRegistry::lookupTarget(EffectiveTriple.str(), Error);
+  const Target *Target = TargetRegistry::lookupTarget(EffectiveTriple, Error);
   if (!Target) {
     Ctx.Diags.diagnose(SourceLoc(), diag::no_llvm_target, EffectiveTriple.str(),
                        Error);

Original file line number	Diff line number	Diff line change
`@@ -1145,8 +1145,7 @@ swift::createTargetMachine(const IRGenOptions &Opts, ASTContext &Ctx,`
`1145`	`1145`	`}`
`1146`	`1146`
`1147`	`1147`	`std::string Error;`
`1148`		`- const Target *Target =`
`1149`		`- TargetRegistry::lookupTarget(EffectiveTriple.str(), Error);`
	`1148`	`+ const Target *Target = TargetRegistry::lookupTarget(EffectiveTriple, Error);`
`1150`	`1149`	`if (!Target) {`
`1151`	`1150`	`Ctx.Diags.diagnose(SourceLoc(), diag::no_llvm_target, EffectiveTriple.str(),`
`1152`	`1151`	`Error);`