From 68f49496a035dc30e2c4a82a4b891916a83c3f46 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 5 Dec 2025 18:10:03 +0100 Subject: [PATCH 1/4] system(wl3) update STM32WL3x HAL Drivers to v1.3.1 Included in STM32CubeWL3 FW v1.3.1 Signed-off-by: Frederic Pillon --- .../STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h | 2 +- .../Inc/stm32wl3x_hal_i2c_ex.h | 18 +- .../Inc/stm32wl3x_hal_smbus_ex.h | 16 +- .../Inc/stm32wl3x_ll_dma.h | 104 ------- .../STM32WL3x_HAL_Driver/Release_Notes.html | 272 +++++++++++++----- .../Src/stm32wl3x_hal_flash_ex.c | 2 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 7 files changed, 220 insertions(+), 196 deletions(-) diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h index a91747987f..a99bef4ecc 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h @@ -49,7 +49,7 @@ extern "C" { */ #define __STM32WL3X_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32WL3X_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ -#define __STM32WL3X_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32WL3X_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32WL3X_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WL3X_HAL_VERSION ((__STM32WL3X_HAL_VERSION_MAIN << 24U)\ |(__STM32WL3X_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h index e3ad8763eb..f3395066a0 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h @@ -53,18 +53,20 @@ extern "C" { /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus * @{ */ -#if defined (I2C1) || defined (I2C2) +#if defined (I2C1) #define I2C_FASTMODEPLUS_PA0 SYSCFG_I2C_FMP_CTRL_I2C1_PA0_FMP /*!< Enable Fast Mode Plus on PA0 */ #define I2C_FASTMODEPLUS_PA1 SYSCFG_I2C_FMP_CTRL_I2C1_PA1_FMP /*!< Enable Fast Mode Plus on PA1 */ #define I2C_FASTMODEPLUS_PB6 SYSCFG_I2C_FMP_CTRL_I2C1_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ #define I2C_FASTMODEPLUS_PB7 SYSCFG_I2C_FMP_CTRL_I2C1_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ #define I2C_FASTMODEPLUS_PB10 SYSCFG_I2C_FMP_CTRL_I2C1_PB10_FMP /*!< Enable Fast Mode Plus on PB10 */ #define I2C_FASTMODEPLUS_PB11 SYSCFG_I2C_FMP_CTRL_I2C1_PB11_FMP /*!< Enable Fast Mode Plus on PB11 */ +#endif /* I2C1 */ +#if defined(I2C2) #define I2C_FASTMODEPLUS_PA6 SYSCFG_I2C_FMP_CTRL_I2C2_PA6_FMP /*!< Enable Fast Mode Plus on PA6 */ #define I2C_FASTMODEPLUS_PA7 SYSCFG_I2C_FMP_CTRL_I2C2_PA7_FMP /*!< Enable Fast Mode Plus on PA7 */ #define I2C_FASTMODEPLUS_PA13 SYSCFG_I2C_FMP_CTRL_I2C2_PA13_FMP /*!< Enable Fast Mode Plus on PA13 */ #define I2C_FASTMODEPLUS_PA14 SYSCFG_I2C_FMP_CTRL_I2C2_PA14_FMP /*!< Enable Fast Mode Plus on PA14 */ -#endif /* I2C1 || I2C2 */ +#endif /* I2C2 */ /** * @} */ @@ -128,18 +130,22 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) -#if defined(I2C1) || defined(I2C2) +#if defined(I2C1) #define IS_I2C_FASTMODEPLUS(__CONFIG__) ( \ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_PA0)) == I2C_FASTMODEPLUS_PA0) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_PA1)) == I2C_FASTMODEPLUS_PA1) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB10)) == I2C_FASTMODEPLUS_PB10) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB11)) == I2C_FASTMODEPLUS_PB11) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB11)) == I2C_FASTMODEPLUS_PB11) ) +#endif /* I2C1 */ + +#if defined(I2C2) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ( \ (((__CONFIG__) & (I2C_FASTMODEPLUS_PA6)) == I2C_FASTMODEPLUS_PA6) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_PA7)) == I2C_FASTMODEPLUS_PA7) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_PA13)) == I2C_FASTMODEPLUS_PA13) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA14)) == I2C_FASTMODEPLUS_PA14)) -#endif /* I2C1 || I2C2 */ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA14)) == I2C_FASTMODEPLUS_PA14) ) +#endif /* I2C2 */ /** * @} diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_smbus_ex.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_smbus_ex.h index 0adb1f2fd6..873d037138 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_smbus_ex.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_smbus_ex.h @@ -44,16 +44,20 @@ extern "C" { /** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus * @{ */ +#if defined (I2C1) #define SMBUS_FASTMODEPLUS_PA0 SYSCFG_I2C_FMP_CTRL_I2C1_PA0_FMP /*!< Enable Fast Mode Plus on PA0 */ #define SMBUS_FASTMODEPLUS_PA1 SYSCFG_I2C_FMP_CTRL_I2C1_PA1_FMP /*!< Enable Fast Mode Plus on PA1 */ #define SMBUS_FASTMODEPLUS_PB6 SYSCFG_I2C_FMP_CTRL_I2C1_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ #define SMBUS_FASTMODEPLUS_PB7 SYSCFG_I2C_FMP_CTRL_I2C1_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ #define SMBUS_FASTMODEPLUS_PB10 SYSCFG_I2C_FMP_CTRL_I2C1_PB10_FMP /*!< Enable Fast Mode Plus on PB10 */ #define SMBUS_FASTMODEPLUS_PB11 SYSCFG_I2C_FMP_CTRL_I2C1_PB11_FMP /*!< Enable Fast Mode Plus on PB11 */ +#endif /* I2C1 */ +#if defined(I2C2) #define SMBUS_FASTMODEPLUS_PA6 SYSCFG_I2C_FMP_CTRL_I2C2_PA6_FMP /*!< Enable Fast Mode Plus on PA6 */ #define SMBUS_FASTMODEPLUS_PA7 SYSCFG_I2C_FMP_CTRL_I2C2_PA7_FMP /*!< Enable Fast Mode Plus on PA7 */ #define SMBUS_FASTMODEPLUS_PA13 SYSCFG_I2C_FMP_CTRL_I2C2_PA13_FMP /*!< Enable Fast Mode Plus on PA13 */ #define SMBUS_FASTMODEPLUS_PA14 SYSCFG_I2C_FMP_CTRL_I2C2_PA14_FMP /*!< Enable Fast Mode Plus on PA14 */ +#endif /* I2C2 */ /** * @} */ @@ -110,19 +114,23 @@ void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); /** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros * @{ */ -#if defined(I2C1) || defined(I2C2) +#if defined(I2C1) #define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ( \ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA0)) == SMBUS_FASTMODEPLUS_PA0) || \ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA1)) == SMBUS_FASTMODEPLUS_PA1) || \ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB10)) == SMBUS_FASTMODEPLUS_PB10) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB11)) == SMBUS_FASTMODEPLUS_PB11) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB11)) == SMBUS_FASTMODEPLUS_PB11) ) +#endif /* I2C1 */ + +#if defined(I2C2) +#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ( \ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA6)) == SMBUS_FASTMODEPLUS_PA6) || \ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA7)) == SMBUS_FASTMODEPLUS_PA7) || \ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA13)) == SMBUS_FASTMODEPLUS_PA13) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA14)) == SMBUS_FASTMODEPLUS_PA14)) -#endif /* I2C1 || I2C2 */ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA14)) == SMBUS_FASTMODEPLUS_PA14) ) +#endif /* I2C2 */ /** * @} diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h index e49d7c53f5..b94790b322 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h @@ -433,7 +433,6 @@ typedef struct */ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -454,7 +453,6 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -475,7 +473,6 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); } @@ -512,7 +509,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); @@ -540,7 +536,6 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); } @@ -566,7 +561,6 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM)); } @@ -593,7 +587,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC, Mode); } @@ -617,7 +610,6 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC)); } @@ -642,7 +634,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC, PeriphOrM2MSrcIncMode); } @@ -666,7 +657,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC)); } @@ -691,7 +681,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC, MemoryOrM2MDstIncMode); } @@ -715,7 +704,6 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC)); } @@ -741,7 +729,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize); } @@ -766,7 +753,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE)); } @@ -792,7 +778,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE, MemoryOrM2MDstDataSize); } @@ -817,7 +802,6 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE)); } @@ -844,7 +828,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL, Priority); } @@ -870,7 +853,6 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL)); } @@ -895,7 +877,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT, NbData); } @@ -919,7 +900,6 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT)); } @@ -951,7 +931,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { - (void)DMAx; /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { @@ -986,7 +965,6 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -1010,7 +988,6 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress); } @@ -1032,7 +1009,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1054,7 +1030,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1078,7 +1053,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress); } @@ -1102,7 +1076,6 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -1124,7 +1097,6 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1146,7 +1118,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1169,7 +1140,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request); } @@ -1191,7 +1161,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID)); } @@ -1211,7 +1180,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); } @@ -1223,7 +1191,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); } @@ -1235,7 +1202,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); } @@ -1247,7 +1213,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); } @@ -1259,7 +1224,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); } @@ -1271,7 +1235,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); } @@ -1283,7 +1246,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); } @@ -1295,7 +1257,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL); } @@ -1307,7 +1268,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); } @@ -1319,7 +1279,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); } @@ -1331,7 +1290,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); } @@ -1343,7 +1301,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); } @@ -1355,7 +1312,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); } @@ -1367,7 +1323,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); } @@ -1379,7 +1334,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); } @@ -1391,7 +1345,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL); } @@ -1403,7 +1356,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); } @@ -1415,7 +1367,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); } @@ -1427,7 +1378,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); } @@ -1439,7 +1389,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); } @@ -1451,7 +1400,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); } @@ -1463,7 +1411,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); } @@ -1475,7 +1422,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); } @@ -1487,7 +1433,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL); } @@ -1499,7 +1444,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); } @@ -1511,7 +1455,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); } @@ -1523,7 +1466,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); } @@ -1535,7 +1477,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); } @@ -1547,7 +1488,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); } @@ -1559,7 +1499,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); } @@ -1571,7 +1510,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); } @@ -1583,7 +1521,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL); } @@ -1595,7 +1532,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); } @@ -1607,7 +1543,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); } @@ -1619,7 +1554,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); } @@ -1631,7 +1565,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); } @@ -1643,7 +1576,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); } @@ -1655,7 +1587,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); } @@ -1667,7 +1598,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); } @@ -1679,7 +1609,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8); } @@ -1691,7 +1620,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); } @@ -1703,7 +1631,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); } @@ -1715,7 +1642,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); } @@ -1727,7 +1653,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); } @@ -1739,7 +1664,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); } @@ -1751,7 +1675,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); } @@ -1763,7 +1686,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); } @@ -1775,7 +1697,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8); } @@ -1787,7 +1708,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); } @@ -1799,7 +1719,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); } @@ -1811,7 +1730,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); } @@ -1823,7 +1741,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); } @@ -1835,7 +1752,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); } @@ -1847,7 +1763,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); } @@ -1859,7 +1774,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); } @@ -1871,7 +1785,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8); } @@ -1883,7 +1796,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); } @@ -1895,7 +1807,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); } @@ -1907,7 +1818,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); } @@ -1919,7 +1829,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); } @@ -1931,7 +1840,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); } @@ -1943,7 +1851,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); } @@ -1955,7 +1862,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); } @@ -1967,7 +1873,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8); } @@ -1995,7 +1900,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -2016,7 +1920,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -2037,7 +1940,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -2058,7 +1960,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -2079,7 +1980,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -2100,7 +2000,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -2121,7 +2020,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); } @@ -2143,7 +2041,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); } @@ -2165,7 +2062,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WL3x_HAL_Driver/Release_Notes.html index ed3799a6d3..fccf365508 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WL3x_HAL_Driver/Release_Notes.html @@ -5,16 +5,27 @@ Release Notes for STM32CubeWL33 HAL Drivers Package - - @@ -24,52 +35,113 @@

Release Notes for

STM32WL3xx HAL Drivers

Copyright © 2024-2025 STMicroelectronics

- +

Purpose

-

The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

-

The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

-

The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:

-

BSP updates

@@ -109,47 +184,56 @@

Supported Devices and boards

  • NUCLEO-WL3RKB1 board
  • NUCLEO-WL3RKB2 board
    • -

    Backward compatibility

    +

    Backward compatibility

    -

    Known Limitations

    +

    Known Limitations

    -

    Dependencies

    +

    Dependencies

    -

    Notes

    +

    Notes

    - + +
    -

    Main Changes

    -

    Release of HAL and LL drivers for STM32WL3x devices

    -

    Contents

    -

    HAL Drivers updates

    +

    Main Changes

    +

    Release of +HAL and LL drivers for STM32WL3x +devices

    +

    Contents

    +

    HAL Drivers updates

    • HAL MRSUBG driver
        -
      • Fixed wrong length of SYNC word in wM-Bus packet initialization function.
        • +
      • Fixed wrong length of SYNC word in wM-Bus packet initialization +function.
      • Fixed HAL_MRSubG_Sequencer_Microseconds return value.
        • -
      • HAL_MRSUBG_TIMER_CPU_WKUP IRQ Handler moved from MRSUBG to MRSUBG TIMER.
        • +
      • HAL_MRSUBG_TIMER_CPU_WKUP IRQ Handler moved from MRSUBG to MRSUBG +TIMER.
      • Updated names for IRQ handlers.
    • HAL LPAWUR driver
        -
      • Added MspInit and MspDeInit functions to MRSUBG, MRSUBG TIMER, and LPAWUR.
        • +
      • Added MspInit and MspDeInit functions to MRSUBG, MRSUBG TIMER, and +LPAWUR.
    • HAL RCC driver
        -
      • Add LL RCC APIs to manage RTC clock: LL_RCC_EnableRTC(), LL_RCC_DisableRTC() and LL_RCC_IsEnabledRTC().
        • -
      • Added support for RCC_LPUART1_CLKSOURCE_16M with a frequency of 16,000,000.
        • +
      • Add LL RCC APIs to manage RTC clock: LL_RCC_EnableRTC(), +LL_RCC_DisableRTC() and LL_RCC_IsEnabledRTC().
        • +
      • Added support for RCC_LPUART1_CLKSOURCE_16M with a +frequency of 16,000,000.

    LL Drivers updates

    @@ -160,41 +244,48 @@

    LL Drivers updates

  • LL USART driver
      -
    • Solve Coverity out-of-bound memory access warning in use of USART_PRESCALER_TAB array.
      • +
    • Solve Coverity out-of-bound memory access warning in use of +USART_PRESCALER_TAB array.
  • LL LPUART driver
      -
    • Solve Coverity out-of-bound memory access warning in use of LPUART_PRESCALER_TAB array.
      • +
    • Solve Coverity out-of-bound memory access warning in use of +LPUART_PRESCALER_TAB array.
    • -

    Supported Devices and boards

    +

    Supported Devices and +boards

    • NUCLEO-WL33CC1 board
    • NUCLEO-WL33CC2 board
    -

    Backward compatibility

    +

    Backward compatibility

    • Not applicable
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Dependencies

    +

    Dependencies

    • None
    -

    Notes

    +

    Notes

    • None
    - + +
    -

    Main Changes

    -

    Release of HAL and LL drivers for STM32WL3x devices

    +

    Main Changes

    +

    Release +of HAL and LL drivers for STM32WL3x +devices

    Improved MRSUBG LL and HAL drivers with new APIs and macros:
    • @@ -236,92 +327,115 @@

      Release of HAL UART driver
      • Corrections in CHM/PDF rendering for HAL_UART
        • -
      • Provide accurate position in RxEventCallback when ReceptionToIdle mode is used with DMA, when UART and DMA interrupts process is delayed
        • -
      • Correct references to HAL_UARTEx_WakeupCallback and to HAL_UART_WAKEUP_CB_ID define, according to series capabilities
        • +
      • Provide accurate position in RxEventCallback when ReceptionToIdle +mode is used with DMA, when UART and DMA interrupts process is +delayed
        • +
      • Correct references to HAL_UARTEx_WakeupCallback and to +HAL_UART_WAKEUP_CB_ID define, according to series capabilities

    • LL LPUART driver
        -
      • Solve Coverity out-of-bound memory access warning in use of LPUART_PRESCALER_TAB array
        • +
      • Solve Coverity out-of-bound memory access warning in use of +LPUART_PRESCALER_TAB array
    • LL USART driver
        -
      • Solve Coverity out-of-bound memory access warning in use of USART_PRESCALER_TAB array
        • +
      • Solve Coverity out-of-bound memory access warning in use of +USART_PRESCALER_TAB array

    Check the code documentation for further details.

    -

    Contents

    +

    Contents

    • Release of HAL/LL drivers
        -

      • HAL: COMP, CORTEX, CRC, CRYP, DMA, FLASH, GPIO, I2C, IRDA, IWDG, LCD, LPAWUR, MRSUBG, PWR, RCC, RNG, RTC, SMARTCARD, SPI, TIM, UART, USART

        • -

      • LL: COMP, CRC, DMA, GPIO, I2C, LCSC, LPUART, LPAWUR, MRSUBG, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS

        • +

      • HAL: COMP, CORTEX, CRC, CRYP, DMA, FLASH, GPIO, +I2C, IRDA, IWDG, LCD, LPAWUR, MRSUBG, PWR, RCC, RNG, RTC, SMARTCARD, +SPI, TIM, UART, USART

        • +

      • LL: COMP, CRC, DMA, GPIO, I2C, LCSC, LPUART, +LPAWUR, MRSUBG, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS

    -

    Supported Devices and boards

    +

    Supported Devices and +boards

    • NUCLEO-WL33CC1 board
    • NUCLEO-WL33CC2 board
    -

    Backward compatibility

    +

    Backward compatibility

    • Not applicable
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Dependencies

    +

    Dependencies

    • None
    -

    Notes

    +

    Notes

    • None
    - + +
    -

    Main Changes

    -

    First Official Release of HAL and LL drivers for STM32WL33 devices

    -

    Contents

    +

    Main Changes

    +

    First +Official Release of HAL and LL drivers for +STM32WL33 devices

    +

    Contents

    • First Official Release of HAL/LL drivers
        -

      • HAL: COMP, CORTEX, CRC, CRYP, DMA, FLASH, GPIO, I2C, IRDA, IWDG, LCD, LPAWUR, MRSUBG, PWR, RCC, RNG, RTC, SMARTCARD, SPI, TIM, UART, USART

        • -

      • LL: COMP, CRC, DMA, GPIO, I2C, LCSC, LPUART, LPAWUR, MRSUBG, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS

        • +

      • HAL: COMP, CORTEX, CRC, CRYP, DMA, FLASH, GPIO, +I2C, IRDA, IWDG, LCD, LPAWUR, MRSUBG, PWR, RCC, RNG, RTC, SMARTCARD, +SPI, TIM, UART, USART

        • +

      • LL: COMP, CRC, DMA, GPIO, I2C, LCSC, LPUART, +LPAWUR, MRSUBG, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS

    -

    Supported Devices and boards

    +

    Supported Devices and +boards

    • NUCLEO-WL33CC board
    -

    Backward compatibility

    +

    Backward compatibility

    • Not applicable
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Dependencies

    +

    Dependencies

    • None
    -

    Notes

    +

    Notes

    • None
    - +