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Merge pull request #2869 from fpistm/stm32cubeWL3_update
chore(wl3): update to latest STM32CubeWL3 v1.3.1
2 parents 6798ca6 + b9131c2 commit dfdf369

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‎system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4042,6 +4042,7 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */
40424042
/* ============================================================================================================================*/
40434043
/*===================== SPI =====================*/
40444044
/* ============================================================================================================================*/
4045+
#define SPI_I2S_SUPPORT /*!< I2S support */
40454046

40464047
/* ===================================================== CR1 =====================================================*/
40474048
#define SPI_CR1_BIDIMODE_Pos (15UL) /*!<SPI CR1: BIDIMODE (Bit 15) */
@@ -4255,6 +4256,59 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */
42554256
#define SPI_TXCRCR_TXCRC_14 (0x4000U << SPI_TXCRCR_TXCRC_Pos)
42564257
#define SPI_TXCRCR_TXCRC_15 (0x8000U << SPI_TXCRCR_TXCRC_Pos)
42574258

4259+
/* ===================================================== I2SCFGR =====================================================*/
4260+
#define SPI_I2SCFGR_ASTRTEN_Pos (12UL) /*!<SPI I2SCFGR: ASTRTEN (Bit 12) */
4261+
#define SPI_I2SCFGR_ASTRTEN_Msk (0x1000UL) /*!< SPI I2SCFGR: ASTRTEN (Bitfield-Mask: 0x01) */
4262+
#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
4263+
#define SPI_I2SCFGR_I2SMOD_Pos (11UL) /*!<SPI I2SCFGR: I2SMOD (Bit 11) */
4264+
#define SPI_I2SCFGR_I2SMOD_Msk (0x800UL) /*!< SPI I2SCFGR: I2SMOD (Bitfield-Mask: 0x01) */
4265+
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
4266+
#define SPI_I2SCFGR_I2SE_Pos (10UL) /*!<SPI I2SCFGR: I2SE (Bit 10) */
4267+
#define SPI_I2SCFGR_I2SE_Msk (0x400UL) /*!< SPI I2SCFGR: I2SE (Bitfield-Mask: 0x01) */
4268+
#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
4269+
#define SPI_I2SCFGR_I2SCFG_Pos (8UL) /*!<SPI I2SCFGR: I2SCFG (Bit 8) */
4270+
#define SPI_I2SCFGR_I2SCFG_Msk (0x300UL) /*!< SPI I2SCFGR: I2SCFG (Bitfield-Mask: 0x03) */
4271+
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
4272+
#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos)
4273+
#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos)
4274+
#define SPI_I2SCFGR_PCMSYNC_Pos (7UL) /*!<SPI I2SCFGR: PCMSYNC (Bit 7) */
4275+
#define SPI_I2SCFGR_PCMSYNC_Msk (0x80UL) /*!< SPI I2SCFGR: PCMSYNC (Bitfield-Mask: 0x01) */
4276+
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
4277+
#define SPI_I2SCFGR_I2SSTD_Pos (4UL) /*!<SPI I2SCFGR: I2SSTD (Bit 4) */
4278+
#define SPI_I2SCFGR_I2SSTD_Msk (0x30UL) /*!< SPI I2SCFGR: I2SSTD (Bitfield-Mask: 0x03) */
4279+
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
4280+
#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos)
4281+
#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos)
4282+
#define SPI_I2SCFGR_CKPOL_Pos (3UL) /*!<SPI I2SCFGR: CKPOL (Bit 3) */
4283+
#define SPI_I2SCFGR_CKPOL_Msk (0x8UL) /*!< SPI I2SCFGR: CKPOL (Bitfield-Mask: 0x01) */
4284+
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
4285+
#define SPI_I2SCFGR_DATLEN_Pos (1UL) /*!<SPI I2SCFGR: DATLEN (Bit 1) */
4286+
#define SPI_I2SCFGR_DATLEN_Msk (0x6UL) /*!< SPI I2SCFGR: DATLEN (Bitfield-Mask: 0x03) */
4287+
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
4288+
#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos)
4289+
#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos)
4290+
#define SPI_I2SCFGR_CHLEN_Pos (0UL) /*!<SPI I2SCFGR: CHLEN (Bit 0) */
4291+
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL) /*!< SPI I2SCFGR: CHLEN (Bitfield-Mask: 0x01) */
4292+
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
4293+
4294+
/* ===================================================== I2SPR =====================================================*/
4295+
#define SPI_I2SPR_MCKOE_Pos (9UL) /*!<SPI I2SPR: MCKOE (Bit 9) */
4296+
#define SPI_I2SPR_MCKOE_Msk (0x200UL) /*!< SPI I2SPR: MCKOE (Bitfield-Mask: 0x01) */
4297+
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
4298+
#define SPI_I2SPR_ODD_Pos (8UL) /*!<SPI I2SPR: ODD (Bit 8) */
4299+
#define SPI_I2SPR_ODD_Msk (0x100UL) /*!< SPI I2SPR: ODD (Bitfield-Mask: 0x01) */
4300+
#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
4301+
#define SPI_I2SPR_I2SDIV_Pos (0UL) /*!<SPI I2SPR: I2SDIV (Bit 0) */
4302+
#define SPI_I2SPR_I2SDIV_Msk (0xffUL) /*!< SPI I2SPR: I2SDIV (Bitfield-Mask: 0xff) */
4303+
#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
4304+
#define SPI_I2SPR_I2SDIV_0 (0x1U << SPI_I2SPR_I2SDIV_Pos)
4305+
#define SPI_I2SPR_I2SDIV_1 (0x2U << SPI_I2SPR_I2SDIV_Pos)
4306+
#define SPI_I2SPR_I2SDIV_2 (0x4U << SPI_I2SPR_I2SDIV_Pos)
4307+
#define SPI_I2SPR_I2SDIV_3 (0x8U << SPI_I2SPR_I2SDIV_Pos)
4308+
#define SPI_I2SPR_I2SDIV_4 (0x10U << SPI_I2SPR_I2SDIV_Pos)
4309+
#define SPI_I2SPR_I2SDIV_5 (0x20U << SPI_I2SPR_I2SDIV_Pos)
4310+
#define SPI_I2SPR_I2SDIV_6 (0x40U << SPI_I2SPR_I2SDIV_Pos)
4311+
#define SPI_I2SPR_I2SDIV_7 (0x80U << SPI_I2SPR_I2SDIV_Pos)
42584312

42594313

42604314
/* ============================================================================================================================*/
@@ -11373,6 +11427,8 @@ typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */
1137311427
/******************************** SPI Instances *******************************/
1137411428
#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI3)
1137511429

11430+
/******************************** I2S Instances *******************************/
11431+
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI3))
1137611432

1137711433
/****************************** IWDG Instances ********************************/
1137811434
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)

‎system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3x.h‎

Lines changed: 1 addition & 1 deletion
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@@ -89,7 +89,7 @@
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*/
9090
#define __STM32WL3x_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
9191
#define __STM32WL3x_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
92-
#define __STM32WL3x_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
92+
#define __STM32WL3x_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
9393
#define __STM32WL3x_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
9494
#define __STM32WL3x_CMSIS_VERSION ((__STM32WL3x_CMSIS_VERSION_MAIN << 24U)\
9595
|(__STM32WL3x_CMSIS_VERSION_SUB1 << 16U)\

‎system/Drivers/CMSIS/Device/ST/STM32WL3x/Release_Notes.html‎

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@@ -60,11 +60,35 @@ <h1 id="purpose">Purpose</h1>
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<section id="update-history" class="col-sm-12 col-lg-8">
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<h1>Update history</h1>
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<div class="collapse">
63-
<input type="checkbox" id="collapse-section5" checked aria-hidden="true">
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<input type="checkbox" id="collapse-section6" checked aria-hidden="true">
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<label for="collapse-section6" aria-hidden="true"> <strong>V1.3.1 /
65+
20-November-2025</strong> </label>
66+
<div>
67+
<h2 id="main-changes">Main Changes</h2>
68+
<ul>
69+
<li>Added missing I2S support on WL3Rx devices (stm32wl3rx.h)</li>
70+
</ul>
71+
<h2 id="known-limitations">Known Limitations</h2>
72+
<ul>
73+
<li>None</li>
74+
</ul>
75+
<h2 id="development-toolchains-and-compilers">Development Toolchains and
76+
Compilers</h2>
77+
<ul>
78+
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
79+
</ul>
80+
<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
81+
<ul>
82+
<li>STM32WL3xx devices</li>
83+
</ul>
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</div>
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</div>
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<div class="collapse">
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<input type="checkbox" id="collapse-section5" aria-hidden="true">
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<label for="collapse-section5" aria-hidden="true"> <strong>V1.3.0 /
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29-October-2025</strong> </label>
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<div>
67-
<h2 id="main-changes">Main Changes</h2>
91+
<h2 id="main-changes-1">Main Changes</h2>
6892
<ul>
6993
<li>Added support to STM32WL3Rx product line.</li>
7094
<li>[LCSC] LCSC_VER register removed from the accessible register list,
@@ -74,16 +98,17 @@ <h2 id="main-changes">Main Changes</h2>
7498
<li>[MRSUBG] RSSI_FLT bit #3 renamed to
7599
<code>FREEZE_SYNC_ON_SYNC_OOK_PEAK_DECAY</code></li>
76100
</ul>
77-
<h2 id="known-limitations">Known Limitations</h2>
101+
<h2 id="known-limitations-1">Known Limitations</h2>
78102
<ul>
79103
<li>None</li>
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</ul>
81-
<h2 id="development-toolchains-and-compilers">Development Toolchains and
82-
Compilers</h2>
105+
<h2 id="development-toolchains-and-compilers-1">Development Toolchains
106+
and Compilers</h2>
83107
<ul>
84108
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
85109
</ul>
86-
<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
110+
<h2 id="supported-devices-and-boards-1">Supported Devices and
111+
boards</h2>
87112
<ul>
88113
<li>STM32WL3xx devices</li>
89114
</ul>
@@ -94,7 +119,7 @@ <h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
94119
<label for="collapse-section3" aria-hidden="true"> <strong>V1.2.0 /
95120
04-June-2025</strong> </label>
96121
<div>
97-
<h2 id="main-changes-1">Main Changes</h2>
122+
<h2 id="main-changes-2">Main Changes</h2>
98123
<ul>
99124
<li>Documentation based on jQuery 1.7.1 removed</li>
100125
</ul>
@@ -104,17 +129,17 @@ <h2 id="contents">Contents</h2>
104129
<li>Renamed some interrupt to improve clarity and consistency</li>
105130
<li>Added FQCY_BAND_ID bits definition for RF_INFO_OUT register</li>
106131
</ul>
107-
<h2 id="known-limitations-1">Known Limitations</h2>
132+
<h2 id="known-limitations-2">Known Limitations</h2>
108133
<ul>
109134
<li>CMSIS devices files are delivered “as is” and have not been fully
110135
validated</li>
111136
</ul>
112-
<h2 id="development-toolchains-and-compilers-1">Development Toolchains
137+
<h2 id="development-toolchains-and-compilers-2">Development Toolchains
113138
and Compilers</h2>
114139
<ul>
115140
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
116141
</ul>
117-
<h2 id="supported-devices-and-boards-1">Supported Devices and
142+
<h2 id="supported-devices-and-boards-2">Supported Devices and
118143
boards</h2>
119144
<ul>
120145
<li>STM32WL3xx devices</li>
@@ -126,7 +151,7 @@ <h2 id="supported-devices-and-boards-1">Supported Devices and
126151
<label for="collapse-section2" aria-hidden="true"> <strong>V1.1.0 /
127152
05-February-2025</strong> </label>
128153
<div>
129-
<h2 id="main-changes-2">Main Changes</h2>
154+
<h2 id="main-changes-3">Main Changes</h2>
130155
<h3 id="release">Release</h3>
131156
<ul>
132157
<li>Release of CMSIS for STM32WL3xx devices</li>
@@ -135,17 +160,17 @@ <h2 id="contents-1">Contents</h2>
135160
<ul>
136161
<li>CMSIS devices files for STM32WL3xx</li>
137162
</ul>
138-
<h2 id="known-limitations-2">Known Limitations</h2>
163+
<h2 id="known-limitations-3">Known Limitations</h2>
139164
<ul>
140165
<li>CMSIS devices files are delivered “as is” and have not been fully
141166
validated</li>
142167
</ul>
143-
<h2 id="development-toolchains-and-compilers-2">Development Toolchains
168+
<h2 id="development-toolchains-and-compilers-3">Development Toolchains
144169
and Compilers</h2>
145170
<ul>
146171
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
147172
</ul>
148-
<h2 id="supported-devices-and-boards-2">Supported Devices and
173+
<h2 id="supported-devices-and-boards-3">Supported Devices and
149174
boards</h2>
150175
<ul>
151176
<li>STM32WL3xx devices</li>
@@ -157,7 +182,7 @@ <h2 id="supported-devices-and-boards-2">Supported Devices and
157182
<label for="collapse-section1" aria-hidden="true"> <strong>V1.0.0 /
158183
30-October-2024</strong> </label>
159184
<div>
160-
<h2 id="main-changes-3">Main Changes</h2>
185+
<h2 id="main-changes-4">Main Changes</h2>
161186
<h3 id="first-release">First Release</h3>
162187
<ul>
163188
<li>First Official Release of CMSIS for STM32WL33x devices</li>
@@ -166,17 +191,17 @@ <h2 id="contents-2">Contents</h2>
166191
<ul>
167192
<li>CMSIS devices files for STM32WL33x</li>
168193
</ul>
169-
<h2 id="known-limitations-3">Known Limitations</h2>
194+
<h2 id="known-limitations-4">Known Limitations</h2>
170195
<ul>
171196
<li>CMSIS devices files are delivered “as is” and have not been fully
172197
validated</li>
173198
</ul>
174-
<h2 id="development-toolchains-and-compilers-3">Development Toolchains
199+
<h2 id="development-toolchains-and-compilers-4">Development Toolchains
175200
and Compilers</h2>
176201
<ul>
177202
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1</li>
178203
</ul>
179-
<h2 id="supported-devices-and-boards-3">Supported Devices and
204+
<h2 id="supported-devices-and-boards-4">Supported Devices and
180205
boards</h2>
181206
<ul>
182207
<li>STM32WL33x devices</li>

‎system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md‎

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Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@
2323
* STM32WB0: 1.4.0
2424
* STM32WBA: 1.8.0
2525
* STM32WL: 1.3.0
26-
* STM32WL3: 1.3.0
26+
* STM32WL3: 1.3.1
2727

2828
Release notes of each STM32YYxx CMSIS available here:
2929

‎system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ extern "C" {
4949
*/
5050
#define __STM32WL3X_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
5151
#define __STM32WL3X_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
52-
#define __STM32WL3X_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
52+
#define __STM32WL3X_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
5353
#define __STM32WL3X_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
5454
#define __STM32WL3X_HAL_VERSION ((__STM32WL3X_HAL_VERSION_MAIN << 24U)\
5555
|(__STM32WL3X_HAL_VERSION_SUB1 << 16U)\

‎system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h‎

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -53,18 +53,20 @@ extern "C" {
5353
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
5454
* @{
5555
*/
56-
#if defined (I2C1) || defined (I2C2)
56+
#if defined (I2C1)
5757
#define I2C_FASTMODEPLUS_PA0 SYSCFG_I2C_FMP_CTRL_I2C1_PA0_FMP /*!< Enable Fast Mode Plus on PA0 */
5858
#define I2C_FASTMODEPLUS_PA1 SYSCFG_I2C_FMP_CTRL_I2C1_PA1_FMP /*!< Enable Fast Mode Plus on PA1 */
5959
#define I2C_FASTMODEPLUS_PB6 SYSCFG_I2C_FMP_CTRL_I2C1_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
6060
#define I2C_FASTMODEPLUS_PB7 SYSCFG_I2C_FMP_CTRL_I2C1_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
6161
#define I2C_FASTMODEPLUS_PB10 SYSCFG_I2C_FMP_CTRL_I2C1_PB10_FMP /*!< Enable Fast Mode Plus on PB10 */
6262
#define I2C_FASTMODEPLUS_PB11 SYSCFG_I2C_FMP_CTRL_I2C1_PB11_FMP /*!< Enable Fast Mode Plus on PB11 */
63+
#endif /* I2C1 */
64+
#if defined(I2C2)
6365
#define I2C_FASTMODEPLUS_PA6 SYSCFG_I2C_FMP_CTRL_I2C2_PA6_FMP /*!< Enable Fast Mode Plus on PA6 */
6466
#define I2C_FASTMODEPLUS_PA7 SYSCFG_I2C_FMP_CTRL_I2C2_PA7_FMP /*!< Enable Fast Mode Plus on PA7 */
6567
#define I2C_FASTMODEPLUS_PA13 SYSCFG_I2C_FMP_CTRL_I2C2_PA13_FMP /*!< Enable Fast Mode Plus on PA13 */
6668
#define I2C_FASTMODEPLUS_PA14 SYSCFG_I2C_FMP_CTRL_I2C2_PA14_FMP /*!< Enable Fast Mode Plus on PA14 */
67-
#endif /* I2C1 || I2C2 */
69+
#endif /* I2C2 */
6870
/**
6971
* @}
7072
*/
@@ -128,18 +130,22 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
128130

129131
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
130132

131-
#if defined(I2C1) || defined(I2C2)
133+
#if defined(I2C1)
132134
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ( \
133135
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
134136
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA0)) == I2C_FASTMODEPLUS_PA0) || \
135137
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA1)) == I2C_FASTMODEPLUS_PA1) || \
136138
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB10)) == I2C_FASTMODEPLUS_PB10) || \
137-
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB11)) == I2C_FASTMODEPLUS_PB11) || \
139+
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB11)) == I2C_FASTMODEPLUS_PB11) )
140+
#endif /* I2C1 */
141+
142+
#if defined(I2C2)
143+
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ( \
138144
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA6)) == I2C_FASTMODEPLUS_PA6) || \
139145
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA7)) == I2C_FASTMODEPLUS_PA7) || \
140146
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA13)) == I2C_FASTMODEPLUS_PA13) || \
141-
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA14)) == I2C_FASTMODEPLUS_PA14))
142-
#endif /* I2C1 || I2C2 */
147+
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA14)) == I2C_FASTMODEPLUS_PA14) )
148+
#endif /* I2C2 */
143149

144150
/**
145151
* @}

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