[L5] Update STM32L5xx HAL Drivers to v1.0.4

Included in STM32CubeL5 FW v1.4.0

Signed-off-by: Frederic Pillon <frederic.pillon@st.com>

Author: fpistm

system/Drivers/STM32L5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

@@ -24,7 +24,7 @@
 #define STM32_ASSERT_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Exported types ------------------------------------------------------------*/

system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32_assert_template.h

@@ -23,7 +23,7 @@
 #define STM32L5xx_HAL_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -204,8 +204,8 @@ typedef enum
 #define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
 
 /**
- * @}
- */
+  * @}
+  */
 
 /** @defgroup SYSCFG_Lock_items SYSCFG Lock items
   * @brief SYSCFG items to set lock on
@@ -395,15 +395,15 @@ typedef enum
   */
 #define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__)    do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
                                                                 SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
-                                                            }while(0)
+                                                               }while(0)
 
 /** @brief  SRAM2 page 32 to 63 write protection enable macro
   * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
   * @note   Write protection can only be disabled by a system reset
   */
 #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
                                                                 SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\
-                                                            }while(0)
+                                                               }while(0)
 
 /** @brief  SRAM2 page write protection unlock prior to erase
   * @note   Writing a wrong key reactivates the write protection
@@ -422,11 +422,11 @@ typedef enum
   */
 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
                                                                 SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\
-                                                            }while(0)
+                                                               }while(0)
 
 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
                                                                 CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\
-                                                            }while(0)
+                                                               }while(0)
 
 /** @brief  SYSCFG Break ECC lock.
   *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
@@ -459,7 +459,8 @@ typedef enum
   *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
-#define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
+#define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
+                                                & (__FLAG__))!= 0U) ? 1U : 0U)
 
 /** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.
   */
@@ -587,7 +588,7 @@ HAL_StatusTypeDef HAL_Init(void);
 HAL_StatusTypeDef HAL_DeInit(void);
 void              HAL_MspInit(void);
 void              HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
 
 /**
   * @}