add clock bypass (#126)

Author: dotcypress

src/rcc/config.rs

@@ -53,9 +53,11 @@ pub enum PLLSrc {
 /// RTC clock input source
 #[derive(Clone, Copy)]
 pub enum RTCSrc {
-    LSE = 0b01,
-    LSI = 0b10,
-    HSE = 0b11,
+    LSE,
+    LSE_BYPASS,
+    LSI,
+    HSE,
+    HSE_BYPASS,
 }
 
 /// PLL divider

src/rcc/mod.rs

@@ -301,19 +301,37 @@ impl Rcc {
     }
 
     pub(crate) fn enable_rtc(&self, src: RTCSrc) {
-        match src {
-            RTCSrc::LSI => self.enable_lsi(),
-            RTCSrc::HSE => self.enable_hse(false),
-            RTCSrc::LSE => self.enable_lse(false),
-        }
+        let rtc_sel = match src {
+            RTCSrc::LSE => {
+                self.enable_lse(false);
+                0b01
+            }
+            RTCSrc::LSE_BYPASS => {
+                self.enable_lse(true);
+                0b01
+            }
+            RTCSrc::LSI => {
+                self.enable_lsi();
+                0b10
+            }
+            RTCSrc::HSE => {
+                self.enable_hse(false);
+                0b11
+            }
+            RTCSrc::HSE_BYPASS => {
+                self.enable_hse(true);
+                0b11
+            }
+        };
+
         self.apbenr1
             .modify(|_, w| w.rtcapben().set_bit().pwren().set_bit());
         self.apbsmenr1.modify(|_, w| w.rtcapbsmen().set_bit());
         self.unlock_rtc();
         self.bdcr.modify(|_, w| w.bdrst().set_bit());
         self.bdcr.modify(|_, w| unsafe {
             w.rtcsel()
-                .bits(src as u8)
+                .bits(rtc_sel)
                 .rtcen()
                 .set_bit()
                 .bdrst()