fix(breaking): clippy lints (#18)

Signed-off-by: Martin Kröning <martin.kroening@eonerc.rwth-aachen.de>

Author: mkroening

src/capability/msi.rs

@@ -83,8 +83,7 @@ impl MsiCapability {
     }
 
     pub fn ctrl(&self, access: &impl ConfigRegionAccess) -> u32 {
-        let reg = unsafe { access.read(self.address.address, self.address.offset) };
-        reg
+        unsafe { access.read(self.address.address, self.address.offset) }
     }
 
     /// Is MSI capability enabled?

src/lib.rs

@@ -76,7 +76,19 @@ pub type InterruptPin = u8;
 // TODO: documentation
 pub trait ConfigRegionAccess {
     fn function_exists(&self, address: PciAddress) -> bool;
+
+    /// Performs a PCI read at `address` with `offset`.
+    /// 
+    /// # Safety
+    /// 
+    /// `address` and `offset` must be valid for PCI reads.
     unsafe fn read(&self, address: PciAddress, offset: u16) -> u32;
+
+    /// Performs a PCI write at `address` with `offset`.
+    /// 
+    /// # Safety
+    /// 
+    /// `address` and `offset` must be valid for PCI writes.
     unsafe fn write(&self, address: PciAddress, offset: u16, value: u32);
 }
 
@@ -288,7 +300,7 @@ impl EndpointHeader {
         /*
          * If bit 0 is `0`, the BAR is in memory. If it's `1`, it's in I/O.
          */
-        if bar.get_bit(0) == false {
+        if !bar.get_bit(0) {
             let prefetchable = bar.get_bit(3);
             let address = bar.get_bits(4..32) << 4;
 
@@ -358,10 +370,13 @@ impl EndpointHeader {
         }
     }
 
-    /// Write to a BAR, setting the address for a device to use. The supplied value must be a valid
-    /// BAR value (refer to the PCIe specification for requirements) and must be of the correct
-    /// size (i.e. no larger than `u32::MAX` for 32-bit BARs). In the case of a 64-bit BAR, the
-    /// supplied slot should be the first slot of the pair.
+    /// Write to a BAR, setting the address for a device to use.
+    /// 
+    /// # Safety
+    /// 
+    /// The supplied value must be a valid BAR value (refer to the PCIe specification for
+    /// requirements) and must be of the correct size (i.e. no larger than `u32::MAX` for 32-bit
+    /// BARs). In the case of a 64-bit BAR, the supplied slot should be the first slot of the pair.
     pub unsafe fn write_bar(
         &mut self,
         slot: u8,
@@ -388,7 +403,7 @@ impl EndpointHeader {
                 }
                 Ok(())
             }
-            None => return Err(BarWriteError::NoSuchBar),
+            None => Err(BarWriteError::NoSuchBar),
         }
     }
 

src/register.rs

@@ -1,7 +1,7 @@
 use bit_field::BitField;
 use core::{
     convert::TryFrom,
-    fmt::{Debug, Formatter},
+    fmt::{self, Debug, Formatter},
 };
 
 /// Slowest time that a device will assert DEVSEL# for any bus command except Configuration Space
@@ -13,15 +13,26 @@ pub enum DevselTiming {
     Slow = 0x2,
 }
 
+#[derive(Debug)]
+pub struct TryFromDevselTimingError {
+    number: u8,
+}
+
+impl fmt::Display for TryFromDevselTimingError {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "No discriminant in `DevselTiming` matches the value `{}`", self.number)
+    }
+}
+
 impl TryFrom<u8> for DevselTiming {
-    type Error = ();
+    type Error = TryFromDevselTimingError;
 
     fn try_from(value: u8) -> Result<Self, Self::Error> {
         match value {
             0x0 => Ok(DevselTiming::Fast),
             0x1 => Ok(DevselTiming::Medium),
             0x2 => Ok(DevselTiming::Slow),
-            _ => Err(()),
+            number => Err(TryFromDevselTimingError { number }),
         }
     }
 }
@@ -64,7 +75,7 @@ impl StatusRegister {
     /// Configuration Space read and writes.
     ///
     /// For PCIe always set to `Fast`
-    pub fn devsel_timing(&self) -> Result<DevselTiming, ()> {
+    pub fn devsel_timing(&self) -> Result<DevselTiming, TryFromDevselTimingError> {
         let bits = self.0.get_bits(9..11);
         DevselTiming::try_from(bits as u8)
     }