Add basic configuration of MSI-X capabilities

Author: IsaacWoods

src/capability/mod.rs

@@ -3,8 +3,10 @@ use bit_field::BitField;
 use core::fmt::Formatter;
 
 mod msi;
+mod msix;
 
 pub use msi::{MsiCapability, MultipleMessageSupport, TriggerMode};
+pub use msix::MsixCapability;
 
 #[derive(Clone)]
 pub struct PciCapabilityAddress {
@@ -52,16 +54,18 @@ pub enum PciCapability {
     /// PCI Express capability, Cap ID = `0x10`
     PciExpress(PciCapabilityAddress),
     /// MSI-X capability, Cap ID = `0x11`
-    MsiX(PciCapabilityAddress),
+    MsiX(MsixCapability),
     /// Unknown capability
-    Unknown {
-        address: PciCapabilityAddress,
-        id: u8,
-    },
+    Unknown { address: PciCapabilityAddress, id: u8 },
 }
 
 impl PciCapability {
-    fn parse(id: u8, address: PciCapabilityAddress, extension: u16) -> Option<PciCapability> {
+    fn parse(
+        id: u8,
+        address: PciCapabilityAddress,
+        extension: u16,
+        access: &impl ConfigRegionAccess,
+    ) -> Option<PciCapability> {
         match id {
             0x00 => None, // null capability
             0x01 => Some(PciCapability::PowerManagement(address)),
@@ -79,7 +83,7 @@ impl PciCapability {
             0x0D => Some(PciCapability::BridgeSubsystemVendorId(address)),
             0x0E => Some(PciCapability::AGP3(address)),
             0x10 => Some(PciCapability::PciExpress(address)),
-            0x11 => Some(PciCapability::MsiX(address)),
+            0x11 => Some(PciCapability::MsiX(MsixCapability::new(address, extension, access))),
             _ => Some(PciCapability::Unknown { address, id }),
         }
     }
@@ -92,16 +96,8 @@ pub struct CapabilityIterator<'a, T: ConfigRegionAccess> {
 }
 
 impl<'a, T: ConfigRegionAccess> CapabilityIterator<'a, T> {
-    pub(crate) fn new(
-        address: PciAddress,
-        offset: u16,
-        access: &'a T,
-    ) -> CapabilityIterator<'a, T> {
-        CapabilityIterator {
-            address,
-            offset,
-            access,
-        }
+    pub(crate) fn new(address: PciAddress, offset: u16, access: &'a T) -> CapabilityIterator<'a, T> {
+        CapabilityIterator { address, offset, access }
     }
 }
 
@@ -119,11 +115,9 @@ impl<'a, T: ConfigRegionAccess> Iterator for CapabilityIterator<'a, T> {
             let extension = data.get_bits(16..32) as u16;
             let cap = PciCapability::parse(
                 id as u8,
-                PciCapabilityAddress {
-                    address: self.address,
-                    offset: self.offset,
-                },
+                PciCapabilityAddress { address: self.address, offset: self.offset },
                 extension,
+                self.access,
             );
             self.offset = next_ptr as u16;
             if let Some(cap) = cap {

src/capability/msix.rs

@@ -0,0 +1,67 @@
+use super::{PciCapabilityAddress, TriggerMode};
+use crate::ConfigRegionAccess;
+use bit_field::BitField;
+
+#[derive(Clone, Debug)]
+pub struct MsixCapability {
+    address: PciCapabilityAddress,
+    table_size: u16,
+    /// Table BAR in bits 0..3 and offset into that BAR in bits 3..31
+    table: u32,
+    /// Pending Bit Array BAR in bits 0..3 and offset into that BAR in bits 3..31
+    pba: u32,
+}
+
+impl MsixCapability {
+    pub(crate) fn new(
+        address: PciCapabilityAddress,
+        control: u16,
+        access: &impl ConfigRegionAccess,
+    ) -> MsixCapability {
+        let table_size = control.get_bits(0..11) + 1;
+        let table = unsafe { access.read(address.address, address.offset + 0x04) };
+        let pba = unsafe { access.read(address.address, address.offset + 0x08) };
+        MsixCapability { address, table_size, table, pba }
+    }
+
+    /// Enable MSI-X on the specified device feature.
+    ///
+    /// Unlike with MSI, the MSI message data and delivery address is not contained within the
+    /// capability, but instead in system memory, and pointed to by the BAR specified by
+    /// `[MsixCapability::table_bar]` and `[MsixCapability::table_offset]`. The caller is therefore
+    /// responsible for configuring this separately, as this crate does not have access to
+    /// arbitrary physical memory.
+    pub fn set_enabled(&mut self, enabled: bool, access: &impl ConfigRegionAccess) {
+        let mut control = unsafe { access.read(self.address.address, self.address.offset) };
+        control.set_bit(31, enabled);
+        unsafe {
+            access.write(self.address.address, self.address.offset, control);
+        }
+    }
+
+    /// The index of the BAR that contains the MSI-X table.
+    pub fn table_bar(&self) -> u8 {
+        self.table.get_bits(0..3) as u8
+    }
+
+    /// The offset, in bytes, of the MSI-X table within its BAR.
+    pub fn table_offset(&self) -> u32 {
+        /*
+         * To form the offset into the BAR, we mask off (set to zero) the lowest 3 bits, but
+         * they're retained as part of the offset.
+         */
+        self.table & !0b111
+    }
+
+    pub fn pba_bar(&self) -> u8 {
+        self.pba.get_bits(0..3) as u8
+    }
+
+    pub fn pba_offset(&self) -> u32 {
+        /*
+         * To form the offset into the BAR, we mask off (set to zero) the lowest 3 bits, but
+         * they're retained as part of the offset.
+         */
+        self.pba & !0b111
+    }
+}