We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent c330ed0 commit 7d9d09dCopy full SHA for 7d9d09d
riscv-rt/src/lib.rs
@@ -565,6 +565,15 @@
565
//!
566
//! Saves a little code size if there is only one hart on the target.
567
568
+//! ## `no-mhartid`
569
+//!
570
+//! Skips reading `mhartid` and uses 0 instead. Useful for targets that doesn't implement this instruction.
571
+//! Automatically enables `single-hart`.
572
573
+//! ## `no-xtvec`
574
575
+//! Skips interrupts setup.
576
577
//! ## `s-mode`
578
579
//! Supervisor mode. While most registers/instructions have variants for both `mcause` and
0 commit comments