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riscv-rt/src/lib.rs

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//!
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//! Saves a little code size if there is only one hart on the target.
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//!
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//! ## `no-mhartid`
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//!
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//! Skips reading `mhartid` and uses 0 instead. Useful for targets that doesn't implement this instruction.
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//! Automatically enables `single-hart`.
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//!
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//! ## `no-xtvec`
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//!
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//! Skips interrupts setup.
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//!
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//! ## `s-mode`
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//!
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//! Supervisor mode. While most registers/instructions have variants for both `mcause` and

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