Merge pull request #378 from KushalMeghani1644/add-qemu-ci-v2

Add QEMU CI support

Author: romancardenas

.github/workflows/qemu.yaml

@@ -0,0 +1,59 @@
+name: QEMU tests
+on:
+  merge_group:
+  pull_request:
+  push:
+    branches:
+      - master
+
+env:
+  CARGO_TERM_COLOR: always
+
+jobs:
+  testexamples:
+    name: QEMU run
+    runs-on: ubuntu-24.04
+    strategy:
+      fail-fast: false
+      matrix:
+        toolchain: [stable]
+        target-qemu:
+          - target: riscv32i-unknown-none-elf
+            qemu: riscv32
+          - target: riscv32im-unknown-none-elf
+            qemu: riscv32
+          - target: riscv32imc-unknown-none-elf
+            qemu: riscv32
+          - target: riscv32imac-unknown-none-elf
+            qemu: riscv32
+          - target: riscv32imafc-unknown-none-elf
+            qemu: riscv32
+          - target: riscv64imac-unknown-none-elf
+            qemu: riscv64
+          - target: riscv64gc-unknown-none-elf
+            qemu: riscv64
+        example:
+          - qemu_uart
+          - qemu_semihosting
+
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+
+      - name: Configure Rust target ${{ matrix.target-qemu.target }}
+        run: |
+          rustup toolchain install ${{ matrix.toolchain }}
+          rustup default ${{ matrix.toolchain }}
+          rustup target add ${{ matrix.target-qemu.target }}
+
+      - name: Cache Dependencies
+        uses: Swatinem/rust-cache@v2
+
+      - name: Install QEMU
+        run: |
+          sudo apt update
+          sudo apt install -y qemu-system-${{ matrix.target-qemu.qemu }}
+
+      - name: Run-pass tests
+        run: cargo run --package xtask -- qemu --target ${{ matrix.target-qemu.target }} --example ${{ matrix.example }}
+

Cargo.toml

@@ -11,6 +11,7 @@ members = [
     "riscv-types",
     "tests-build",
     "tests-trybuild",
+    "xtask",
 ]
 
 default-members = [

ci/expected/qemu_semihosting.run

@@ -0,0 +1 @@
+Hello from semihosting!

ci/expected/qemu_uart.run

@@ -0,0 +1 @@
+Hello from UART!

riscv-rt/CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
+- Added examples for CI tests using semihosting and UART
 - New `no-mhartid` feature to load 0 to `a0` instead of reading `mhartid`.
 - New `no-xtvec` feature that removes interrupt stuff.
 

riscv-rt/Cargo.toml

@@ -32,6 +32,8 @@ defmt = { version = "1.0.1", optional = true }
 
 [dev-dependencies]
 panic-halt = "1.0.0"
+riscv-semihosting = { path = "../riscv-semihosting", version = "0.2.1" }
+riscv = { path = "../riscv", version = "0.15.0", features = ["critical-section-single-hart"] }
 
 [features]
 pre-init = []

riscv-rt/examples/device_virt.x

@@ -0,0 +1,11 @@
+MEMORY
+{
+    RAM : ORIGIN = 0x80000000, LENGTH = 16M
+}
+REGION_ALIAS("REGION_TEXT", RAM);
+REGION_ALIAS("REGION_RODATA", RAM);
+REGION_ALIAS("REGION_DATA", RAM);
+REGION_ALIAS("REGION_BSS", RAM);
+REGION_ALIAS("REGION_HEAP", RAM);
+REGION_ALIAS("REGION_STACK", RAM);
+INCLUDE link.x

riscv-rt/examples/qemu_semihosting.rs

@@ -0,0 +1,22 @@
+//! Semihosting example for QEMU
+//!
+//! This example uses RISC-V semihosting to print output and cleanly exit QEMU.
+//! Run with: `qemu-system-riscv32 -machine virt -nographic -semihosting-config enable=on,target=native -bios none -kernel <binary>`
+
+#![no_std]
+#![no_main]
+
+extern crate panic_halt;
+
+use riscv_rt::entry;
+use riscv_semihosting::{
+    debug::{self, EXIT_SUCCESS},
+    hprintln,
+};
+
+#[entry]
+fn main() -> ! {
+    hprintln!("Hello from semihosting!");
+    debug::exit(EXIT_SUCCESS);
+    loop {}
+}

riscv-rt/examples/qemu_uart.rs

@@ -0,0 +1,61 @@
+//! UART example for QEMU virt machine
+//!
+//! This example demonstrates direct UART output on QEMU's virt machine.
+//! It writes to the NS16550-compatible UART at 0x1000_0000.
+
+#![no_std]
+#![no_main]
+
+extern crate panic_halt;
+
+use riscv_rt::entry;
+use riscv_semihosting::debug::{self, EXIT_SUCCESS};
+
+const UART_BASE: usize = 0x1000_0000;
+const UART_THR: usize = UART_BASE;
+const UART_IER: usize = UART_BASE + 1;
+const UART_FCR: usize = UART_BASE + 2;
+const UART_LCR: usize = UART_BASE + 3;
+const UART_LSR: usize = UART_BASE + 5;
+const LCR_DLAB: u8 = 1 << 7;
+const LCR_8N1: u8 = 0x03;
+const LSR_THRE: u8 = 1 << 5;
+
+unsafe fn uart_write_reg(off: usize, v: u8) {
+    (off as *mut u8).write_volatile(v);
+}
+
+unsafe fn uart_read_reg(off: usize) -> u8 {
+    (off as *const u8).read_volatile()
+}
+
+fn uart_init() {
+    unsafe {
+        uart_write_reg(UART_LCR, LCR_DLAB);
+        uart_write_reg(UART_THR, 0x01);
+        uart_write_reg(UART_IER, 0x00);
+        uart_write_reg(UART_LCR, LCR_8N1);
+        uart_write_reg(UART_FCR, 0x07);
+    }
+}
+
+fn uart_write_byte(b: u8) {
+    unsafe {
+        while (uart_read_reg(UART_LSR) & LSR_THRE) == 0 {}
+        uart_write_reg(UART_THR, b);
+    }
+}
+
+fn uart_write_str(s: &str) {
+    for &b in s.as_bytes() {
+        uart_write_byte(b);
+    }
+}
+
+#[entry]
+fn main() -> ! {
+    uart_init();
+    uart_write_str("Hello from UART!\n");
+    debug::exit(EXIT_SUCCESS);
+    loop {}
+}

typos.toml

@@ -1,3 +1,3 @@
 [default]
 extend-ignore-re = ["[Ss][Ii][Ee]", "[Ss][Xx][Ll]", "[.]?useed[.,:]?", "[Ss][Tt][Ii][Pp]"]
-extend-ignore-words-re = ["[Pp]endings", "PENDINGS"]
+extend-ignore-words-re = ["[Pp]endings", "PENDINGS", "THR", "THRE"]