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Merge pull request #88 from the-snowwhite/DE10_Nano_FB_Cramps
De10 nano fb cramps
2 parents de7edf0 + 6405271 commit fc8bee0

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‎HW/QuartusProjects/DE10_Nano_Commands.md‎

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DE10_Nano_Commands:
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u-boot: (replace xx:xx:xx:xx:xx:xx with a REAL mac address)
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setenv ethaddr xx:xx:xx:xx:xx:xx
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setenv hostname mksocfpga-nano-soc
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saveenv
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reset
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sudo apt update
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Machinekit:
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sudo apt-get install $(apt-cache depends machinekit | grep Depends | sed "s/.*ends:\ //" | tr '\n' ' ')
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sudo apt purge machinekit
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(sudo dpkg -i machinekit-rt-preempt_0.1.1-1_armhf.deb machinekit_0.1.1-1_armhf.deb)
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(sudo apt-get autoremove)
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sudo apt install machinekit-rt-preempt
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Configs:
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sudo apt install socfpga-rbf
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sudo apt install git ca-certificates
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git clone https://github.com/the-snowwhite/Hm2-soc_FDM.git
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for De10_Nano:
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cd Hm2-soc_FDM
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git checkout DE10_Nano_FB_Cramps
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cd ~/
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git clone https://github.com/the-snowwhite/Machineface.git
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cd Machineface
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git checkout work-updated
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cd ~/
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git clone https://github.com/the-snowwhite/Cetus.git
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cd Cetus
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git checkout probework2
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cd ~/
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SPI for tmc2130 stepper drivers:
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git clone --recursive https://github.com/the-snowwhite/SPI.git
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sudo apt install python-dev
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cd SPI/py-spidev
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sudo python setup.py install
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cd ~/
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if /usr/include/features.h:374:25: fatal error: sys/cdefs.h: No such file or directory
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-->sudo apt install --reinstall libc6-dev
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sudo python setup.py install
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cd ~/
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gksu leafpad /etc/linuxcnc/machinekit.ini
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--> REMOTE=1
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cat <<EOT > start.sh
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#!/bin/bash
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## Enable debug
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sudo sh -c 'echo 1 > /proc/sys/fs/suid_dumpable'
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export DEBUG=5
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/home/machinekit/SPI/set_tmc2130.sh 8
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/usr/bin/mklauncher /home/machinekit/Hm2-soc_FDM
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EOT
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chmod +x start.sh
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./start.sh
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then run machinekit client :-)

‎HW/QuartusProjects/DE10_Nano_FB_Cramps/.gitignore‎

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*.qip

‎HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.ipx‎

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<?xml version="1.0" encoding="UTF-8"?>
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<library>
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<path path="../../cv-ip/**/*" />
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</library>

‎HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.out.sdc‎

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## Generated SDC file "DE10_Nano_FB_Cramps.out.sdc"
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## Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, the Altera Quartus Prime License Agreement,
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## the Altera MegaCore Function License Agreement, or other
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## applicable license agreement, including, without limitation,
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## that your use is for the sole purpose of programming logic
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## devices manufactured by Altera and sold by Altera or its
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## authorized distributors. Please refer to the applicable
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## agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus Prime"
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## VERSION "Version 15.1.2 Build 193 02/01/2016 SJ Standard Edition"
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## DATE "Tue Aug 29 13:25:32 2017"
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##
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## DEVICE "5CSEBA6U23I7"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {fpga_clk1_50} -period "50.0 MHz" [get_ports {FPGA_CLK1_50}]
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create_clock -name {fpga_clk2_50} -period "50.0 MHz" [get_ports {FPGA_CLK2_50}]
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create_clock -name {fpga_clk3_50} -period "50.0 MHz" [get_ports {FPGA_CLK3_50}]
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# for enhancing USB BlasterII to be reliable, 25MHz
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create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
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set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
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set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
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set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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create_generated_clock -name {soc_system:u0|soc_system_pll_stream:pll_stream|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL_O_VCOPH0} -source [get_pins {u0|pll_stream|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50.000 -multiply_by 12 -divide_by 2 -master_clock {fpga_clk1_50} [get_pins {u0|pll_stream|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
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create_generated_clock -name {soc_system:u0|soc_system_pll_stream:pll_stream|altera_pll:altera_pll_i|outclk_wire[0]} -source [get_pins {u0|pll_stream|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 2 -master_clock {soc_system:u0|soc_system_pll_stream:pll_stream|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL_O_VCOPH0} [get_pins {u0|pll_stream|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
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create_generated_clock -name {soc_system:u0|soc_system_pll_stream:pll_stream|altera_pll:altera_pll_i|outclk_wire[1]} -source [get_pins {u0|pll_stream|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 4 -master_clock {soc_system:u0|soc_system_pll_stream:pll_stream|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL_O_VCOPH0} [get_pins {u0|pll_stream|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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set_clock_uncertainty -rise_from [get_clocks {fpga_clk1_50}] -rise_to [get_clocks {fpga_clk1_50}] -setup 0.310
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set_clock_uncertainty -rise_from [get_clocks {fpga_clk1_50}] -rise_to [get_clocks {fpga_clk1_50}] -hold 0.270
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set_clock_uncertainty -rise_from [get_clocks {fpga_clk1_50}] -fall_to [get_clocks {fpga_clk1_50}] -setup 0.310
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set_clock_uncertainty -rise_from [get_clocks {fpga_clk1_50}] -fall_to [get_clocks {fpga_clk1_50}] -hold 0.270
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set_clock_uncertainty -fall_from [get_clocks {fpga_clk1_50}] -rise_to [get_clocks {fpga_clk1_50}] -setup 0.310
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set_clock_uncertainty -fall_from [get_clocks {fpga_clk1_50}] -rise_to [get_clocks {fpga_clk1_50}] -hold 0.270
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set_clock_uncertainty -fall_from [get_clocks {fpga_clk1_50}] -fall_to [get_clocks {fpga_clk1_50}] -setup 0.310
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set_clock_uncertainty -fall_from [get_clocks {fpga_clk1_50}] -fall_to [get_clocks {fpga_clk1_50}] -hold 0.270
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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‎HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.qpf‎

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DATE = "17:14:54 March 04, 2015"
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QUARTUS_VERSION = "14.1"
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# Revisions
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PROJECT_REVISION = "DE10_Nano_FB_Cramps"

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