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the-snowwhitethe-snowwhite
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quick-fix for freeing gpio1 pins and removing capsense core from CRAMPS 3x24 config
and cleanup Signed-off-by: Michael Brown <producer@holotronic.dk>
1 parent 089a8e3 commit 7754d9c

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11 files changed

+166
-88
lines changed

11 files changed

+166
-88
lines changed

‎HW/QuartusProjects/Common/gpio_adr_decoder_reg.sv‎

Lines changed: 92 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,7 @@ parameter MuxGPIOIOWidth = 36;
7777
parameter NumIOAddrReg = 6;
7878
parameter NumGPIO = 2;
7979

80+
parameter Capsense = 1;
8081
parameter NumSense = 4;
8182
parameter ADC = "";
8283
// local param
@@ -255,7 +256,7 @@ adc_ltc2308_fifo adc_ltc2308_fifo_inst
255256
assign mux_reg_index = busaddress_r - 16'h1120;
256257
assign mux_reg_addr = (mux_reg_index[6:2]);
257258
assign mux_reg_byte = (mux_reg_index[1:0]);
258-
259+
generate if (Capsense >= 1) begin
259260
// Writes:
260261
always @( posedge reset_in or posedge write_address) begin
261262
if (reset_in) begin
@@ -265,7 +266,9 @@ adc_ltc2308_fifo adc_ltc2308_fifo_inst
265266
if (busaddress_r == 10'h0304) begin hysteresis_reg <= busdata_in_r; end
266267
end
267268
end
268-
269+
end
270+
endgenerate
271+
269272
genvar il;
270273
generate
271274
for(il=0;il<NumIOAddrReg;il=il+1) begin : reg_initloop
@@ -323,7 +326,7 @@ adc_ltc2308_fifo adc_ltc2308_fifo_inst
323326
// wire [GPIOWidth-1:0] gpio1_out_data = {gpio1_data_fromhm3[GPIOWidth-1:5],4'bz,charge};
324327
// wire [GPIOWidth-1:0] gpio1_input_data;
325328
// assign gpio_input_data[1] = {gpio1_input_data[GPIOWidth-1:5],sense,charge};
326-
329+
generate if (Capsense >=1) begin
327330
bidir_io #(.IOWidth(GPIOWidth * NumGPIO),.PortNumWidth(PortNumWidth)) bidir_io_inst
328331
(
329332
.clk(reg_clk),
@@ -334,8 +337,20 @@ adc_ltc2308_fifo adc_ltc2308_fifo_inst
334337
.gpioport({gpioport[1],gpioport[0]}) , // inout [IOIOWidth-1:0] gpioport_sig
335338
.data_from_gpio({gpio_input_data[1],gpio_input_data[0]}) // output [IOIOWidth-1:0] read_data_sig
336339
);
337-
338-
340+
end
341+
else begin
342+
bidir_io #(.IOWidth(GPIOWidth * NumGPIO),.PortNumWidth(PortNumWidth)) bidir_io_inst
343+
(
344+
.clk(reg_clk),
345+
.portselnum(portnumsel),
346+
.out_ena({out_ena[1],out_ena[0]}) , // input out_ena_sig
347+
.od({od[1],od[0]}) , // input od_sig
348+
.out_data({iodatafromhm3[1], iodatafromhm3[0]}) , // input [IOIOWidth-1:0] out_data_sig
349+
.gpioport({gpioport[1],gpioport[0]}) , // inout [IOIOWidth-1:0] gpioport_sig
350+
.data_from_gpio({gpio_input_data[1],gpio_input_data[0]}) // output [IOIOWidth-1:0] read_data_sig
351+
);
352+
end
353+
endgenerate
339354
// Read:
340355

341356
integer oo,om,oi;
@@ -346,57 +361,85 @@ adc_ltc2308_fifo adc_ltc2308_fifo_inst
346361
busdata_to_cpu <= 32'b0;
347362
end
348363
else if (read_address) begin
349-
if (adc_address_valid) begin busdata_to_cpu <= adc_data_out; end
350-
// if ((busaddress_r == 'h0200) || (busaddress_r == 'h0204)) begin busdata_to_cpu <= adc_data_out; end
351-
else if (busaddress_r == 'h0300) begin busdata_to_cpu <= touched; end
352-
else if (busaddress_r == 'h0304) begin busdata_to_cpu <= hysteresis_reg; end
353-
else if(busaddress_r == 'h1000) begin busdata_to_cpu <= {8'b0,gpio_input_data[0][23:0]}; end
354-
else if(busaddress_r == 'h1004) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][11:0],gpio_input_data[0][35:24]}; end
355-
else if(busaddress_r == 'h1008) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][35:12]}; end
356-
// else if(busaddress_r == 'h100c) begin busdata_to_cpu <= {8'b0,gpio_input_data[2][23:0]}; end
357-
// else if(busaddress_r == 'h1010) begin busdata_to_cpu <= {8'b0,gpio_input_data[3][11:0],gpio_input_data[2][35:24]}; end
358-
// else if(busaddress_r == 'h1014) begin busdata_to_cpu <= {8'b0,gpio_input_data[3][35:12]}; end
359-
// else if ((busaddress_r >= 16'h1100) && (busaddress_r < 16'h1200)) begin
360-
else if (ddr_address_valid || od_address_valid) begin
361-
for(oo=0;oo<NumIOAddrReg;oo=oo+1) begin : reggen_loop
362-
if (busaddress_r == ('h1100 + (oo*4))) begin busdata_to_cpu <= ddr_reg[oo]; end
363-
else if (busaddress_r == ('h1300 + (oo*4))) begin busdata_to_cpu <= od_reg[oo]; end
364+
if (Capsense >= 1) begin
365+
if (adc_address_valid) begin busdata_to_cpu <= adc_data_out; end
366+
else if (busaddress_r == 'h0300) begin busdata_to_cpu <= touched; end
367+
else if (busaddress_r == 'h0304) begin busdata_to_cpu <= hysteresis_reg; end
368+
else if(busaddress_r == 'h1000) begin busdata_to_cpu <= {8'b0,gpio_input_data[0][23:0]}; end
369+
else if(busaddress_r == 'h1004) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][11:0],gpio_input_data[0][35:24]}; end
370+
else if(busaddress_r == 'h1008) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][35:12]}; end
371+
// else if(busaddress_r == 'h100c) begin busdata_to_cpu <= {8'b0,gpio_input_data[2][23:0]}; end
372+
// else if(busaddress_r == 'h1010) begin busdata_to_cpu <= {8'b0,gpio_input_data[3][11:0],gpio_input_data[2][35:24]}; end
373+
// else if(busaddress_r == 'h1014) begin busdata_to_cpu <= {8'b0,gpio_input_data[3][35:12]}; end
374+
// else if ((busaddress_r >= 16'h1100) && (busaddress_r < 16'h1200)) begin
375+
else if (ddr_address_valid || od_address_valid) begin
376+
for(oo=0;oo<NumIOAddrReg;oo=oo+1) begin : reggen_loop
377+
if (busaddress_r == ('h1100 + (oo*4))) begin busdata_to_cpu <= ddr_reg[oo]; end
378+
else if (busaddress_r == ('h1300 + (oo*4))) begin busdata_to_cpu <= od_reg[oo]; end
379+
end
364380
end
365-
end
366-
else if (mux_address_valid) begin
367-
for(om=0;om<NumIOAddrReg;om=om+1) begin : mux_reggen_loop
368-
for(oi=0;oi<Mux_regPrIOReg;oi=oi+1) begin : mux_reggen_loop
369-
if (busaddress_r == ('h1120 + (om*24) + (oi*4))) begin busdata_to_cpu <= mux_reg[om][oi]; end
381+
else if (mux_address_valid) begin
382+
for(om=0;om<NumIOAddrReg;om=om+1) begin : mux_reggen_loop
383+
for(oi=0;oi<Mux_regPrIOReg;oi=oi+1) begin : mux_reggen_loop
384+
if (busaddress_r == ('h1120 + (om*24) + (oi*4))) begin busdata_to_cpu <= mux_reg[om][oi]; end
385+
end
386+
end
387+
end
388+
else begin busdata_to_cpu <= busdata_fromhm2; end
389+
end else begin
390+
if (adc_address_valid) begin busdata_to_cpu <= adc_data_out; end
391+
// if ((busaddress_r == 'h0200) || (busaddress_r == 'h0204)) begin busdata_to_cpu <= adc_data_out; end
392+
else if (busaddress_r == 'h0304) begin busdata_to_cpu <= hysteresis_reg; end
393+
else if(busaddress_r == 'h1000) begin busdata_to_cpu <= {8'b0,gpio_input_data[0][23:0]}; end
394+
else if(busaddress_r == 'h1004) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][11:0],gpio_input_data[0][35:24]}; end
395+
else if(busaddress_r == 'h1008) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][35:12]}; end
396+
// else if(busaddress_r == 'h100c) begin busdata_to_cpu <= {8'b0,gpio_input_data[2][23:0]}; end
397+
// else if(busaddress_r == 'h1010) begin busdata_to_cpu <= {8'b0,gpio_input_data[3][11:0],gpio_input_data[2][35:24]}; end
398+
// else if(busaddress_r == 'h1014) begin busdata_to_cpu <= {8'b0,gpio_input_data[3][35:12]}; end
399+
// else if ((busaddress_r >= 16'h1100) && (busaddress_r < 16'h1200)) begin
400+
else if (ddr_address_valid || od_address_valid) begin
401+
for(oo=0;oo<NumIOAddrReg;oo=oo+1) begin : reggen_loop
402+
if (busaddress_r == ('h1100 + (oo*4))) begin busdata_to_cpu <= ddr_reg[oo]; end
403+
else if (busaddress_r == ('h1300 + (oo*4))) begin busdata_to_cpu <= od_reg[oo]; end
404+
end
405+
end
406+
else if (mux_address_valid) begin
407+
for(om=0;om<NumIOAddrReg;om=om+1) begin : mux_reggen_loop
408+
for(oi=0;oi<Mux_regPrIOReg;oi=oi+1) begin : mux_reggen_loop
409+
if (busaddress_r == ('h1120 + (om*24) + (oi*4))) begin busdata_to_cpu <= mux_reg[om][oi]; end
410+
end
370411
end
371412
end
413+
else begin busdata_to_cpu <= busdata_fromhm2; end
372414
end
373-
else begin busdata_to_cpu <= busdata_fromhm2; end
374415
end
375416
end
376417
endgenerate
377-
378-
assign sense = gpio_input_data[1][5:1];
379-
380-
capsense capsense_inst
381-
(
382-
.clk(reg_clk) , // input clk_sig
383-
.reset(sense_reset) , // input reset_sig
384-
.sense(sense) , // input [num-1:0] sense_sig
385-
.hysteresis(hysteresis),
386-
.calibval_0(calibval_0),
387-
.counts_0(counts_0),
388-
.charge(charge) , // output charge_sig
389-
.touched(touched) // output [num-1:0] touched_sig
390-
);
391-
392-
defparam capsense_inst.num = NumSense;
393-
// States
394-
defparam capsense_inst.CHARGE = 1;
395-
defparam capsense_inst.DISCHARGE = 2;
396-
// freqwuency in Mhz , times in us
397-
defparam capsense_inst.clockfrequency = 200;
398-
defparam capsense_inst.periodtime = 5;
399-
418+
419+
generate if (Capsense >=1) begin
420+
assign sense = gpio_input_data[1][5:1];
421+
422+
capsense capsense_inst
423+
(
424+
.clk(reg_clk) , // input clk_sig
425+
.reset(sense_reset) , // input reset_sig
426+
.sense(sense) , // input [num-1:0] sense_sig
427+
.hysteresis(hysteresis),
428+
.calibval_0(calibval_0),
429+
.counts_0(counts_0),
430+
.charge(charge) , // output charge_sig
431+
.touched(touched) // output [num-1:0] touched_sig
432+
);
433+
434+
defparam capsense_inst.num = NumSense;
435+
// States
436+
defparam capsense_inst.CHARGE = 1;
437+
defparam capsense_inst.DISCHARGE = 2;
438+
// freqwuency in Mhz , times in us
439+
defparam capsense_inst.clockfrequency = 200;
440+
defparam capsense_inst.periodtime = 5;
441+
end
442+
endgenerate
400443

401444
endmodule
402445

‎HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.qsf‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -649,7 +649,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
649649
set_global_assignment -name SDC_FILE DE0_Nano_SoC_Cramps.sdc
650650
set_global_assignment -name VHDL_FILE ../Common/firmware_id.vhd
651651
set_global_assignment -name MIF_FILE firmware_id.mif
652-
set_global_assignment -name QIP_FILE ../../hm2/config/DE0_Nano_SoC_Cramps/hm3_DE0_Nano_SoC.qip
652+
set_global_assignment -name QIP_FILE hm3_DE0_Nano_SoC.qip
653653
set_global_assignment -name QIP_FILE ../../hm2/hm3_socfpga.qip
654654
set_global_assignment -name QIP_FILE hm3_pin_config.qip
655655
set_global_assignment -name SYSTEMVERILOG_FILE ../Common/capsense.sv

‎HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.sdc‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@
77
# Clock constraints
88

99
create_clock -name "fpga_clk1_50" -period 20.000ns [get_ports {FPGA_CLK1_50}]
10-
create_clock -name "fpga_clk1_50" -period 20.000ns [get_ports {FPGA_CLK2_50}]
1110

1211

1312
# Automatically constrain PLL and other generated clocks

‎HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.sv‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -357,6 +357,7 @@ defparam gpio_adr_decoder_reg_inst.MuxGPIOIOWidth = MuxGPIOIOWidth;
357357
defparam gpio_adr_decoder_reg_inst.NumIOAddrReg = NumIOAddrReg;
358358
//defparam gpio_adr_decoder_reg_inst.MuxLedWidth = MuxLedWidth;
359359
defparam gpio_adr_decoder_reg_inst.NumGPIO = NumGPIO;
360+
defparam gpio_adr_decoder_reg_inst.Capsense = Capsense;
360361
defparam gpio_adr_decoder_reg_inst.NumSense = 4;
361362

362363
//

‎HW/QuartusProjects/DE0_Nano_SoC_Cramps/build.sh‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,8 @@ build_config() {
4242
# Use sed because the C pre-processor only allows identifiers to be #define'd
4343
# which means in rare instances it could match actual VHDL code. Here we use
4444
# the % character to support a batch-style variable scheme
45-
sed "s/%CONFIG%/${1}/g" <hm3_pin_config.in > hm3_pin_config.qip
45+
sed "s/%CONFIG%/${1}/g" <${CONFIG_DIR}/hm3_pin_config.in > hm3_pin_config.qip
46+
sed "s/%CONFIG%/${1}/g" <${CONFIG_DIR}/hm3_DE0_Nano_SoC.in > hm3_DE0_Nano_SoC.qip
4647

4748
# Actually build the FPGA bit file
4849
make rbf

HW/hm2/config/DE0_Nano_SoC_Cramps/atlas_3_24.sv renamed to HW/hm2/config/DE0_Nano_SoC_Cramps/atlas_3x24.sv

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,4 +30,5 @@ parameter BoardAdaptor = 0;
3030
parameter MuxGPIOIOWidth = IOWidth/NumGPIO;
3131
parameter MuxLedWidth = LEDCount/NumGPIO;
3232
parameter ADC = "DE0-Nano-SoC";
33+
parameter Capsense = 0;
3334
endpackage //_HeaderIncluded

‎HW/hm2/config/DE0_Nano_SoC_Cramps/atlas_3x24_cap.sv‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
package boardtype;
2+
// DE0-Nano Dev kit and I/O adaptors specific info
3+
// {STRAIGHT=0,DB25=1} BoardAdaptor;
4+
5+
parameter BoardAdaptor = 0;
6+
parameter ClockHigh = 200000000; // 200 MHz
7+
parameter ClockMed = 100000000; // 100 MHz
8+
parameter ClockLow = 50000000; // 50 MHz
9+
// parameter BoardNameLow = 32'h41524554; // "TERA"
10+
// parameter BoardNameHigh = 32'h4E304544; // "DE0N"
11+
parameter BoardNameLow = 32'h4153454D; // "MESA"
12+
parameter BoardNameHigh = 32'h35324935; // "5I25"
13+
parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25)
14+
// FIXME: Figure out Mesanet encoding and put something sensible here
15+
parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd
16+
// Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os
17+
// Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd
18+
parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header)
19+
parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth
20+
parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25
21+
parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards)
22+
parameter LEDCount = 0; // Number of LEDs
23+
parameter SepClocks = "true"; // Deprecated
24+
parameter OneWS = "true"; // Deprecated
25+
parameter BusWidth = 32;
26+
parameter AddrWidth = 16;
27+
28+
parameter GPIOWidth = 36;
29+
parameter NumGPIO = 2;
30+
parameter MuxGPIOIOWidth = IOWidth/NumGPIO;
31+
parameter MuxLedWidth = LEDCount/NumGPIO;
32+
parameter ADC = "DE0-Nano-SoC";
33+
parameter Capsense = 1;
34+
endpackage //_HeaderIncluded

‎HW/hm2/config/DE0_Nano_SoC_Cramps/atlas_3x24_cap_spi.sv‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
package boardtype;
2+
// DE0-Nano Dev kit and I/O adaptors specific info
3+
// {STRAIGHT=0,DB25=1} BoardAdaptor;
4+
5+
parameter BoardAdaptor = 0;
6+
parameter ClockHigh = 200000000; // 200 MHz
7+
parameter ClockMed = 100000000; // 100 MHz
8+
parameter ClockLow = 50000000; // 50 MHz
9+
// parameter BoardNameLow = 32'h41524554; // "TERA"
10+
// parameter BoardNameHigh = 32'h4E304544; // "DE0N"
11+
parameter BoardNameLow = 32'h4153454D; // "MESA"
12+
parameter BoardNameHigh = 32'h35324935; // "5I25"
13+
parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25)
14+
// FIXME: Figure out Mesanet encoding and put something sensible here
15+
parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd
16+
// Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os
17+
// Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd
18+
parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header)
19+
parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth
20+
parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25
21+
parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards)
22+
parameter LEDCount = 0; // Number of LEDs
23+
parameter SepClocks = "true"; // Deprecated
24+
parameter OneWS = "true"; // Deprecated
25+
parameter BusWidth = 32;
26+
parameter AddrWidth = 16;
27+
28+
parameter GPIOWidth = 36;
29+
parameter NumGPIO = 2;
30+
parameter MuxGPIOIOWidth = IOWidth/NumGPIO;
31+
parameter MuxLedWidth = LEDCount/NumGPIO;
32+
parameter ADC = "DE0-Nano-SoC";
33+
parameter Capsense = 1;
34+
endpackage //_HeaderIncluded

‎HW/hm2/config/DE0_Nano_SoC_Cramps/de1soc_3_24.sv‎

Lines changed: 0 additions & 35 deletions
This file was deleted.

HW/hm2/config/DE0_Nano_SoC_Cramps/hm3_DE0_Nano_SoC.qip renamed to HW/hm2/config/DE0_Nano_SoC_Cramps/hm3_DE0_Nano_SoC.in

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
11
set_global_assignment -name VHDL_FILE ../../hm2/config/DE0_Nano_SoC_Cramps/hostmot3_cfg.vhd
2-
set_global_assignment -name SYSTEMVERILOG_FILE ../../hm2/config/DE0_Nano_SoC_Cramps/atlas_3_24.sv
2+
set_global_assignment -name SYSTEMVERILOG_FILE ../../hm2/config/DE0_Nano_SoC_Cramps/atlas_%CONFIG%.sv

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