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Add: new Updated zynq_bp.tcl.in as zynqmp_bp.tcl.in file.
With generation of .hdf hw definition file including bitstream Signed-off-by: Holotronic <producer@holotronic.dk>
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‎HW/VivadoProjects/avnet/ultra96/ultra96v1_config‎

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#!/bin/sh
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# TCL Template Filename
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TCL_TEMP_FILE=../../zynq_bp.tcl.in
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TCL_TEMP_FILE=../../zynqmp_bp.tcl.in
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# The fpga device we are building for
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FPGA_DEVICE=xczu3eg-sbva484-1-e

‎HW/VivadoProjects/avnet/ultra96/ultra96v2_config‎

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#!/bin/sh
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# TCL Template Filename
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TCL_TEMP_FILE=../../zynq_bp.tcl.in
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TCL_TEMP_FILE=../../zynqmp_bp.tcl.in
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# The fpga device we are building for
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FPGA_DEVICE=xczu3eg-sbva484-1-e

‎HW/VivadoProjects/make_bitfile.sh‎

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/tools/Xilinx/Vivado/2019.1/bin/vivado -mode batch -source "$PRJ_FILE"
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# bootgen: skip ultre96 projects
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if test "${1#*"ultra96"}" = "$1"; then
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if test "${1#*"ultra96"}" = "$1" && test "${1#*"fz3"}" = "$1"; then
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# Update the bif file for bootgen
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# component file1 needs the pin file path

‎HW/VivadoProjects/zynqmp_bp.tcl.in‎

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#
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# Vivado (TM) v2019.1 (64-bit)
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#
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# Tcl script template for re-creating zynq projects
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#
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# Generated by Vivado on Wed Apr 20 01:20:00 UTC 2016
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# IP Build 1412160 on Tue Nov 17 13:47:24 MST 2019
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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# when this script was generated. In order to re-create the project, please source this
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# file in the Vivado Tcl Shell.
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#
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# * Note that the runs in the created project will be configured the same way as the
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# original project, however they will not be launched automatically. To regenerate the
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# run results please launch the synthesis/implementation runs as needed.
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#
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# Set the reference directory for source file relative paths (by default the value is script directory path)
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set origin_dir [file dirname [info script]]
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set origin_dir "${origin_dir}/../"
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# Use origin directory path location variable, if specified in the tcl shell
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if { [info exists ::origin_dir_loc] } {
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set origin_dir $::origin_dir_loc
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}
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# Setup some helpful variables passed in by the make script
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set prj_name %PRJ_NAME%
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set pin_const_file $origin_dir/%PIN_HW_XDC_FILE%
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set fpgadev_name %FPGA_DEVICE%
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set board_part "%BOARD_PART%"
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set bitfile_name %BIT_FILE%
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set top_lvl_bd_script_file %TOP_LEVEL_BD_FILE%
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set prj_created_dir "$origin_dir/${prj_name}_created"
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set script_file "${prj_name}.tcl"
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# Help information for this script
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proc help {} {
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variable script_file
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puts "\nDescription:"
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puts "Recreate a Vivado project from this script. The created project will be"
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puts "functionally equivalent to the original project for which this script was"
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puts "generated. The script contains commands for creating a project, filesets,"
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puts "runs, adding/importing sources and setting properties on various objects.\n"
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puts "Syntax:"
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puts "$script_file"
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puts "$script_file -tclargs \[--origin_dir <path>\]"
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puts "$script_file -tclargs \[--help\]\n"
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puts "Usage:"
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puts "Name Description"
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puts "-------------------------------------------------------------------------"
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puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
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puts " origin_dir path value is \".\", otherwise, the value"
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puts " that was set with the \"-paths_relative_to\" switch"
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puts " when this script was generated.\n"
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puts "\[--help\] Print help information for this script"
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puts "-------------------------------------------------------------------------\n"
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exit 0
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}
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if { $::argc > 0 } {
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for {set i 0} {$i < [llength $::argc]} {incr i} {
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set option [string trim [lindex $::argv $i]]
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switch -regexp -- $option {
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"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
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"--help" { help }
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default {
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if { [regexp {^-} $option] } {
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puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
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return 1
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}
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}
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}
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}
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}
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# Set the directory path for the original project from where this script was exported
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set orig_proj_dir "[file normalize $prj_created_dir]"
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# Create project
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create_project "$prj_name" $prj_created_dir
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# Set the directory path for the new project
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set proj_dir [get_property directory [current_project]]
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# Set project properties
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set obj [get_projects $prj_name]
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if {$board_part ne ""} {
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set_property "part" "$fpgadev_name" $obj
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set_property "board_part" $board_part $obj
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} else {
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set_property "part" "$fpgadev_name" $obj
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}
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set_property "default_lib" "xil_defaultlib" $obj
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set_property "sim.ip.auto_export_scripts" "1" $obj
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set_property "simulator_language" "Mixed" $obj
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set_property "target_language" "VHDL" $obj
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# Create 'sources_1' fileset (if not found)
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if {[string equal [get_filesets -quiet sources_1] ""]} {
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create_fileset -srcset sources_1
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}
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# Set IP repository paths
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set obj [get_filesets sources_1]
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set prj_ip_path "[file normalize "$origin_dir/../../../zynq-ip"]"
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# Include a project local IP repository if it exists
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if {[file isdirectory "$origin_dir/ip"]} {
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set prj_ip_path "$prj_ip_path $origin_dir/ip"
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}
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set_property "ip_repo_paths" "$prj_ip_path" $obj
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# Rebuild user ip_repo's index before adding any source files
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update_ip_catalog -rebuild
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# Build the bd
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source $origin_dir/$top_lvl_bd_script_file
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# Create the hdl wrapper file
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make_wrapper -files [get_files $proj_dir/${prj_name}.srcs/sources_1/bd/soc_system/soc_system.bd] -top
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add_files -norecurse $orig_proj_dir/${prj_name}.srcs/sources_1/bd/soc_system/hdl/soc_system_wrapper.vhd
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# Set 'sources_1' fileset object
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set obj [get_filesets sources_1]
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set files [list \
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[file normalize "$prj_created_dir/${prj_name}.srcs/sources_1/bd/soc_system/hdl/soc_system_wrapper.vhd" ]\
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[file normalize "$prj_created_dir/firmware_id.mif" ]\
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]
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#add_files -norecurse -fileset $obj $files
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set imported_files [import_files -fileset sources_1 $files]
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set file "hdl/soc_system_wrapper.vhd"
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "file_type" -value "VHDL" -objects $file_obj
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#set file "${prj_name}_created/firmware_id.mif"
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set file "firmware_id.mif"
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "file_type" -value "Memory Initialization Files" -objects $file_obj
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# Set 'sources_1' fileset properties
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set obj [get_filesets sources_1]
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set_property "top" "soc_system_wrapper" $obj
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# Create 'constrs_1' fileset (if not found)
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if {[string equal [get_filesets -quiet constrs_1] ""]} {
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create_fileset -constrset constrs_1
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}
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# Set 'constrs_1' fileset object
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set obj [get_filesets constrs_1]
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# Add/Import constrs file and set constrs file properties
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set file "[file normalize "$pin_const_file"]"
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set file_added [add_files -norecurse -fileset $obj $file]
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set file "$pin_const_file"
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set file [file normalize $file]
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set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
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set_property "file_type" "XDC" $file_obj
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# Set 'constrs_1' fileset properties
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set obj [get_filesets constrs_1]
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# Create 'sim_1' fileset (if not found)
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if {[string equal [get_filesets -quiet sim_1] ""]} {
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create_fileset -simset sim_1
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}
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# Set 'sim_1' fileset object
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set obj [get_filesets sim_1]
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# Empty (no sources present)
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# Set 'sim_1' fileset properties
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set obj [get_filesets sim_1]
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set_property "top" "soc_system_wrapper" $obj
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set_property "xelab.nosort" "1" $obj
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set_property "xelab.unifast" "" $obj
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# Create 'synth_1' run (if not found)
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if {[string equal [get_runs -quiet synth_1] ""]} {
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create_run -name synth_1 -part $fpgadev_name -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
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} else {
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set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
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set_property flow "Vivado Synthesis 2019" [get_runs synth_1]
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}
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set obj [get_runs synth_1]
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set_property "needs_refresh" "1" $obj
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set_property "part" "$fpgadev_name" $obj
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# set the current synth run
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current_run -synthesis [get_runs synth_1]
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# Create 'impl_1' run (if not found)
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if {[string equal [get_runs -quiet impl_1] ""]} {
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create_run -name impl_1 -part $fpgadev_name -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
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} else {
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set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
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set_property flow "Vivado Implementation 2019" [get_runs impl_1]
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}
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set obj [get_runs impl_1]
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set_property "needs_refresh" "1" $obj
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set_property "part" "$fpgadev_name" $obj
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set_property "steps.write_bitstream.args.readback_file" "0" $obj
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set_property "steps.write_bitstream.args.verbose" "0" $obj
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# set the current impl run
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current_run -implementation [get_runs impl_1]
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puts "INFO: Project created: $prj_name"
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# reset the runs just in case
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reset_run synth_1
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reset_run impl_1
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# Launch the runs
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set_property synth_checkpoint_mode None [get_files $prj_created_dir/$prj_name.srcs/sources_1/bd/soc_system/soc_system.bd]
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generate_target all [get_files $prj_created_dir/$prj_name.srcs/sources_1/bd/soc_system/soc_system.bd]
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export_ip_user_files -of_objects [get_files $prj_created_dir/$prj_name.srcs/sources_1/bd/soc_system/soc_system.bd] -no_script -sync -force -quiet
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launch_runs impl_1 -to_step write_bitstream -jobs 16
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wait_on_run impl_1
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open_run impl_1
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# Write the bitstream
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write_bitstream "$prj_created_dir/$bitfile_name"
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# Write the hw platform
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set sdk_workspace [file join $prj_created_dir $prj_name.sdk]
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if { [file exists $sdk_workspace] == 0 } {
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file mkdir $sdk_workspace
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}
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set design_top_name [get_property "top" [current_fileset]]
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file copy -force [file join $prj_created_dir $prj_name.runs "impl_1" $design_top_name.sysdef] [file join $sdk_workspace $design_top_name.hdf]

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