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[VP] Remove VP_PROPERTY_REDUCTION and VP_PROPERTY_CMP [nfc] (#105551)
These lists are quite static and several of the parameters are actually constant across all users. Heavy use of macros is undesirable, and not idiomatic in LLVM, so let's just use the naive switch cases. I'll probably continue with removing the other property macros. These two just happened to be the two I actually had to figure out for an unrelated change.
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-69
lines changed

3 files changed

+48
-69
lines changed

‎llvm/include/llvm/IR/VPIntrinsics.def‎

Lines changed: 0 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -129,11 +129,6 @@
129129
#define VP_PROPERTY_MEMOP(POINTERPOS, DATAPOS)
130130
#endif
131131

132-
// Map this VP reduction intrinsic to its reduction operand positions.
133-
#ifndef VP_PROPERTY_REDUCTION
134-
#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS)
135-
#endif
136-
137132
// A property to infer VP binary-op SDNode opcodes automatically.
138133
#ifndef VP_PROPERTY_BINARYOP
139134
#define VP_PROPERTY_BINARYOP
@@ -144,13 +139,6 @@
144139
#define VP_PROPERTY_CASTOP
145140
#endif
146141

147-
// This VP Intrinsic is a comparison operation
148-
// The condition code arg is at CCPOS and accepts floating-point condition
149-
// codes if ISFP is set, else it accepts integer condition codes.
150-
#ifndef VP_PROPERTY_CMP
151-
#define VP_PROPERTY_CMP(CCPOS, ISFP)
152-
#endif
153-
154142
/// } Property Macros
155143

156144
///// Integer Arithmetic {
@@ -567,15 +555,13 @@ END_REGISTER_VP_SDNODE(VP_SETCC)
567555
BEGIN_REGISTER_VP_INTRINSIC(vp_fcmp, 3, 4)
568556
HELPER_MAP_VPID_TO_VPSD(vp_fcmp, VP_SETCC)
569557
VP_PROPERTY_FUNCTIONAL_OPC(FCmp)
570-
VP_PROPERTY_CMP(2, true)
571558
VP_PROPERTY_CONSTRAINEDFP(0, 1, experimental_constrained_fcmp)
572559
END_REGISTER_VP_INTRINSIC(vp_fcmp)
573560

574561
// llvm.vp.icmp(x,y,cc,mask,vlen)
575562
BEGIN_REGISTER_VP_INTRINSIC(vp_icmp, 3, 4)
576563
HELPER_MAP_VPID_TO_VPSD(vp_icmp, VP_SETCC)
577564
VP_PROPERTY_FUNCTIONAL_OPC(ICmp)
578-
VP_PROPERTY_CMP(2, false)
579565
END_REGISTER_VP_INTRINSIC(vp_icmp)
580566

581567
///// } Comparisons
@@ -655,7 +641,6 @@ END_REGISTER_VP(vp_gather, VP_GATHER)
655641
BEGIN_REGISTER_VP(VPID, 2, 3, VPSD, 1) \
656642
VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \
657643
VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
658-
VP_PROPERTY_REDUCTION(0, 1) \
659644
END_REGISTER_VP(VPID, VPSD)
660645

661646
// llvm.vp.reduce.add(start,x,mask,vlen)
@@ -725,13 +710,11 @@ HELPER_REGISTER_REDUCTION_VP(vp_reduce_fminimum, VP_REDUCE_FMINIMUM,
725710
#define HELPER_REGISTER_REDUCTION_SEQ_VP(VPID, VPSD, SEQ_VPSD, SDOPC, SEQ_SDOPC, INTRIN) \
726711
BEGIN_REGISTER_VP_INTRINSIC(VPID, 2, 3) \
727712
BEGIN_REGISTER_VP_SDNODE(VPSD, 1, VPID, 2, 3) \
728-
VP_PROPERTY_REDUCTION(0, 1) \
729713
VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
730714
END_REGISTER_VP_SDNODE(VPSD) \
731715
BEGIN_REGISTER_VP_SDNODE(SEQ_VPSD, 1, VPID, 2, 3) \
732716
HELPER_MAP_VPID_TO_VPSD(VPID, SEQ_VPSD) \
733717
VP_PROPERTY_FUNCTIONAL_SDOPC(SEQ_SDOPC) \
734-
VP_PROPERTY_REDUCTION(0, 1) \
735718
END_REGISTER_VP_SDNODE(SEQ_VPSD) \
736719
VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \
737720
END_REGISTER_VP_INTRINSIC(VPID)
@@ -796,11 +779,9 @@ END_REGISTER_VP(experimental_vp_splat, EXPERIMENTAL_VP_SPLAT)
796779
#undef HELPER_MAP_VPID_TO_VPSD
797780
#undef VP_PROPERTY_BINARYOP
798781
#undef VP_PROPERTY_CASTOP
799-
#undef VP_PROPERTY_CMP
800782
#undef VP_PROPERTY_CONSTRAINEDFP
801783
#undef VP_PROPERTY_FUNCTIONAL_INTRINSIC
802784
#undef VP_PROPERTY_FUNCTIONAL_OPC
803785
#undef VP_PROPERTY_FUNCTIONAL_SDOPC
804786
#undef VP_PROPERTY_NO_FUNCTIONAL
805787
#undef VP_PROPERTY_MEMOP
806-
#undef VP_PROPERTY_REDUCTION

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp‎

Lines changed: 19 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -503,13 +503,26 @@ bool ISD::isVPBinaryOp(unsigned Opcode) {
503503
bool ISD::isVPReduction(unsigned Opcode) {
504504
switch (Opcode) {
505505
default:
506-
break;
507-
#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
508-
#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true;
509-
#define END_REGISTER_VP_SDNODE(VPSD) break;
510-
#include "llvm/IR/VPIntrinsics.def"
506+
return false;
507+
case ISD::VP_REDUCE_ADD:
508+
case ISD::VP_REDUCE_MUL:
509+
case ISD::VP_REDUCE_AND:
510+
case ISD::VP_REDUCE_OR:
511+
case ISD::VP_REDUCE_XOR:
512+
case ISD::VP_REDUCE_SMAX:
513+
case ISD::VP_REDUCE_SMIN:
514+
case ISD::VP_REDUCE_UMAX:
515+
case ISD::VP_REDUCE_UMIN:
516+
case ISD::VP_REDUCE_FMAX:
517+
case ISD::VP_REDUCE_FMIN:
518+
case ISD::VP_REDUCE_FMAXIMUM:
519+
case ISD::VP_REDUCE_FMINIMUM:
520+
case ISD::VP_REDUCE_FADD:
521+
case ISD::VP_REDUCE_FMUL:
522+
case ISD::VP_REDUCE_SEQ_FADD:
523+
case ISD::VP_REDUCE_SEQ_FMUL:
524+
return true;
511525
}
512-
return false;
513526
}
514527

515528
/// The operand position of the vector mask.

‎llvm/lib/IR/IntrinsicInst.cpp‎

Lines changed: 29 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -738,14 +738,25 @@ Function *VPIntrinsic::getDeclarationForParams(Module *M, Intrinsic::ID VPID,
738738

739739
bool VPReductionIntrinsic::isVPReduction(Intrinsic::ID ID) {
740740
switch (ID) {
741+
case Intrinsic::vp_reduce_add:
742+
case Intrinsic::vp_reduce_mul:
743+
case Intrinsic::vp_reduce_and:
744+
case Intrinsic::vp_reduce_or:
745+
case Intrinsic::vp_reduce_xor:
746+
case Intrinsic::vp_reduce_smax:
747+
case Intrinsic::vp_reduce_smin:
748+
case Intrinsic::vp_reduce_umax:
749+
case Intrinsic::vp_reduce_umin:
750+
case Intrinsic::vp_reduce_fmax:
751+
case Intrinsic::vp_reduce_fmin:
752+
case Intrinsic::vp_reduce_fmaximum:
753+
case Intrinsic::vp_reduce_fminimum:
754+
case Intrinsic::vp_reduce_fadd:
755+
case Intrinsic::vp_reduce_fmul:
756+
return true;
741757
default:
742-
break;
743-
#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
744-
#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true;
745-
#define END_REGISTER_VP_INTRINSIC(VPID) break;
746-
#include "llvm/IR/VPIntrinsics.def"
758+
return false;
747759
}
748-
return false;
749760
}
750761

751762
bool VPCastIntrinsic::isVPCast(Intrinsic::ID ID) {
@@ -763,13 +774,11 @@ bool VPCastIntrinsic::isVPCast(Intrinsic::ID ID) {
763774
bool VPCmpIntrinsic::isVPCmp(Intrinsic::ID ID) {
764775
switch (ID) {
765776
default:
766-
break;
767-
#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
768-
#define VP_PROPERTY_CMP(CCPOS, ...) return true;
769-
#define END_REGISTER_VP_INTRINSIC(VPID) break;
770-
#include "llvm/IR/VPIntrinsics.def"
777+
return false;
778+
case Intrinsic::vp_fcmp:
779+
case Intrinsic::vp_icmp:
780+
return true;
771781
}
772-
return false;
773782
}
774783

775784
bool VPBinOpIntrinsic::isVPBinOp(Intrinsic::ID ID) {
@@ -803,22 +812,10 @@ static ICmpInst::Predicate getIntPredicateFromMD(const Value *Op) {
803812
}
804813

805814
CmpInst::Predicate VPCmpIntrinsic::getPredicate() const {
806-
bool IsFP = true;
807-
std::optional<unsigned> CCArgIdx;
808-
switch (getIntrinsicID()) {
809-
default:
810-
break;
811-
#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
812-
#define VP_PROPERTY_CMP(CCPOS, ISFP) \
813-
CCArgIdx = CCPOS; \
814-
IsFP = ISFP; \
815-
break;
816-
#define END_REGISTER_VP_INTRINSIC(VPID) break;
817-
#include "llvm/IR/VPIntrinsics.def"
818-
}
819-
assert(CCArgIdx && "Unexpected vector-predicated comparison");
820-
return IsFP ? getFPPredicateFromMD(getArgOperand(*CCArgIdx))
821-
: getIntPredicateFromMD(getArgOperand(*CCArgIdx));
815+
assert(isVPCmp(getIntrinsicID()));
816+
return getIntrinsicID() == Intrinsic::vp_fcmp
817+
? getFPPredicateFromMD(getArgOperand(2))
818+
: getIntPredicateFromMD(getArgOperand(2));
822819
}
823820

824821
unsigned VPReductionIntrinsic::getVectorParamPos() const {
@@ -831,27 +828,15 @@ unsigned VPReductionIntrinsic::getStartParamPos() const {
831828

832829
std::optional<unsigned>
833830
VPReductionIntrinsic::getVectorParamPos(Intrinsic::ID ID) {
834-
switch (ID) {
835-
#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
836-
#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS) return VECTORPOS;
837-
#define END_REGISTER_VP_INTRINSIC(VPID) break;
838-
#include "llvm/IR/VPIntrinsics.def"
839-
default:
840-
break;
841-
}
831+
if (isVPReduction(ID))
832+
return 1;
842833
return std::nullopt;
843834
}
844835

845836
std::optional<unsigned>
846837
VPReductionIntrinsic::getStartParamPos(Intrinsic::ID ID) {
847-
switch (ID) {
848-
#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
849-
#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS) return STARTPOS;
850-
#define END_REGISTER_VP_INTRINSIC(VPID) break;
851-
#include "llvm/IR/VPIntrinsics.def"
852-
default:
853-
break;
854-
}
838+
if (isVPReduction(ID))
839+
return 0;
855840
return std::nullopt;
856841
}
857842

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