Skip to content

Commit ae58f7f

Browse files
jakubcabaljakubcabal
committed
Add TX UART side
1 parent a2843c2 commit ae58f7f

File tree

1 file changed

+125
-41
lines changed

1 file changed

+125
-41
lines changed

‎source/uart.vhd‎

Lines changed: 125 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,8 @@ entity UART is
2929
Generic (
3030
BAUD_RATE : integer := 9600; -- baud rate value, default is 9600
3131
DATA_BITS : integer := 8; -- legal values: 5,6,7,8
32-
--STOP_BITS : integer; -- TODO, now is default 1 stop bit
33-
--PARITY_BIT : integer; -- TODO, now is default none parity bit
32+
--STOP_BITS : integer; -- TODO, now must be 1 stop bit
33+
--PARITY_BIT : integer; -- TODO, now must be none parity bit
3434
CLK_FREQ : integer := 50e6 -- set system clock frequency in Hz, default is 50 MHz
3535
);
3636
Port (
@@ -44,7 +44,8 @@ entity UART is
4444
TX_VALID : out std_logic; -- when TX_VALID = 1, data on TX_DATA are valid
4545
-- USER RX INTERFACE
4646
RX_DATA : in std_logic_vector(DATA_BITS-1 downto 0);
47-
RX_VALID : in std_logic -- when RX_VALID = 1, data on RX_DATA are valid
47+
RX_VALID : in std_logic; -- when RX_VALID = 1, data on RX_DATA are valid
48+
RX_READY : out std_logic -- when RX_READY = 1, you can set RX_VALID to 1
4849
);
4950
end UART;
5051

@@ -53,17 +54,25 @@ architecture FULL of UART is
5354
-- constants
5455
constant divider_value : integer := CLK_FREQ / BAUD_RATE;
5556
-- signals
56-
signal rx_data_reg : std_logic_vector(DATA_BITS-1 downto 0);
57-
signal rx_data_reg_next : std_logic_vector(DATA_BITS-1 downto 0);
58-
signal rx_data_vld : std_logic;
59-
signal rx_data_vld_next : std_logic;
57+
signal tx_uart_reg : std_logic;
58+
signal tx_uart_reg_next : std_logic;
59+
signal tx_uart_data : std_logic_vector(DATA_BITS-1 downto 0);
60+
signal tx_uart_bit_count : integer range 0 to DATA_BITS+1;
61+
signal tx_uart_bit_count_next : integer range 0 to DATA_BITS+1;
62+
signal tx_uart_ready : std_logic;
63+
signal tx_uart_ready_next : std_logic;
64+
signal rx_uart_data : std_logic_vector(DATA_BITS-1 downto 0);
65+
signal rx_uart_data_next : std_logic_vector(DATA_BITS-1 downto 0);
66+
signal rx_uart_vld : std_logic;
67+
signal rx_uart_vld_next : std_logic;
68+
signal rx_uart_bit_count : integer range 0 to DATA_BITS-1;
69+
signal rx_uart_bit_count_next : integer range 0 to DATA_BITS-1;
6070
signal uart_clk_en : std_logic;
61-
6271
signal ticks : integer range 0 to divider_value;
63-
signal rx_data_bit_count : integer range 0 to DATA_BITS-1;
64-
signal rx_data_bit_count_next : integer range 0 to DATA_BITS-1;
6572

66-
type state is (idle, receive_data, receive_stop_bit);
73+
type state is (idle, receive_data, transmit_data, receive_stop_bit);
74+
signal tx_present_st : state;
75+
signal tx_next_st : state;
6776
signal rx_present_st : state;
6877
signal rx_next_st : state;
6978

@@ -73,7 +82,7 @@ begin
7382
-- UART CLOCK DIVIDER
7483
-- -------------------------------------------------------------------------
7584

76-
process (CLK)
85+
clk_divider : process (CLK)
7786
begin
7887
if (rising_edge(CLK)) then
7988
if (RST = '1') then
@@ -92,21 +101,32 @@ begin
92101
-- INPUT REGISTER
93102
-- -------------------------------------------------------------------------
94103

95-
-- TODO
104+
RX_READY <= tx_uart_ready;
105+
106+
input_reg : process (CLK)
107+
begin
108+
if (rising_edge(CLK)) then
109+
if (RST = '1') then
110+
tx_uart_data <= (others => '0');
111+
elsif (RX_VALID = '1' AND tx_uart_ready = '1') then
112+
tx_uart_data <= RX_DATA;
113+
end if;
114+
end if;
115+
end process;
96116

97117
-- -------------------------------------------------------------------------
98118
-- OUTPUT REGISTER
99119
-- -------------------------------------------------------------------------
100120

101-
TX_VALID <= rx_data_vld;
121+
TX_VALID <= rx_uart_vld;
102122

103-
process (CLK)
123+
output_reg : process (CLK)
104124
begin
105125
if (rising_edge(CLK)) then
106126
if (RST = '1') then
107127
TX_DATA <= (others => '0');
108-
elsif (rx_data_vld = '1') then
109-
TX_DATA <= rx_data_reg;
128+
elsif (rx_uart_vld = '1') then
129+
TX_DATA <= rx_uart_data;
110130
end if;
111131
end if;
112132
end process;
@@ -115,7 +135,71 @@ begin
115135
-- TX UART FSM
116136
-- -------------------------------------------------------------------------
117137

118-
-- TODO
138+
TX_UART <= tx_uart_reg;
139+
140+
process (CLK)
141+
begin
142+
if (rising_edge(CLK)) then
143+
if (RST = '1') then
144+
tx_present_st <= idle;
145+
tx_uart_bit_count <= 0;
146+
tx_uart_ready <= '0';
147+
tx_uart_reg <= '1';
148+
else
149+
tx_present_st <= tx_next_st;
150+
tx_uart_bit_count <= tx_uart_bit_count_next;
151+
tx_uart_ready <= tx_uart_ready_next;
152+
tx_uart_reg <= tx_uart_reg_next;
153+
end if;
154+
end if;
155+
end process;
156+
157+
process (tx_present_st, RX_VALID, tx_uart_bit_count, tx_uart_ready, tx_uart_data, tx_uart_reg, uart_clk_en)
158+
begin
159+
160+
tx_uart_bit_count_next <= tx_uart_bit_count;
161+
tx_uart_ready_next <= tx_uart_ready;
162+
tx_uart_reg_next <= tx_uart_reg;
163+
tx_next_st <= tx_present_st;
164+
165+
case tx_present_st is
166+
167+
when idle =>
168+
if (RX_VALID = '1') then
169+
tx_uart_ready_next <= '0';
170+
tx_uart_reg_next <= '1';
171+
tx_next_st <= transmit_data;
172+
else
173+
tx_uart_ready_next <= '1';
174+
tx_uart_reg_next <= '1';
175+
tx_next_st <= idle;
176+
end if;
177+
178+
when transmit_data =>
179+
if (uart_clk_en = '1') then
180+
if (tx_uart_bit_count = DATA_BITS+1) then -- stop bit
181+
tx_uart_bit_count_next <= 0;
182+
tx_uart_reg_next <= '1';
183+
tx_next_st <= idle;
184+
elsif (tx_uart_bit_count = 0) then -- start bit
185+
tx_uart_bit_count_next <= tx_uart_bit_count + 1;
186+
tx_uart_reg_next <= '0';
187+
tx_next_st <= transmit_data;
188+
else -- data bits
189+
tx_uart_bit_count_next <= tx_uart_bit_count + 1;
190+
tx_uart_reg_next <= tx_uart_data(tx_uart_bit_count-1);
191+
tx_next_st <= transmit_data;
192+
end if;
193+
end if;
194+
195+
when others =>
196+
tx_uart_bit_count_next <= 0;
197+
tx_uart_ready_next <= '0';
198+
tx_uart_reg_next <= '1';
199+
tx_next_st <= idle;
200+
201+
end case;
202+
end process;
119203

120204
-- -------------------------------------------------------------------------
121205
-- RX UART FSM
@@ -126,25 +210,25 @@ begin
126210
if (rising_edge(CLK)) then
127211
if (RST = '1') then
128212
rx_present_st <= idle;
129-
rx_data_bit_count <= 0;
130-
rx_data_reg <= (others => '0');
131-
rx_data_vld <= '0';
213+
rx_uart_bit_count <= 0;
214+
rx_uart_data <= (others => '0');
215+
rx_uart_vld <= '0';
132216
else
133217
rx_present_st <= rx_next_st;
134-
rx_data_bit_count <= rx_data_bit_count_next;
135-
rx_data_reg <= rx_data_reg_next;
136-
rx_data_vld <= rx_data_vld_next;
218+
rx_uart_bit_count <= rx_uart_bit_count_next;
219+
rx_uart_data <= rx_uart_data_next;
220+
rx_uart_vld <= rx_uart_vld_next;
137221
end if;
138222
end if;
139223
end process;
140224

141-
process (rx_present_st, uart_clk_en, RX_UART, rx_data_bit_count, rx_data_reg, rx_data_vld)
225+
process (rx_present_st, uart_clk_en, RX_UART, rx_uart_bit_count, rx_uart_data, rx_uart_vld)
142226
begin
143227

144-
rx_data_bit_count_next <= rx_data_bit_count;
145-
rx_data_reg_next <= rx_data_reg;
146-
rx_data_vld_next <= rx_data_vld;
147-
rx_next_st <= rx_present_st;
228+
rx_uart_bit_count_next <= rx_uart_bit_count;
229+
rx_uart_data_next <= rx_uart_data;
230+
rx_uart_vld_next <= rx_uart_vld;
231+
rx_next_st <= rx_present_st;
148232

149233
case rx_present_st is
150234

@@ -157,32 +241,32 @@ begin
157241

158242
when receive_data =>
159243
if (uart_clk_en = '1') then
160-
if (rx_data_bit_count = DATA_BITS-1) then
161-
rx_data_bit_count_next <= 0;
162-
rx_data_reg_next(DATA_BITS-1) <= RX_UART;
163-
rx_data_reg_next(DATA_BITS-2 downto 0) <= rx_data_reg(DATA_BITS-1 downto 1);
244+
if (rx_uart_bit_count = DATA_BITS-1) then
245+
rx_uart_bit_count_next <= 0;
246+
rx_uart_data_next(DATA_BITS-1) <= RX_UART;
247+
rx_uart_data_next(DATA_BITS-2 downto 0) <= rx_uart_data(DATA_BITS-1 downto 1);
164248
rx_next_st <= receive_stop_bit;
165249
else
166-
rx_data_bit_count_next <= rx_data_bit_count + 1;
167-
rx_data_reg_next(DATA_BITS-1) <= RX_UART;
168-
rx_data_reg_next(DATA_BITS-2 downto 0) <= rx_data_reg(DATA_BITS-1 downto 1);
250+
rx_uart_bit_count_next <= rx_uart_bit_count + 1;
251+
rx_uart_data_next(DATA_BITS-1) <= RX_UART;
252+
rx_uart_data_next(DATA_BITS-2 downto 0) <= rx_uart_data(DATA_BITS-1 downto 1);
169253
rx_next_st <= receive_data;
170254
end if;
171255
end if;
172256

173257
when receive_stop_bit =>
174258
if (uart_clk_en = '1' AND RX_UART = '1') then
175-
rx_data_vld_next <= '1';
259+
rx_uart_vld_next <= '1';
176260
rx_next_st <= idle;
177261
else
178-
rx_data_vld_next <= '0';
262+
rx_uart_vld_next <= '0';
179263
rx_next_st <= receive_stop_bit;
180264
end if;
181265

182266
when others =>
183-
rx_data_bit_count_next <= 0;
184-
rx_data_reg_next <= (others => '0');
185-
rx_data_vld_next <= '0';
267+
rx_uart_bit_count_next <= 0;
268+
rx_uart_data_next <= (others => '0');
269+
rx_uart_vld_next <= '0';
186270
rx_next_st <= idle;
187271

188272
end case;

0 commit comments

Comments
 (0)