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jakubcabaljakubcabal
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UART: Some optimization and cleanup code
1 parent b973b48 commit 83a977a

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3 files changed

+123
-88
lines changed

3 files changed

+123
-88
lines changed

‎source/comp/uart_rx.vhd‎

Lines changed: 34 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -13,18 +13,18 @@ use IEEE.NUMERIC_STD.ALL;
1313

1414
entity UART_RX is
1515
Generic (
16-
PARITY_BIT : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
16+
PARITY_BIT : string := "none" -- type of parity: "none", "even", "odd", "mark", "space"
1717
);
1818
Port (
1919
CLK : in std_logic; -- system clock
2020
RST : in std_logic; -- high active synchronous reset
2121
-- UART INTERFACE
2222
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
23-
UART_RXD : in std_logic;
23+
UART_RXD : in std_logic; -- serial receive data
2424
-- USER DATA OUTPUT INTERFACE
25-
DATA_OUT : out std_logic_vector(7 downto 0);
26-
DATA_VLD : out std_logic; -- when DATA_VLD = 1, data on DATA_OUT are valid
27-
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid, current and next data may be invalid
25+
DATA_OUT : out std_logic_vector(7 downto 0); -- output data
26+
DATA_VLD : out std_logic; -- when DATA_VLD = 1, output data are valid
27+
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid
2828
);
2929
end UART_RX;
3030

@@ -35,8 +35,7 @@ architecture FULL of UART_RX is
3535
signal rx_clk_divider_en : std_logic;
3636
signal rx_data : std_logic_vector(7 downto 0);
3737
signal rx_bit_count : unsigned(2 downto 0);
38-
signal rx_bit_count_en : std_logic;
39-
signal rx_data_shreg_en : std_logic;
38+
signal rx_receiving_data : std_logic;
4039
signal rx_parity_bit : std_logic;
4140
signal rx_parity_error : std_logic;
4241
signal rx_parity_check_en : std_logic;
@@ -49,30 +48,36 @@ architecture FULL of UART_RX is
4948
begin
5049

5150
-- -------------------------------------------------------------------------
52-
-- UART RECEIVER CLOCK DIVIDER
51+
-- UART RECEIVER CLOCK DIVIDER AND CLOCK ENABLE FLAG
5352
-- -------------------------------------------------------------------------
5453

55-
uart_rx_clk_divider : process (CLK)
54+
uart_rx_clk_divider_p : process (CLK)
5655
begin
5756
if (rising_edge(CLK)) then
5857
if (rx_clk_divider_en = '1') then
5958
if (uart_clk_en = '1') then
6059
if (rx_ticks = "1111") then
6160
rx_ticks <= (others => '0');
62-
rx_clk_en <= '0';
63-
elsif (rx_ticks = "0111") then
64-
rx_ticks <= rx_ticks + 1;
65-
rx_clk_en <= '1';
6661
else
6762
rx_ticks <= rx_ticks + 1;
68-
rx_clk_en <= '0';
6963
end if;
7064
else
7165
rx_ticks <= rx_ticks;
72-
rx_clk_en <= '0';
7366
end if;
7467
else
7568
rx_ticks <= (others => '0');
69+
end if;
70+
end if;
71+
end process;
72+
73+
uart_rx_clk_en_p : process (CLK)
74+
begin
75+
if (rising_edge(CLK)) then
76+
if (RST = '1') then
77+
rx_clk_en <= '0';
78+
elsif (uart_clk_en = '1' AND rx_ticks = "0111") then
79+
rx_clk_en <= '1';
80+
else
7681
rx_clk_en <= '0';
7782
end if;
7883
end if;
@@ -82,12 +87,12 @@ begin
8287
-- UART RECEIVER BIT COUNTER
8388
-- -------------------------------------------------------------------------
8489

85-
uart_rx_bit_counter : process (CLK)
90+
uart_rx_bit_counter_p : process (CLK)
8691
begin
8792
if (rising_edge(CLK)) then
8893
if (RST = '1') then
8994
rx_bit_count <= (others => '0');
90-
elsif (rx_bit_count_en = '1' AND rx_clk_en = '1') then
95+
elsif (rx_clk_en = '1' AND rx_receiving_data = '1') then
9196
if (rx_bit_count = "111") then
9297
rx_bit_count <= (others => '0');
9398
else
@@ -101,12 +106,12 @@ begin
101106
-- UART RECEIVER DATA SHIFT REGISTER
102107
-- -------------------------------------------------------------------------
103108

104-
uart_rx_data_shift_reg : process (CLK)
109+
uart_rx_data_shift_reg_p : process (CLK)
105110
begin
106111
if (rising_edge(CLK)) then
107112
if (RST = '1') then
108113
rx_data <= (others => '0');
109-
elsif (rx_clk_en = '1' AND rx_data_shreg_en = '1') then
114+
elsif (rx_clk_en = '1' AND rx_receiving_data = '1') then
110115
rx_data <= UART_RXD & rx_data(7 downto 1);
111116
end if;
112117
end if;
@@ -129,7 +134,7 @@ begin
129134
PARITY_OUT => rx_parity_bit
130135
);
131136

132-
uart_rx_parity_check_reg : process (CLK)
137+
uart_rx_parity_check_reg_p : process (CLK)
133138
begin
134139
if (rising_edge(CLK)) then
135140
if (RST = '1') then
@@ -149,14 +154,14 @@ begin
149154
-- UART RECEIVER OUTPUT REGISTER
150155
-- -------------------------------------------------------------------------
151156

152-
uart_rx_output_reg : process (CLK)
157+
uart_rx_output_reg_p : process (CLK)
153158
begin
154159
if (rising_edge(CLK)) then
155160
if (RST = '1') then
156161
DATA_VLD <= '0';
157162
FRAME_ERROR <= '0';
158163
else
159-
if (rx_output_reg_en = '1') then
164+
if (rx_clk_en = '1' AND rx_output_reg_en = '1') then
160165
DATA_VLD <= NOT rx_parity_error AND UART_RXD;
161166
FRAME_ERROR <= NOT UART_RXD;
162167
else
@@ -190,8 +195,7 @@ begin
190195

191196
when idle =>
192197
rx_output_reg_en <= '0';
193-
rx_bit_count_en <= '0';
194-
rx_data_shreg_en <= '0';
198+
rx_receiving_data <= '0';
195199
rx_clk_divider_en <= '0';
196200
rx_parity_check_en <= '0';
197201

@@ -203,8 +207,7 @@ begin
203207

204208
when startbit =>
205209
rx_output_reg_en <= '0';
206-
rx_bit_count_en <= '0';
207-
rx_data_shreg_en <= '0';
210+
rx_receiving_data <= '0';
208211
rx_clk_divider_en <= '1';
209212
rx_parity_check_en <= '0';
210213

@@ -216,8 +219,7 @@ begin
216219

217220
when databits =>
218221
rx_output_reg_en <= '0';
219-
rx_bit_count_en <= '1';
220-
rx_data_shreg_en <= '1';
222+
rx_receiving_data <= '1';
221223
rx_clk_divider_en <= '1';
222224
rx_parity_check_en <= '0';
223225

@@ -233,8 +235,7 @@ begin
233235

234236
when paritybit =>
235237
rx_output_reg_en <= '0';
236-
rx_bit_count_en <= '0';
237-
rx_data_shreg_en <= '0';
238+
rx_receiving_data <= '0';
238239
rx_clk_divider_en <= '1';
239240
rx_parity_check_en <= '1';
240241

@@ -245,23 +246,20 @@ begin
245246
end if;
246247

247248
when stopbit =>
248-
rx_bit_count_en <= '0';
249-
rx_data_shreg_en <= '0';
249+
rx_receiving_data <= '0';
250250
rx_clk_divider_en <= '1';
251251
rx_parity_check_en <= '0';
252+
rx_output_reg_en <= '1';
252253

253254
if (rx_clk_en = '1') then
254255
rx_nstate <= idle;
255-
rx_output_reg_en <= '1';
256256
else
257257
rx_nstate <= stopbit;
258-
rx_output_reg_en <= '0';
259258
end if;
260259

261260
when others =>
262261
rx_output_reg_en <= '0';
263-
rx_bit_count_en <= '0';
264-
rx_data_shreg_en <= '0';
262+
rx_receiving_data <= '0';
265263
rx_clk_divider_en <= '0';
266264
rx_parity_check_en <= '0';
267265
rx_nstate <= idle;

‎source/comp/uart_tx.vhd‎

Lines changed: 21 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -13,18 +13,18 @@ use IEEE.NUMERIC_STD.ALL;
1313

1414
entity UART_TX is
1515
Generic (
16-
PARITY_BIT : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
16+
PARITY_BIT : string := "none" -- type of parity: "none", "even", "odd", "mark", "space"
1717
);
1818
Port (
1919
CLK : in std_logic; -- system clock
2020
RST : in std_logic; -- high active synchronous reset
2121
-- UART INTERFACE
2222
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
23-
UART_TXD : out std_logic;
23+
UART_TXD : out std_logic; -- serial transmit data
2424
-- USER DATA INPUT INTERFACE
25-
DATA_IN : in std_logic_vector(7 downto 0);
26-
DATA_SEND : in std_logic; -- when DATA_SEND = 1, data on DATA_IN will be transmit, DATA_SEND can set to 1 only when BUSY = 0
27-
BUSY : out std_logic -- when BUSY = 1 transiever is busy, you must not set DATA_SEND to 1
25+
DATA_IN : in std_logic_vector(7 downto 0); -- input data
26+
DATA_SEND : in std_logic; -- when DATA_SEND = 1, input data are valid and will be transmit
27+
BUSY : out std_logic -- when BUSY = 1, transmitter is busy and you must not set DATA_SEND to 1
2828
);
2929
end UART_TX;
3030

@@ -52,27 +52,33 @@ begin
5252
-- UART TRANSMITTER CLOCK DIVIDER
5353
-- -------------------------------------------------------------------------
5454

55-
uart_tx_clk_divider : process (CLK)
55+
uart_tx_clk_divider_p : process (CLK)
5656
begin
5757
if (rising_edge(CLK)) then
5858
if (tx_clk_divider_en = '1') then
5959
if (uart_clk_en = '1') then
6060
if (tx_ticks = "1111") then
6161
tx_ticks <= (others => '0');
62-
tx_clk_en <= '0';
63-
elsif (tx_ticks = "0001") then
64-
tx_ticks <= tx_ticks + 1;
65-
tx_clk_en <= '1';
6662
else
6763
tx_ticks <= tx_ticks + 1;
68-
tx_clk_en <= '0';
6964
end if;
7065
else
7166
tx_ticks <= tx_ticks;
72-
tx_clk_en <= '0';
7367
end if;
7468
else
7569
tx_ticks <= (others => '0');
70+
end if;
71+
end if;
72+
end process;
73+
74+
uart_tx_clk_en_p : process (CLK)
75+
begin
76+
if (rising_edge(CLK)) then
77+
if (RST = '1') then
78+
tx_clk_en <= '0';
79+
elsif (uart_clk_en = '1' AND tx_ticks = "0001") then
80+
tx_clk_en <= '1';
81+
else
7682
tx_clk_en <= '0';
7783
end if;
7884
end if;
@@ -82,7 +88,7 @@ begin
8288
-- UART TRANSMITTER INPUT DATA REGISTER
8389
-- -------------------------------------------------------------------------
8490

85-
uart_tx_input_data_reg : process (CLK)
91+
uart_tx_input_data_reg_p : process (CLK)
8692
begin
8793
if (rising_edge(CLK)) then
8894
if (RST = '1') then
@@ -97,7 +103,7 @@ begin
97103
-- UART TRANSMITTER BIT COUNTER
98104
-- -------------------------------------------------------------------------
99105

100-
uart_tx_bit_counter : process (CLK)
106+
uart_tx_bit_counter_p : process (CLK)
101107
begin
102108
if (rising_edge(CLK)) then
103109
if (RST = '1') then
@@ -136,7 +142,7 @@ begin
136142
-- UART TRANSMITTER OUTPUT DATA REGISTER
137143
-- -------------------------------------------------------------------------
138144

139-
uart_tx_output_data_reg : process (CLK)
145+
uart_tx_output_data_reg_p : process (CLK)
140146
begin
141147
if (rising_edge(CLK)) then
142148
if (RST = '1') then

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