[MAINTENANCE]: Small code clean and optimization

Author: jakubcabal

rtl/comp/uart_clk_div.vhd

@@ -55,11 +55,7 @@ begin
     div_mark_p : process (CLK)
     begin
         if (rising_edge(CLK)) then
-            if (RST = '1') then
-                DIV_MARK <= '0';
-            else
-                DIV_MARK <= ENABLE and clk_div_cnt_mark;
-            end if;
+            DIV_MARK <= ENABLE and clk_div_cnt_mark;
         end if;
     end process;
 

rtl/comp/uart_debouncer.vhd

@@ -1,7 +1,6 @@
 --------------------------------------------------------------------------------
 -- PROJECT: SIMPLE UART FOR FPGA
 --------------------------------------------------------------------------------
--- MODULE:  UART DEBOUNCER
 -- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
 -- LICENSE: The MIT License (MIT), please read LICENSE file
 -- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
@@ -22,7 +21,7 @@ entity UART_DEBOUNCER is
         DEB_IN  : in  std_logic; -- input of signal from outside FPGA
         DEB_OUT : out std_logic  -- output of debounced (filtered) signal
     );
-end UART_DEBOUNCER;
+end entity;
 
 architecture RTL of UART_DEBOUNCER is
 
@@ -76,4 +75,4 @@ begin
         end if;
     end process;
 
-end RTL;
+end architecture;

rtl/comp/uart_parity.vhd

@@ -1,7 +1,6 @@
 --------------------------------------------------------------------------------
 -- PROJECT: SIMPLE UART FOR FPGA
 --------------------------------------------------------------------------------
--- MODULE:  UART PARITY BIT GENERATOR
 -- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
 -- LICENSE: The MIT License (MIT), please read LICENSE file
 -- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
@@ -20,9 +19,9 @@ entity UART_PARITY is
         DATA_IN     : in  std_logic_vector(DATA_WIDTH-1 downto 0);
         PARITY_OUT  : out std_logic
     );
-end UART_PARITY;
+end entity;
 
-architecture FULL of UART_PARITY is
+architecture RTL of UART_PARITY is
 
 begin
 
@@ -31,7 +30,6 @@ begin
     -- -------------------------------------------------------------------------
 
     even_parity_g : if (PARITY_TYPE = "even") generate
-
         process (DATA_IN)
         	variable parity_temp : std_logic;
         begin
@@ -41,11 +39,9 @@ begin
             end loop;
             PARITY_OUT <= parity_temp;
         end process;
-
     end generate;
 
     odd_parity_g : if (PARITY_TYPE = "odd") generate
-
         process (DATA_IN)
         	variable parity_temp : std_logic;
         begin
@@ -55,19 +51,14 @@ begin
             end loop;
             PARITY_OUT <= parity_temp;
         end process;
-
     end generate;
 
     mark_parity_g : if (PARITY_TYPE = "mark") generate
-
         PARITY_OUT <= '1';
-
     end generate;
 
     space_parity_g : if (PARITY_TYPE = "space") generate
-
         PARITY_OUT <= '0';
-
     end generate;
 
-end FULL;
+end architecture;

rtl/comp/uart_tx.vhd

@@ -26,9 +26,9 @@ entity UART_TX is
         DIN_VLD     : in  std_logic; -- when DIN_VLD = 1, input data (DIN) are valid
         DIN_RDY     : out std_logic  -- when DIN_RDY = 1, transmitter is ready and valid input data will be accepted for transmiting
     );
-end UART_TX;
+end entity;
 
-architecture FULL of UART_TX is
+architecture RTL of UART_TX is
 
     signal tx_clk_en       : std_logic;
     signal tx_clk_div_clr  : std_logic;
@@ -250,4 +250,4 @@ begin
         end case;
     end process;
 
-end FULL;
+end architecture;

rtl/uart.vhd

@@ -33,6 +33,7 @@ use IEEE.MATH_REAL.ALL;
     -- UART loopback example is for CYC1000 board now.
 -- Version 1.3 - 
     -- Added better simulation with automatic checking of transactions.
+    -- Little code cleaning and code optimization.
 
 entity UART is
     Generic (

sim/uart_tb.vhd

@@ -12,9 +12,9 @@ use IEEE.NUMERIC_STD.ALL;
 use IEEE.MATH_REAL.ALL;
 
 entity UART_TB is
-end UART_TB;
+end entity;
 
-architecture FULL of UART_TB is
+architecture SIM of UART_TB is
 
     signal CLK : std_logic;
     signal RST : std_logic;