Update README.md

Author: jakubcabal

README.md

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 Simple UART (Universal Asynchronous Receiver & Transmitter) module for serial communication with an FPGA. The UART module was implemented using VHDL.
 
+**This is not stable version! There are still a few bugs and the module does not work correctly.**
 **The default settings are 115200 Baud rate, 8 Data bits, 1 Stop bit, No parity.**
 
 The UART module passed simulations. In the near future it will be implemented generic support for parity bit and set the number of stop bits. Stay tuned!