Add usage summary and small changes

Author: jakubcabal

README.md

@@ -2,4 +2,10 @@
 
 Simple UART (Universal Asynchronous Receiver & Transmitter) module for serial communication with an FPGA. The UART module was implemented using VHDL.
 
-###UART module is not yet completed. Stay tuned!
+The UART module passed simulations. In the near future it will be implemented generic support for parity bit and set the number of stop bits. Stay tuned!
+
+#####Synthesis resource usage summary:
+- Logic element (LUT): 85
+- Registers (FF): 50
+
+*Synthesis was performed using Quartus II 64-Bit Version 13.0.1 with defauld values of generics.*