diff --git a/flow-Agent/AutoTuner-integration/ORFS-with-AutoTuner/analyst_agent_workbench.py b/flow-Agent/AutoTuner-integration/ORFS-with-AutoTuner/analyst_agent_workbench.py index 939872c..785e1d5 100644 --- a/flow-Agent/AutoTuner-integration/ORFS-with-AutoTuner/analyst_agent_workbench.py +++ b/flow-Agent/AutoTuner-integration/ORFS-with-AutoTuner/analyst_agent_workbench.py @@ -9,12 +9,47 @@ import anthropic # type: ignore import time # For retry delay import random # For placeholder BayesOpt, can be removed if BayesOpt is robust +from pathlib import Path # For Bayesian Optimization from skopt import Optimizer from skopt.space import Real, Integer, Categorical from skopt.utils import use_named_args # For easier handling of parameters +from rag.index import load_embeddings_and_docs, build_and_save_embeddings +from rag.util import answerWithRAG, modelUtility +from sentence_transformers import SentenceTransformer +import torch + +## ========== New addition: Three QA data paths========== +base_dir = Path(__file__).parent + +# Construct a relative path +qa_paths = [ + base_dir.parent.parent / "EDA-Corpus-main" / "Augmented_Data" / "Question-Answer" / "Flow" / "Flow.csv", + base_dir.parent.parent / "EDA-Corpus-main" / "Augmented_Data" / "Question-Answer" / "General" / "General.csv", + base_dir.parent.parent / "EDA-Corpus-main" / "Augmented_Data" / "Question-Answer" / "Tools" / "Tools.csv", +] +merged_csv_path = "RAGData/RAGFLOWGUIDE.csv" # Unify the file path of the vector library +os.makedirs("RAGData", exist_ok=True) + +def merge_qa_files(file_list, output_path): + dfs = [] + for path in file_list: + if os.path.exists(path): + df = pd.read_csv(path) + # Clean up duplicates and blank lines + df = df.drop_duplicates().dropna(how="any") + dfs.append(df) + print(f"[RAG] Loaded file: {path}, containing {len(df)} records.") + else: + print(f"[Warning] The file does not exist: {path}") + if dfs: + merged = pd.concat(dfs, ignore_index=True) + merged.to_csv(output_path, index=False) + print(f"[RAG] The QA files have been merged into {output_path}, totaling {len(merged)} pieces of data.") + else: + raise FileNotFoundError("[Error] No valid QA files were found.") # --- Global State for Tools --- TOOL_STATE = { "current_df": pd.DataFrame(), @@ -190,6 +225,17 @@ def get_sample_rows(n_rows=3, query_string=None): return header + ":\n" + df_to_sample.sample(actual_n_rows).to_string() except Exception as e: return "Error in get_sample_rows: " + str(e) + "\n" + traceback.format_exc() +def get_rag_context(query, topk=6): + """ + Answer questions using the RAG database. + query: Query strings of users or LLMS + topk: Search for the top k relevant documents + """ + try: + return answerWithRAG(query, embeddings, embeddingModel, docs, docsDict, topk=topk) + except Exception as e: + return f"Error in RAG retrieval: {str(e)}" + def suggest_bayesian_optimization_configs(target_metric_to_minimize, n_suggestions=5, training_data_query=None, validation_data_query=None): log_to_file_and_console("[BAYESOPT] Called suggest_bayesian_optimization_configs.") log_to_file_and_console("[BAYESOPT] Target metric: " + str(target_metric_to_minimize)) @@ -383,6 +429,7 @@ def suggest_bayesian_optimization_configs(target_metric_to_minimize, n_suggestio "get_sample_rows": get_sample_rows, "reset_data_to_all_valid_runs": reset_data_to_all_valid_runs, "suggest_bayesian_optimization_configs": suggest_bayesian_optimization_configs, + "get_rag_context": get_rag_context, "suggest_new_tool": lambda suggested_tool_name, suggested_tool_description: log_to_file_and_console("[LLM TOOL SUGGESTION]\nName: " + str(suggested_tool_name) + "\nDescription: " + str(suggested_tool_description)) or "New tool suggestion noted: " + str(suggested_tool_name) } @@ -506,7 +553,20 @@ def suggest_bayesian_optimization_configs(target_metric_to_minimize, n_suggestio }, "required": ["target_metric_to_minimize"] } + }, + { + "name": "get_rag_context", + "description": "Retrieve the RAG database of OpenROAD-Agent and return relevant API documentation or code snippets for auxiliary analysis.", + "input_schema": { + "type": "object", + "properties": { + "query": {"type": "string", "description": "The question to be queried"}, + "topk": {"type": "integer", "default": 6, "description": "The number of relevant documents returned"} + }, + "required": ["query"] + } } + ] def run_agent_workbench(main_df=None, circuit=None, pdk=None, @@ -551,6 +611,20 @@ def run_agent_workbench(main_df=None, circuit=None, pdk=None, except Exception as e: print("Error initializing Anthropic client: " + str(e)) return + + try: + embeddings_np, docs, docsDict = load_embeddings_and_docs() + embeddings = torch.tensor(embeddings_np) + embeddingModel = SentenceTransformer("mxbai-embed-large-v1") + print("[RAG] The vector database was successfully loaded.") + except FileNotFoundError: + print("[RAG] The vector library does not exist and is under construction...") + merge_qa_files(qa_paths, merged_csv_path) + build_and_save_embeddings(merged_csv_path) + embeddings_np, docs, docsDict = load_embeddings_and_docs() + embeddings = torch.tensor(embeddings_np) + embeddingModel = SentenceTransformer("mxbai-embed-large-v1") + print("[RAG] The vector library has been built and loaded.") session_uuid = uuid.uuid4() context_file_name = log_dir + "/" + args.circuit + "_" + args.pdk + "_" + args.optimization_goal + "_context_" + str(session_uuid) + ".txt" diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/DB/circuit_modification.csv b/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/DB/circuit_modification.csv new file mode 100644 index 0000000..c0d0783 --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/DB/circuit_modification.csv @@ -0,0 +1,2519 @@ +code,prompt +"# Invert the rotation and the location of instances with the library cell type 'NAND2_X1'. + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the name of the library cell type is 'NAND2_X1' + if inst.getMaster().getName() == 'NAND2_X1': + # Invert the rotation and the location of the instance + transform = inst.getTransform() + transform.invert() + inst.setTransform(transform)",Invert the rotation and the location of instances with the library cell type 'NAND2_X1' +"# Horizontally flip the rotation of the instances whose library cell types are 'AND2_X1' + +#define flipping function +def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Horizontally flip the rotation of the instance + orient = inst.getOrient() + orient = flipX(orient) + inst.setOrient(orient)",Horizontally flip the rotation of the instances whose library cell types are 'AND2_X1' +"# Horizontally flip the rotation of the instances whose library cell types are 'NAND2_X1' + +#define flipping function +def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'NAND2_X1' + if inst.getMaster().getName() == 'NAND2_X1': + # Horizontally flip the rotation of the instance + orient = inst.getTransform().getOrient() + orient = flipX(orient) + inst.setOrient(orient)",Horizontally flip the rotation of the instances whose library cell types are 'NAND2_X1' +"# Horizontally flip the rotation of the instances whose library cell types are 'AND2_X1' + +#define flipping function +def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Horizontally flip the rotation of the instance + transform = inst.getTransform() + orient = transform.getOrient() + orient = flipX(orient) + transform.setOrient(orient) + inst.setTransform(transform)",Horizontally flip the rotation of the instances whose library cell types are 'AND2_X1' +"# Vertically flip the rotation of the instances whose library cell types are 'AND2_X1' + +#define flipping function +def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Vertically flip the rotation of the instance + transform = inst.getTransform() + orient = transform.getOrient() + orient = flipY(orient) + transform.setOrient(orient) + inst.setTransform(transform) ",Vertically flip the rotation of the instances whose library cell types are 'AND2_X1' +"# Vertically flip the rotation of the instances whose library cell types are 'AND2_X1' + +#define flipping function +def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'NAND2_X1' + if inst.getMaster().getName() == 'NAND2_X1': + # Vertically flip the rotation of the instance + transform = inst.getTransform() + orient = transform.getOrient() + orient = flipY(orient) + inst.setOrient(orient)",Vertically flip the rotation of the instances whose library cell types are 'NAND2_X1' +"# Vertically flip the rotation of the instances whose library cell types are 'AND2_X1' + +#define flipping function +def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Vertically flip the rotation of the instance + orient = inst.getOrient() + orient = flipY(orient) + inst.setOrient(orient)",Vertically flip the rotation of the instances whose library cell types are 'AND2_X1' +"# Set the rotation of the instance '_411_' to 'MX' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('_411_') + +# Set the rotation of the instance to 'MX' +inst.setOrient('MX')",set the rotation of the instance '_411_' to 'MX' +"# Set the rotation of the instance '_411_' to 'MX' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('_411_') + +# Set the rotation of the instance to 'MX' +transform = inst.getTransform() +transform.setOrient('MX') +inst.setTransform(transform)",set the rotation of the instance '_411_' to 'MX' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input1' as mentioned in the prompt +inst = block.findInst('input1') +# Get the orientation of the instance +orient = inst.getOrient() +# Check if the orientation is ""MX"" +if orient == 'MX': + # Set the orientation of the instance to ""R0"" + inst.setOrient('R0') +elif orient == 'R0': + # Set the orientation of the instance to ""MX"" + inst.setOrient('MX')",Change the rotation of an instance 'input0'. If the rotation is 'MX' change it to 'R0' and vise versa +"# Set the rotation of the instance '_411_' to 'R0' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('_411_') + +# Set the rotation of the instance to 'R0' +inst.setOrient('R0')",set the rotation of the instance '_411_' to 'R0' +"# Set the rotation of the instance '_411_' to 'R0' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('_411_') + +# Set the rotation of the instance to 'R0' +transform = inst.getTransform() +transform.setOrient('R0') +inst.setTransform(transform)",set the rotation of the instance '_411_' to 'R0' +"# Set the rotation of the instance 'reg[0]_123' to 'R0' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('reg[0]_123') + +# Set the rotation of the instance to 'R0' +inst.setOrient('R0')",set the rotation of the instance 'reg[0]_123' to 'R0' +"# Set the rotation of the instance 'reg[0]_123' to 'R0' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('reg[0]_123') + +# Set the rotation of the instance to 'R0' +transform = inst.getTransform() +transform.setOrient('R0') +inst.setTransform(transform)",set the rotation of the instance 'reg[0]_123' to 'R0' +"# Set the rotation of the instance '118_i[0]' to 'R90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('118_i[0]') + +# Set the rotation of the instance to 'R90' +inst.setOrient('R90')",set the rotation of the instance '118_i[0]' to 'R90' +"# Set the rotation of the instance '118_i[0]' to 'R90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('118_i[0]') + +# Set the rotation of the instance to 'R90' +transform = inst.getTransform() +transform.setOrient('R90') +inst.setTransform(transform)",set the rotation of the instance '118_i[0]' to 'R90' +"# Set the rotation of the instance 'super40' to 'R90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('super40') + +# Set the rotation of the instance to 'R90' +inst.setOrient('R90')",set the rotation of the instance 'super40' to 'R90' +"# Set the rotation of the instance 'super40' to 'R90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('super40') + +# Set the rotation of the instance to 'R90' +transform = inst.getTransform() +transform.setOrient('R90') +inst.setTransform(transform)",set the rotation of the instance 'super40' to 'R90' +"# Set the rotation of the instance '118_i[0]' to 'R180' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('118_i[0]') + +# Set the rotation of the instance to 'R180' +inst.setOrient('R180')",set the rotation of the instance '118_i[0]' to 'R180' +"# Set the rotation of the instance '118_i[0]' to 'R180' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('118_i[0]') + +# Set the rotation of the instance to 'R180' +transform = inst.getTransform() +transform.setOrient('R180') +inst.setTransform(transform)",set the rotation of the instance '118_i[0]' to 'R180' +"# Set the rotation of the instance 'super40' to 'R180' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('super40') + +# Set the rotation of the instance to 'R180' +inst.setOrient('R180')",set the rotation of the instance 'super40' to 'R180' +"# Set the rotation of the instance 'super40' to 'R180' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('super40') + +# Set the rotation of the instance to 'R180' +transform = inst.getTransform() +transform.setOrient('R180') +inst.setTransform(transform)",set the rotation of the instance 'super40' to 'R180' +"# Set the rotation of the instance 'icache_1/_21661_' to 'R270' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Set the rotation of the instance to 'R270' +inst.setOrient('R270')",set the rotation of the instance 'icache_1/_21661_' to 'R270' +"# Set the rotation of the instance 'icache_1/_21661_' to 'R270' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Set the rotation of the instance to 'R270' +transform = inst.getTransform() +transform.setOrient('R270') +inst.setTransform(transform)",set the rotation of the instance 'icache_1/_21661_' to 'R270' +"# Set the rotation of the instance 'input31' to 'R270' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Set the rotation of the instance to 'R270' +inst.setOrient('R270')",set the rotation of the instance 'input31' to 'R270' +"# Set the rotation of the instance 'input31' to 'R270' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Set the rotation of the instance to 'R270' +transform = inst.getTransform() +transform.setOrient('R270') +inst.setTransform(transform)",set the rotation of the instance 'input31' to 'R270' +"# Set the rotation of the instance 'icache_1/_21661_' to 'MY' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Set the rotation of the instance to 'MY' +inst.setOrient('MY')",set the rotation of the instance 'icache_1/_21661_' to 'MY' +"# Set the rotation of the instance 'icache_1/_21661_' to 'MY' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Set the rotation of the instance to 'MY' +transform = inst.getTransform() +transform.setOrient('MY') +inst.setTransform(transform)",set the rotation of the instance 'icache_1/_21661_' to 'MY' +"# Set the rotation of the instance 'input31' to 'MY' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Set the rotation of the instance to 'MY' +inst.setOrient('MY')",set the rotation of the instance 'input31' to 'MY' +"# Set the rotation of the instance 'input31' to 'MY' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Set the rotation of the instance to 'MY' +transform = inst.getTransform() +transform.setOrient('MY') +inst.setTransform(transform)",set the rotation of the instance 'input31' to 'MY' +"# Set the rotation of the instance 'icache_1/_21661_' to 'MYR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Set the rotation of the instance to 'MYR90' +inst.setOrient('MYR90')",set the rotation of the instance 'icache_1/_21661_' to 'MYR90' +"# Set the rotation of the instance 'icache_1/_21661_' to 'MYR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Set the rotation of the instance to 'MYR90' +transform = inst.getTransform() +transform.setOrient('MYR90') +inst.setTransform(transform)",set the rotation of the instance 'icache_1/_21661_' to 'MYR90' +"# Set the rotation of the instance 'input31' to 'MYR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Set the rotation of the instance to 'MYR90' +inst.setOrient('MYR90')",set the rotation of the instance 'input31' to 'MYR90' +"# Set the rotation of the instance 'input31' to 'MYR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Set the rotation of the instance to 'MYR90' +transform = inst.getTransform() +transform.setOrient('MYR90') +inst.setTransform(transform)",set the rotation of the instance 'input31' to 'MYR90' +"# Set the rotation of the instance 'icache_1/_21661_' to 'MX' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Set the rotation of the instance to 'MX' +inst.setOrient('MX')",set the rotation of the instance 'icache_1/_21661_' to 'MX' +"# Set the rotation of the instance 'icache_1/_21661_' to 'MX' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Set the rotation of the instance to 'MX' +transform = inst.getTransform() +transform.setOrient('MX') +inst.setTransform(transform)",set the rotation of the instance 'icache_1/_21661_' to 'MX' +"# Set the rotation of the instance 'input31' to 'MX' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Set the rotation of the instance to 'MX' +inst.setOrient('MX')",set the rotation of the instance 'input31' to 'MX' +"# Set the rotation of the instance 'input31' to 'MX' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Set the rotation of the instance to 'MX' +transform = inst.getTransform() +transform.setOrient('MX') +inst.setTransform(transform)",set the rotation of the instance 'input31' to 'MX' +"# Set the rotation of the instance 'icache_1/_21661_' to 'MXR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Set the rotation of the instance to 'MXR90' +inst.setOrient('MXR90')",set the rotation of the instance 'icache_1/_21661_' to 'MXR90' +"# Set the rotation of the instance 'icache_1/_21661_' to 'MXR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Set the rotation of the instance to 'MXR90' +transform = inst.getTransform() +transform.setOrient('MXR90') +inst.setTransform(transform)",set the rotation of the instance 'icache_1/_21661_' to 'MXR90' +"# Set the rotation of the instance 'input31' to 'MXR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Set the rotation of the instance to 'MXR90' +inst.setOrient('MXR90')",set the rotation of the instance 'input31' to 'MXR90' +"# Set the rotation of the instance 'input31' to 'MXR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Set the rotation of the instance to 'MXR90' +transform = inst.getTransform() +transform.setOrient('MXR90') +inst.setTransform(transform)",set the rotation of the instance 'input31' to 'MXR90' +"# Change the rotation of the instance 'wire2741' to 'R0' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('wire2741') + +# Change the rotation of the instance to 'R0' +inst.setOrient('R0')",change the rotation of the instance 'wire2741' to 'R0' +"# Change the rotation of the instance 'wire2741' to 'R0' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('wire2741') + +# Change the rotation of the instance to 'R0' +transform = inst.getTransform() +transform.setOrient('R0') +inst.setTransform(transform)",change the rotation of the instance 'wire2741' to 'R0' +"# Change the rotation of the instance 'wire2741' to 'R0' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('wire2741') + +# Change the rotation of the instance to 'R0' +inst.setOrient('R0')",Change the rotation of the instance 'wire2741' to 'R0' +"# Change the rotation of the instance 'wire2741' to 'R0' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('wire2741') + +# Change the rotation of the instance to 'R0' +transform = inst.getTransform() +transform.setOrient('R0') +inst.setTransform(transform)",Change the rotation of the instance 'wire2741' to 'R0' +"# Change the rotation of the instance 'max_cap2482' to 'R90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('max_cap2482') + +# Change the rotation of the instance to 'R90' +inst.setOrient('R90')",Change the rotation of the instance 'max_cap2482' to 'R90' +"# Change the rotation of the instance 'max_cap2482' to 'R90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('max_cap2482') + +# Change the rotation of the instance to 'R90' +transform = inst.getTransform() +transform.setOrient('R90') +inst.setTransform(transform)",Change the rotation of the instance 'max_cap2482' to 'R90' +"# Change the rotation of the instance 'super40' to 'R90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('super40') + +# Change the rotation of the instance to 'R90' +inst.setOrient('R90')",Change the rotation of the instance 'super40' to 'R90' +"# Change the rotation of the instance 'super40' to 'R90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('super40') + +# Change the rotation of the instance to 'R90' +transform = inst.getTransform() +transform.setOrient('R90') +inst.setTransform(transform)",Change the rotation of the instance 'super40' to 'R90' +"# Change the rotation of the instance '118_i[0]' to 'R180' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('118_i[0]') + +# Change the rotation of the instance to 'R180' +inst.setOrient('R180')",Change the rotation of the instance '118_i[0]' to 'R180' +"# Change the rotation of the instance '118_i[0]' to 'R180' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('118_i[0]') + +# Change the rotation of the instance to 'R180' +transform = inst.getTransform() +transform.setOrient('R180') +inst.setTransform(transform)",Change the rotation of the instance '118_i[0]' to 'R180' +"# Change the rotation of the instance 'super40' to 'R180' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('super40') + +# Change the rotation of the instance to 'R180' +inst.setOrient('R180')",Change the rotation of the instance 'super40' to 'R180' +"# Change the rotation of the instance 'super40' to 'R180' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('super40') + +# Change the rotation of the instance to 'R180' +transform = inst.getTransform() +transform.setOrient('R180') +inst.setTransform(transform)",Change the rotation of the instance 'super40' to 'R180' +"# Change the rotation of the instance 'icache_1/_21661_' to 'R270' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Change the rotation of the instance to 'R270' +inst.setOrient('R270')",Change the rotation of the instance 'icache_1/_21661_' to 'R270' +"# Change the rotation of the instance 'icache_1/_21661_' to 'R270' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Change the rotation of the instance to 'R270' +transform = inst.getTransform() +transform.setOrient('R270') +inst.setTransform(transform)",Change the rotation of the instance 'icache_1/_21661_' to 'R270' +"# Change the rotation of the instance 'input31' to 'R270' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Change the rotation of the instance to 'R270' +inst.setOrient('R270')",Change the rotation of the instance 'input31' to 'R270' +"# Change the rotation of the instance 'input31' to 'R270' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Change the rotation of the instance to 'R270' +transform = inst.getTransform() +transform.setOrient('R270') +inst.setTransform(transform)",Change the rotation of the instance 'input31' to 'R270' +"# Change the rotation of the instance 'icache_1/_21661_' to 'MY' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Change the rotation of the instance to 'MY' +inst.setOrient('MY')",Change the rotation of the instance 'icache_1/_21661_' to 'MY' +"# Change the rotation of the instance 'icache_1/_21661_' to 'MY' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Change the rotation of the instance to 'MY' +transform = inst.getTransform() +transform.setOrient('MY') +inst.setTransform(transform)",Change the rotation of the instance 'icache_1/_21661_' to 'MY' +"# Change the rotation of the instance 'input31' to 'MY' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Change the rotation of the instance to 'MY' +inst.setOrient('MY')",Change the rotation of the instance 'input31' to 'MY' +"# Change the rotation of the instance 'input31' to 'MY' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Change the rotation of the instance to 'MY' +transform = inst.getTransform() +transform.setOrient('MY') +inst.setTransform(transform)",Change the rotation of the instance 'input31' to 'MY' +"# Change the rotation of the instance 'icache_1/_21661_' to 'MYR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Change the rotation of the instance to 'MYR90' +inst.setOrient('MYR90')",Change the rotation of the instance 'icache_1/_21661_' to 'MYR90' +"# Change the rotation of the instance 'icache_1/_21661_' to 'MYR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Change the rotation of the instance to 'MYR90' +transform = inst.getTransform() +transform.setOrient('MYR90') +inst.setTransform(transform)",Change the rotation of the instance 'icache_1/_21661_' to 'MYR90' +"# Change the rotation of the instance 'input31' to 'MYR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Change the rotation of the instance to 'MYR90' +inst.setOrient('MYR90')",Change the rotation of the instance 'input31' to 'MYR90' +"# Change the rotation of the instance 'input31' to 'MYR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Change the rotation of the instance to 'MYR90' +transform = inst.getTransform() +transform.setOrient('MYR90') +inst.setTransform(transform)",Change the rotation of the instance 'input31' to 'MYR90' +"# Change the rotation of the instance 'icache_1/_21661_' to 'MX' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Change the rotation of the instance to 'MX' +inst.setOrient('MX')",Change the rotation of the instance 'icache_1/_21661_' to 'MX' +"# Change the rotation of the instance 'icache_1/_21661_' to 'MX' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Change the rotation of the instance to 'MX' +transform = inst.getTransform() +transform.setOrient('MX') +inst.setTransform(transform)",Change the rotation of the instance 'icache_1/_21661_' to 'MX' +"# Change the rotation of the instance 'input31' to 'MX' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Change the rotation of the instance to 'MX' +inst.setOrient('MX')",Change the rotation of the instance 'input31' to 'MX' +"# Change the rotation of the instance 'input31' to 'MX' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Change the rotation of the instance to 'MX' +transform = inst.getTransform() +transform.setOrient('MX') +inst.setTransform(transform)",Change the rotation of the instance 'input31' to 'MX' +"# Change the rotation of the instance 'icache_1/_21661_' to 'MXR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Change the rotation of the instance to 'MXR90' +inst.setOrient('MXR90')",Change the rotation of the instance 'icache_1/_21661_' to 'MXR90' +"# Change the rotation of the instance 'icache_1/_21661_' to 'MXR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('icache_1/_21661_') + +# Change the rotation of the instance to 'MXR90' +transform = inst.getTransform() +transform.setOrient('MXR90') +inst.setTransform(transform)",Change the rotation of the instance 'icache_1/_21661_' to 'MXR90' +"# Change the rotation of the instance 'input31' to 'MXR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Change the rotation of the instance to 'MXR90' +inst.setOrient('MXR90')",Change the rotation of the instance 'input31' to 'MXR90' +"# Change the rotation of the instance 'input31' to 'MXR90' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input31') + +# Change the rotation of the instance to 'MXR90' +transform = inst.getTransform() +transform.setOrient('MXR90') +inst.setTransform(transform)",Change the rotation of the instance 'input31' to 'MXR90' +"# Horizontally flip the rotation of the instances whose library cell types are 'OR2_X3' + +#define flipping function +def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'OR2_X3' + if inst.getMaster().getName() == 'OR2_X3': + # Horizontally flip the rotation of the instance + orient = inst.getOrient() + orient = flipX(orient) + inst.setOrient(orient)",Horizontally flip the rotation of the instances whose library cell types are 'OR2_X3' +"# Horizontally flip the rotation of the instances whose library cell types are 'OR2_X3' + +#define flipping function +def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'OR2_X3' + if inst.getMaster().getName() == 'OR2_X3': + # Horizontally flip the rotation of the instance + orient = inst.getTransform().getOrient() + orient = flipX(orient) + inst.setOrient(orient)",Horizontally flip the rotation of the instances whose library cell types are 'OR2_X3' +"# Horizontally flip the rotation of the instances whose library cell types are 'OR2_X3' + +#define flipping function +def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'OR2_X3' + if inst.getMaster().getName() == 'OR2_X3': + # Horizontally flip the rotation of the instance + transform = inst.getTransform() + orient = transform.getOrient() + orient = flipX(orient) + transform.setOrient(orient) + inst.setTransform(transform)",Horizontally flip the rotation of the instances whose library cell types are 'OR2_X3' +"# Vertically flip the rotation of the instances whose library cell types are 'OR2_X3' + +#define flipping function +def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'OR2_X3' + if inst.getMaster().getName() == 'OR2_X3': + # Vertically flip the rotation of the instance + transform = inst.getTransform() + orient = transform.getOrient() + orient = flipY(orient) + transform.setOrient(orient) + inst.setTransform(transform) +",Vertically flip the rotation of the instances whose library cell types are 'OR2_X3' +"# Vertically flip the rotation of the instances whose library cell types are 'OR2_X3' + +#define flipping function +def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'OR2_X3' + if inst.getMaster().getName() == 'OR2_X3': + # Vertically flip the rotation of the instance + transform = inst.getTransform() + orient = transform.getOrient() + orient = flipY(orient) + inst.setOrient(orient)",Vertically flip the rotation of the instances whose library cell types are 'OR2_X3' +"# Vertically flip the rotation of the instances whose library cell types are 'OR2_X3' + +#define flipping function +def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'OR2_X3' + if inst.getMaster().getName() == 'OR2_X3': + # Vertically flip the rotation of the instance + orient = inst.getOrient() + orient = flipY(orient) + inst.setOrient(orient)",Vertically flip the rotation of the instances whose library cell types are 'OR2_X3' +"# Horizontally flip the cells whose library cell types are 'OR2_X3' + +#define flipping function +def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270"" + +# Get the design block +block = design.getBlock() + +# Get all cells in the block +insts = block.getInsts() + +# Iterate through all cells in the block +for inst in insts: + # Check if the library cell type is 'OR2_X3' + if inst.getMaster().getName() == 'OR2_X3': + # Horizontally flip the rotation of the cell + orient = inst.getOrient() + orient = flipX(orient) + inst.setOrient(orient)",Horizontally flip the cells whose library cell types are 'OR2_X3' +"# Horizontally flip the cells whose library cell types are 'OR2_X3' + +#define flipping function +def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270"" + +# Get the design block +block = design.getBlock() + +# Get all cells in the block +insts = block.getInsts() + +# Iterate through all cells in the block +for inst in insts: + # Check if the library cell type is 'OR2_X3' + if inst.getMaster().getName() == 'OR2_X3': + # Horizontally flip the rotation of the cell + orient = inst.getTransform().getOrient() + orient = flipX(orient) + inst.setOrient(orient)",Horizontally flip the cells whose library cell types are 'OR2_X3' +"# Horizontally flip the cells whose library cell types are 'OR2_X3' + +#define flipping function +def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270"" + +# Get the design block +block = design.getBlock() + +# Get all cells in the block +insts = block.getInsts() + +# Iterate through all cells in the block +for inst in insts: + # Check if the library cell type is 'OR2_X3' + if inst.getMaster().getName() == 'OR2_X3': + # Horizontally flip the rotation of the cells\ + transform = inst.getTransform() + orient = transform.getOrient() + orient = flipX(orient) + transform.setOrient(orient) + inst.setTransform(transform)",Horizontally flip the cells whose library cell types are 'OR2_X3' +"# Vertically flip the cells whose library cell types are 'OR2_X3' + +#define flipping function +def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90"" + +# Get the design block +block = design.getBlock() + +# Get all cells in the block +insts = block.getInsts() + +# Iterate through all cells in the block +for inst in insts: + # Check if the library cell type is 'OR2_X3' + if inst.getMaster().getName() == 'OR2_X3': + # Vertically flip the rotation of the cell + transform = inst.getTransform() + orient = transform.getOrient() + orient = flipY(orient) + transform.setOrient(orient) + inst.setTransform(transform) +",Vertically flip the rotation of the instances whose library cell types are 'OR2_X3' +"# Vertically flip the cells whose library cell types are 'OR2_X3' + +#define flipping function +def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90"" + +# Get the design block +block = design.getBlock() + +# Get all cells in the block +insts = block.getInsts() + +# Iterate through all cells in the block +for inst in insts: + # Check if the library cell type is 'OR2_X3' + if inst.getMaster().getName() == 'OR2_X3': + # Vertically flip the rotation of the cell + transform = inst.getTransform() + orient = transform.getOrient() + orient = flipY(orient) + inst.setOrient(orient)",Vertically flip the cells whose library cell types are 'OR2_X3' +"# Vertically flip the cells whose library cell types are 'OR2_X3' + +#define flipping function +def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90"" + +# Get the design block +block = design.getBlock() + +# Get all cells in the block +insts = block.getInsts() + +# Iterate through all cells in the block +for inst in insts: + # Check if the library cell type is 'OR2_X3' + if inst.getMaster().getName() == 'OR2_X3': + # Vertically flip the rotation of the cell + orient = inst.getOrient() + orient = flipY(orient) + inst.setOrient(orient)",Vertically flip the cells whose library cell types are 'OR2_X3' +"# Invert the rotation and the location of instances with the library cell type 'AND2_X1'. + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the name of the library cell type is 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Invert the rotation and the location of the instance + transform = inst.getTransform() + transform.invert() + inst.setTransform(transform)",Invert the rotation and the location of instances with the library cell type 'AND2_X1' +"# Invert the rotation and the location of instances with the library cell type 'OR2_X2'. + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the name of the library cell type is 'OR2_X2' + if inst.getMaster().getName() == 'OR2_X2': + # Invert the rotation and the location of the instance + transform = inst.getTransform() + transform.invert() + inst.setTransform(transform)",Invert the rotation and the location of instances with the library cell type 'OR2_X2' +"# Invert the rotation and the location of cells with the library cell type 'NOR_X3' + +# Get the design block +block = design.getBlock() + +# Get all cells in the block +insts = block.getInsts() + +# Iterate through all cells in the block +for inst in insts: + # Check if the name of the library cell type is 'NOR_X3' + if inst.getMaster().getName() == 'NOR_X3': + # Invert the rotation and the location of the cell + transform = inst.getTransform() + transform.invert() + inst.setTransform(transform)",Invert the rotation and the location of cells with the library cell type 'NOR_X3' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input2' as mentioned in the prompt +inst = block.findInst('input2') +# Set the orientation of the instance as ""MX"" +inst.setOrient('MX')",Adjust the orientation of the instance 'input2' to 'MX'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input2' as mentioned in the prompt +inst = block.findInst('input2') +# Set the rotation of the instance as ""MX"" +inst.setOrient('MX')",Adjust the rotation of the instance 'input2' to 'MX'. +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Find the instance named ""split30"" +inst = block.findInst(""split30"") +# Define the new library cell name +new_mast_name = 'BUF_X4' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the new libarary cell + inst.swapMaster(new_mast) + return True +else: + return False",Upsize the instance split30 to BUF_X4 +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find the instance named ""split30"" +inst = block.findInst(""split30"") +# Define the new library cell name +new_mast_name = 'BUF_X1' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False",Downsize the instance split30 to BUF_X1 +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find the instance named ""_32937_"" +inst = block.findInst(""_32937_"") +# Define the new library cell name +new_mast_name = 'AND2_X3' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False",Scale up the size of the instance _32937_ to AND2_X3 +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find the instance named ""rebuffer_30"" +inst = block.findInst(""rebuffer_30"") +# Define the new library cell name +new_mast_name = 'BUF_X4' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False","Use BUF_X4 to replace the instance ""rebuffer_30""" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""rebuffer_30"" +inst = block.findInst(""rebuffer_30"") +# Define the name of the replacing library cell +new_mast_name = 'BUF_X3' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False","Use BUF_X3 to replace the cell ""rebuffer_30""" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""clkbuf_1_1__f_clk"" +inst = block.findInst(""clkbuf_1_1__f_clk"") +# Define the name of the replacing library cell +new_mast_name = 'CLKBUF_X2' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False","Use CLKBUF_X2 to replace the cell ""clkbuf_1_1__f_clk""" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""clkbuf_1_1__f_clk"" +inst = block.findInst(""clkbuf_1_1__f_clk"") +# Define the name of the replacing library cell +new_mast_name = 'clk_bufferx2' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False","Use clk_bufferx2 to replace the cell ""clkbuf_1_1__f_clk""" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""clkbuf_1_1__f_clk"" +inst = block.findInst(""clkbuf_1_1__f_clk"") +# Define the name of the replacing library cell +new_mast_name = 'clkbufferx2' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False","Use clkbufferx2 to replace the cell ""clkbuf_1_1__f_clk""" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""clkbuf_1_1__f_clk"" +inst = block.findInst(""clkbuf_1_1__f_clk"") +# Define the name of the replacing library cell +new_mast_name = 'CLK_BUF_X4' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False","Use CLK_BUF_X4 to replace the cell ""clkbuf_1_1__f_clk""" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find the instance named ""split30"" +inst = block.findInst(""split30"") +# Define the new library cell name +new_mast_name = 'BUF_X1' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False",Downsize the cell split30 using BUF_X1 +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find the instance named ""split33"" +inst = block.findInst(""split33"") +# Define the new library cell name +new_mast_name = 'BUF_X2' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False",Downsize the cell split33 using BUF_X2 +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Find the instance named ""input104"" +inst = block.findInst(""input104"") +# Define the new library cell name +new_mast_name = 'BUF_X3' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the new libarary cell + inst.swapMaster(new_mast) + return True +else: + return False",Upsize the instance input104 to BUF_X3 +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Find the instance named ""output_104"" +inst = block.findInst(""output_104"") +# Define the new library cell name +new_mast_name = 'OR2_X3' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the new libarary cell + inst.swapMaster(new_mast) + return True +else: + return False",Upsize the instance output_104 to OR2_X3 +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Find the instance named ""output_104"" +inst = block.findInst(""output_104"") +# Define the new library cell name +new_mast_name = 'NOR2_X3' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the new libarary cell + inst.swapMaster(new_mast) + return True +else: + return False",Upsize the instance output_104 to NOR2_X3 +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Find the instance named ""output_104"" +inst = block.findInst(""output_104"") +# Define the new library cell name +new_mast_name = 'NOR_2X3' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the new libarary cell + inst.swapMaster(new_mast) + return True +else: + return False",Upsize the instance output_104 to NOR_2X3 +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""msg_and_gate_118"" +inst = block.findInst(""msg_and_gate_118"") +# Define the name of the replacing library cell +new_mast_name = 'and_gate2_x9' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False","Replace the instance called ""msg_and_gate_118"" with the llibrary cell ""and_gate2_x9""" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""input_118"" +inst = block.findInst(""input_118"") +# Define the name of the replacing library cell +new_mast_name = 'NANDx3' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False","Replace the instance called ""input_118"" with the llibrary cell ""NANDx3""" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""input_118"" +inst = block.findInst(""input_118"") +# Define the name of the replacing library cell +new_mast_name = 'NANDx3' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast)","Replace the instance called ""input_118"" with the llibrary cell ""NANDx3""" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""msg_and_gate_118"" +inst = block.findInst(""msg_and_gate_118"") +# Define the name of the replacing library cell +new_mast_name = 'and_gate2_x9' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast)","Replace the instance called ""msg_and_gate_118"" with the llibrary cell ""and_gate2_x9""" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""msg_and_gate_118"" +inst = block.findInst(""msg_and_gate_118"") +# Define the name of the replacing library cell +new_mast_name = 'and_gate2_x9' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) +else: + print(""The library cell does not exist"")","Replace the instance called ""msg_and_gate_118"" with the llibrary cell ""and_gate2_x9""" +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Find the instance named ""input104"" +inst = block.findInst(""input104"") +# Define the new library cell name +new_mast_name = 'BUF_X3' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the new libarary cell + inst.swapMaster(new_mast) +else: + print(""The library cell does not exist"")",Upsize the instance input104 to BUF_X3. +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find the instance named ""_32937_"" +inst = block.findInst(""_32937_"") +# Define the new library cell name +new_mast_name = 'AND2_X3' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) +else: + print(""The library cell does not exist"")",Scale up the size of the instance _32937_ to AND2_X3. +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find the instance named ""_32937_"" +inst = block.findInst(""_32937_"") +# Define the new library cell name +new_mast_name = 'AND2_X3' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) +else: + print(""The library cell does not exist"")","How can I scale up the size of the instance ""_32937_"" using AND2_X3?" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""msg_and_gate_118"" +inst = block.findInst(""msg_and_gate_118"") +# Define the name of the replacing library cell +new_mast_name = 'and_gate2_x9' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) +else: + print(""The library cell does not exist"")","How can I replace the instance ""msg_and_gate_118"" with the llibrary cell ""and_gate2_x9""?" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""msg_and_gate_118"" +inst = block.findInst(""msg_and_gate_118"") +# Define the name of the replacing library cell +new_mast_name = 'and_gate2_x9' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) +else: + print(""The library cell does not exist"")","Can you give me the script to replace the instance ""msg_and_gate_118"" with the llibrary cell ""and_gate2_x9""?" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""msg_and_gate_118"" +inst = block.findInst(""msg_and_gate_118"") +# Define the name of the replacing library cell +new_mast_name = 'AND2_X6' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) +else: + print(""The library cell does not exist"")","Can you give me the script to replace the instance ""msg_and_gate_118"" with the master ""AND2_X6""?" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""clkbuf_1_1__f_clk"" +inst = block.findInst(""clkbuf_1_1__f_clk"") +# Define the name of the replacing library cell +new_mast_name = 'clkbufferx2' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False","How can I use clkbufferx2 to replace the cell ""clkbuf_1_1__f_clk""?" +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""clkbuf_1_1__f_clk"" +inst = block.findInst(""clkbuf_1_1__f_clk"") +# Define the name of the replacing library cell +new_mast_name = 'clkbufferx2' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False","Show me how I can use clkbufferx2 to replace the cell ""clkbuf_1_1__f_clk""." +"# Get the design block +block = ord.get_db_block() +# Get the openroad database +db = ord.get_db() +# Find cell ""_input_221_"" +inst = block.findInst(""_input_221_"") +# Define the name of the replacing library cell +new_mast_name = 'XOR3x5 ' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the required library cell + inst.swapMaster(new_mast) + return True +else: + return False","How can I use XOR3x5 to replace the cell ""_input_221_""?" +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Find the instance named ""output_104"" +inst = block.findInst(""output_104"") +# Define the new library cell name +new_mast_name = 'NOR_2X3' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the new libarary cell + inst.swapMaster(new_mast) + return True +else: + return False",Show me how I can upsize the instance output_104 to NOR_2X3. +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Find the instance named ""output_118 "" +inst = block.findInst(""output_118 "") +# Define the new library cell name +new_mast_name = 'NOR_2X6' +# Check if the required library cell exists in the database +if db.findMaster(new_mast_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_mast_name) + # Swap the instance's library cell with the new libarary cell + inst.swapMaster(new_mast) + return True +else: + return False",Show me how I can upsize the instance output_118 using NOR_2X6. +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Get all nets +nets = block.getNets() +# Find the POWER and GROUND nets +for net in nets: + if net.getSigType() == 'POWER': + power_net = net + elif net.getSigType() == 'GROUND': + ground_net = net +# Find the source instance named ""_350_"" +source_inst = block.findInst(""_350_"") +# Find the pin connected to net ""_036_"" +for pin in source_inst.getITerms(): + if pin.getNet() is not None: + if pin.getNet().getName() == '_036_': + source_pin = pin + source_net = pin.getNet() + break +# Create a new net +new_net = odb.dbNet_create(block,'new_net_1') +# Find the master instance named 'BUF_X2' +mast = db.findMaster('BUF_X2') +# Create a new instance named 'new_inst_1' using the 'BUF_X2' master +new_inst = odb.dbInst_create(block,mast,'new_inst_1') +# Disconnect the source pin +source_pin.disconnect() +# Connect the source pin to the new net +source_pin.connect(new_net) +# Connect the pins of the new instance +for pin in new_inst.getITerms(): + if pin.isInputSignal(): + pin.connect(new_net) + elif pin.isOutputSignal(): + pin.connect(source_net) + elif pin.getSigType() == 'POWER': + pin.connect(power_net) + elif pin.getSigType() == 'GROUND': + pin.connect(ground_net) +","Add a new instance 'new_inst_1' using buffer cell BUF_X2 after the instance '_350_' on the net '_036', and connect the instances using a new net 'new_net_1'" +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Get all nets +nets = block.getNets() +# Find the POWER and GROUND nets +for net in nets: + if net.getSigType() == 'POWER': + power_net = net + elif net.getSigType() == 'GROUND': + ground_net = net +# Find the source instance named ""_350_"" +source_inst = block.findInst(""_350_"") +# Find the pin connected to net ""_036_"" +for pin in source_inst.getITerms(): + if pin.getNet() is not None: + if pin.getNet().getName() == '_036_': + source_pin = pin + source_net = pin.getNet() + break +# Create a new net +new_net = odb.dbNet_create(block,'new_net_1') +# Find the master instance named 'bufferx3' +mast = db.findMaster('bufferx3') +# Create a new instance named 'new_inst_1' using the 'bufferx3' master +new_inst = odb.dbInst_create(block,mast,'new_inst_1') +# Disconnect the source pin +source_pin.disconnect() +# Connect the source pin to the new net +source_pin.connect(new_net) +# Connect the pins of the new instance +for pin in new_inst.getITerms(): + if pin.isInputSignal(): + pin.connect(new_net) + elif pin.isOutputSignal(): + pin.connect(source_net) + elif pin.getSigType() == 'POWER': + pin.connect(power_net) + elif pin.getSigType() == 'GROUND': + pin.connect(ground_net) +","Add a new instance 'new_inst_1' using buffer cell bufferx3 after the instance '_350_' on the net '_036', and connect the instances using a new net 'new_net_1'" +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Get all nets +nets = block.getNets() +# Find the POWER and GROUND nets +for net in nets: + if net.getSigType() == 'POWER': + power_net = net + elif net.getSigType() == 'GROUND': + ground_net = net +# Find the source instance named ""_350_"" +source_inst = block.findInst(""_350_"") +# Find the pin connected to net ""_036_"" +for pin in source_inst.getITerms(): + if pin.getNet() is not None: + if pin.getNet().getName() == '_036_': + source_pin = pin + source_net = pin.getNet() + break +# Create a new net +new_net = odb.dbNet_create(block,'new_net_1') +# Find the master instance named 'bufferx3' +mast = db.findMaster('bufferx3') +# Create a new instance named 'new_inst_1' using the 'bufferx3' master +new_inst = odb.dbInst_create(block,mast,'new_inst_1') +# Disconnect the source pin +source_pin.disconnect() +# Connect the source pin to the new net +source_pin.connect(new_net) +# Connect the pins of the new instance +for pin in new_inst.getITerms(): + if pin.isInputSignal(): + pin.connect(new_net) + elif pin.isOutputSignal(): + pin.connect(source_net) + elif pin.getSigType() == 'POWER': + pin.connect(power_net) + elif pin.getSigType() == 'GROUND': + pin.connect(ground_net) +","Add a new instance 'new_inst_1' using library cell bufferx3 after the instance '_350_' on the net '_036', and connect the instances using a new net 'new_net_1'" +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Get all nets +nets = block.getNets() +# Find the POWER and GROUND nets +for net in nets: + if net.getSigType() == 'POWER': + power_net = net + elif net.getSigType() == 'GROUND': + ground_net = net +# Find the source instance named ""_350_"" +source_inst = block.findInst(""_350_"") +# Find the pin connected to net ""_036_"" +for pin in source_inst.getITerms(): + if pin.getNet() is not None: + if pin.getNet().getName() == '_036_': + source_pin = pin + source_net = pin.getNet() + break +# Create a new net +new_net = odb.dbNet_create(block,'new_net_1') +# Find the master instance named 'bufferx3' +mast = db.findMaster('bufferx3') +# Create a new instance named 'new_inst_1' using the 'bufferx3' master +new_inst = odb.dbInst_create(block,mast,'new_inst_1') +# Disconnect the source pin +source_pin.disconnect() +# Connect the source pin to the new net +source_pin.connect(new_net) +# Connect the pins of the new instance +for pin in new_inst.getITerms(): + if pin.isInputSignal(): + pin.connect(new_net) + elif pin.isOutputSignal(): + pin.connect(source_net) + elif pin.getSigType() == 'POWER': + pin.connect(power_net) + elif pin.getSigType() == 'GROUND': + pin.connect(ground_net) +","How can I add a new instance 'new_inst_1' using library cell bufferx3 after the instance '_350_' on the net '_036', and connect the instances using a new net 'new_net_1'?" +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Get all nets +nets = block.getNets() +# Find the POWER and GROUND nets +for net in nets: + if net.getSigType() == 'POWER': + power_net = net + elif net.getSigType() == 'GROUND': + ground_net = net +# Find the source instance named ""_350_"" +source_inst = block.findInst(""_350_"") +# Find the pin connected to net ""_036_"" +for pin in source_inst.getITerms(): + if pin.getNet() is not None: + if pin.getNet().getName() == '_036_': + source_pin = pin + source_net = pin.getNet() + break +# Create a new net +new_net = odb.dbNet_create(block,'new_net_1') +# Find the master instance named 'bufferx3' +mast = db.findMaster('bufferx3') +# Create a new instance named 'new_inst_1' using the 'bufferx3' master +new_inst = odb.dbInst_create(block,mast,'new_inst_1') +# Disconnect the source pin +source_pin.disconnect() +# Connect the source pin to the new net +source_pin.connect(new_net) +# Connect the pins of the new instance +for pin in new_inst.getITerms(): + if pin.isInputSignal(): + pin.connect(new_net) + elif pin.isOutputSignal(): + pin.connect(source_net) + elif pin.getSigType() == 'POWER': + pin.connect(power_net) + elif pin.getSigType() == 'GROUND': + pin.connect(ground_net) +","Add a new instance 'new_inst_1' using library cell bufferx3 after the instance '_350_' on the net '_036', and connect the instances using a new net 'new_net_1' " +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""req_val"" +port = block.findBTerm('req_val') +# Find the net with name ""req_msg[17]"" +net = block.findNet('req_msg[17]') +# Connect the port and the net +port.connect(net)",Connect the port named 'req_val' and net named 'req_msg[17]' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""req_val"" +port = block.findBTerm('req_val') +# Disconnect the port +port.disconnect()",Disconnect the port named 'req_val' from the nets it is connected to +"from openroad import Design, Tech + +tech = Tech() +# Make sure to read all required files +design = Design(tech) +# Get PDNGen module +pdngen_obj = design.getPdnGen() +# Find the VDD net +VDD_net = design.getBlock().findNet(""VDD"") +# Rip up the VDD grids +pdn_obj.ripUp(VDD_net)",Rip up the VDD grids +"from openroad import Design, Tech + +tech = Tech() +# Make sure to read all required files +design = Design(tech) +# Get PDNGen module +pdngen_obj = design.getPdnGen() +# Find the VDD net +VSS_net = design.getBlock().findNet(""VSS"") +# Rip up the VSS grids +pdn_obj.ripUp(VSS_net)",Rip up the VSS grids +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input2' as mentioned in the prompt +inst = block.findInst('input2') +#Set the location to coordinates (22500, 33459) +inst.setLocation(22500,33459)","Set the location of the instance named 'input2' to coordinates (22500, 33459)." +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""resp_msg[15]"" +port = block.findBTerm('resp_msg[15]') +# Find the net with name ""req_msg[10]"" +net = block.findNet('req_msg[10]') +# Connect the port and the net +port.connect(net)",Establish a connection between the port 'resp_msg[15]' and the net named 'req_msg[10]'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""resp1_3_msg[15]"" +port = block.findBTerm('resp1_3_msg[15]') +# Find the net with name ""req_msg[10]"" +net = block.findNet('req_msg[10]') +# Connect the port and the net +port.connect(net)",Establish a connection between the port 'resp1_3_msg[15]' and the net named 'req_msg[10]'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""resp1_3_msg[12]"" +port = block.findBTerm('resp1_3_msg[12]') +# Find the net with name ""req_msg[12]"" +net = block.findNet('req_msg[12]') +# Connect the port and the net +port.connect(net)",Establish a connection between the port 'resp1_3_msg[12]' and the net named 'req_msg[12]'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""resp_msg[15]"" +port = block.findBTerm('resp_msg[15]') +# Disconnect the port +port.disconnect()",Remove the connection of the port 'resp_msg[15]' from its associated nets. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""sram_132[15]"" +port = block.findBTerm('sram_132[15]') +# Disconnect the port +port.disconnect()",Remove the connection of the port 'sram_132[15]' from its associated nets. +"from openroad import Design, Tech + +tech = Tech() +# Make sure to read all required files +design = Design(tech) +# Get PDNGen module +pdngen_obj = design.getPdnGen() +# Find the VDD net +VDD_net = design.getBlock().findNet(""VDD"") +# Rip up the VDD grids +pdn_obj.ripUp(VDD_net)",How can I rip up the existing VDD power grid so I can reconstruct PDN? +"from openroad import Design, Tech + +tech = Tech() +# Make sure to read all required files +design = Design(tech) +# Get PDNGen module +pdngen_obj = design.getPdnGen() +# Find the VDD net +VDD_net = design.getBlock().findNet(""VDD"") +# Rip up the VDD grids +pdn_obj.ripUp(VDD_net)",How can I remove the existing VDD power grid? +"from openroad import Design, Tech + +tech = Tech() +# Make sure to read all required files +design = Design(tech) +# Get PDNGen module +pdngen_obj = design.getPdnGen() +# Find the VSS net +VDD_net = design.getBlock().findNet(""VSS"") +# Rip up the VSS grids +pdn_obj.ripUp(VSS_net)",How can I rip up the existing VSS power grid so I can reconstruct PDN? +"from openroad import Design, Tech + +tech = Tech() +# Make sure to read all required files +design = Design(tech) +# Get PDNGen module +pdngen_obj = design.getPdnGen() +# Find the VSS net +VDD_net = design.getBlock().findNet(""VSS"") +# Rip up the VSS grids +pdn_obj.ripUp(VSS_net)",How can I remove the existing VSS power grid? +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input3' as mentioned in the prompt +inst = block.findInst('input3') +#Set the placing location of the instance to (18000,26999) +inst.setLocation(18000,26999)","Set the location of the instance 'input3' to (18000,26999) in OpenDB unit" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""input1"" as mentioned in the prompt +inst = block.findInst('input1') +#Set the location of the instance with X Coordinate 22500 and Y Coordinate as 33459 +inst.setLocation(22500,33459)","Set the location of the instance 'input1' to (22500,33459) in OpenDB unit" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input3' as mentioned in the prompt +inst = block.findInst('input3') +#Set the placing location of the instance to (2.5,1.8) in micron +inst.setLocation(int(2.5*block.getDbUnitsPerMicron()),int(1.8*block.getDbUnitsPerMicron()))","Set the location of the instance 'input3' to (2.5, 1.8) in micron" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'split30' as mentioned in the prompt +inst = block.findInst('split30') +#Set the placing location of the instance to (10.81, 3.6) in micron +inst.setLocation(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","Set the location of the instance 'split30' to (10.81, 3.6) in micron" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'split30' as mentioned in the prompt +inst = block.findInst('split30') +#Set the placing location of the instance to (10.81, 3.6) in micron +inst.setLocation(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","Move the instance 'split30' to (10.81, 3.6) in micron" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name '_11991_' as mentioned in the prompt +inst = block.findInst('_11991_') +#Set the placing location of the instance to (10.81, 3.6) in micron +inst.setLocation(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","How can I move the instance '_11991_' to (10.81, 3.6) in micron?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name '_11991_' as mentioned in the prompt +inst = block.findInst('_11991_') +#Set the placing location of the instance to (20, 3.6) in micron +inst.setLocation(int(20*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","How can I move the instance '_11991_' to (20, 3.6) in micron?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""input1"" as mentioned in the prompt +inst = block.findInst('input1') +#Set the location of the instance with X Coordinate 22500 and Y Coordinate as 33459 +inst.setLocation(22500,33459)","How can I set the location of the instance 'input1' to (22500,33459) in OpenDB unit?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""input1"" as mentioned in the prompt +inst = block.findInst('input1') +#Set the location of the instance with X Coordinate 22500 and Y Coordinate as 33459 +inst.setLocation(22500,33459)","Show me how I can set the location of the instance 'input1' to (22500,33459) in OpenDB unit" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name '_11991_' as mentioned in the prompt +inst = block.findInst('_11991_') +#Set the placing location of the instance to (10.81, 9.18) in micron +inst.setLocation(int(10.81*block.getDbUnitsPerMicron()),int(9.18*block.getDbUnitsPerMicron()))","Show me how I can move the instance '_11991_' to (10.81, 9.18) in micron" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name '_temp_inst_' as mentioned in the prompt +inst = block.findInst('_temp_inst_') +#Set the placing location of the instance to (3.18, 9.18) in micron +inst.setLocation(int(3.18*block.getDbUnitsPerMicron()),int(9.18*block.getDbUnitsPerMicron()))","Show me how I can move the instance '_temp_inst_' to (3.18, 9.18) in micron" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'and_no_123' as mentioned in the prompt +inst = block.findInst('and_no_123') +#Set the placing location of the instance to (4.14, 41.4) in micron +inst.setLocation(int(4.14*block.getDbUnitsPerMicron()),int(41.4*block.getDbUnitsPerMicron()))","Show me how I can move the instance 'and_no_123' to (4.14, 41.4) in micron" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'and_no_123' as mentioned in the prompt +inst = block.findInst('and_no_123') +#Set the placing location of the instance to (4.14, 41.4) in um +inst.setLocation(int(4.14*block.getDbUnitsPerMicron()),int(41.4*block.getDbUnitsPerMicron()))","Show me how I can move the instance 'and_no_123' to (4.14, 41.4) in um" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'split30' as mentioned in the prompt +inst = block.findInst('split30') +#Set the placing location of the instance to (10.81, 3.6) in um +inst.setLocation(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","Set the location of the instance 'split30' to (10.81, 3.6) in um" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'split30' as mentioned in the prompt +inst = block.findInst('split30') +#Set the placing location of the instance to (10.81, 3.6) in um +inst.setLocation(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","Move the instance 'split30' to (10.81, 3.6) in um" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name '_11991_' as mentioned in the prompt +inst = block.findInst('_11991_') +#Set the placing location of the instance to (10.81, 3.6) in um +inst.setLocation(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","How can I move the instance '_11991_' to (10.81, 3.6) in um?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name '_11991_' as mentioned in the prompt +inst = block.findInst('_11991_') +#Set the placing location of the instance to (20, 3.6) in um +inst.setLocation(int(20*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","How can I move the instance '_11991_' to (20, 3.6) in um?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'split30' as mentioned in the prompt +inst = block.findInst('split30') +#Set the placing location of the instance to (10.81, 3.6) in micrometer +inst.setLocation(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","Set the location of the instance 'split30' to (10.81, 3.6) in micrometer" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'split30' as mentioned in the prompt +inst = block.findInst('split30') +#Set the placing location of the instance to (10.81, 3.6) in micrometer +inst.setLocation(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","Move the instance 'split30' to (10.81, 3.6) in micrometer" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name '_11991_' as mentioned in the prompt +inst = block.findInst('_11991_') +#Set the placing location of the instance to (10.81, 3.6) in micrometer +inst.setLocation(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","How can I move the instance '_11991_' to (10.81, 3.6) in micrometer?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name '_11991_' as mentioned in the prompt +inst = block.findInst('_11991_') +#Set the placing location of the instance to (20, 3.6) in micrometer +inst.setLocation(int(20*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","How can I move the instance '_11991_' to (20, 3.6) in micrometer?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input3' as mentioned in the prompt +inst = block.findInst('input3') +#Set the placing location of the instance to (18000,26999) +inst.setOrigin(18000,26999)","Set the location of the instance 'input3' to (18000,26999) in OpenDB unit" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""input1"" as mentioned in the prompt +inst = block.findInst('input1') +#Set the location of the instance with X Coordinate 22500 and Y Coordinate as 33459 +inst.setOrigin(22500,33459)","Set the location of the instance 'input1' to (22500,33459) in OpenDB unit" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input3' as mentioned in the prompt +inst = block.findInst('input3') +#Set the placing location of the instance to (2.5,1.8) in micron +inst.setOrigin(int(2.5*block.getDbUnitsPerMicron()),int(1.8*block.getDbUnitsPerMicron()))","Set the location of the instance 'input3' to (2.5, 1.8) in micron" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'split30' as mentioned in the prompt +inst = block.findInst('split30') +#Set the placing location of the instance to (10.81, 3.6) in micron +inst.setOrigin(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","Set the location of the instance 'split30' to (10.81, 3.6) in micron" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""input1"" as mentioned in the prompt +inst = block.findInst('input1') +#Set the location of the instance with X Coordinate 22500 and Y Coordinate as 33459 +inst.setOrigin(22500,33459)","Show me how I can set the location of the instance 'input1' to (22500,33459) in OpenDB unit" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name '_11991_' as mentioned in the prompt +inst = block.findInst('_11991_') +#Set the placing location of the instance to (10.81, 9.18) in micron +inst.setOrigin(int(10.81*block.getDbUnitsPerMicron()),int(9.18*block.getDbUnitsPerMicron()))","Show me how I can move the instance '_11991_' to (10.81, 9.18) in micron" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name '_temp_inst_' as mentioned in the prompt +inst = block.findInst('_temp_inst_') +#Set the placing location of the instance to (3.18, 9.18) in micron +inst.setOrigin(int(3.18*block.getDbUnitsPerMicron()),int(9.18*block.getDbUnitsPerMicron()))","Show me how I can move the instance '_temp_inst_' to (3.18, 9.18) in micron" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'and_no_123' as mentioned in the prompt +inst = block.findInst('and_no_123') +#Set the placing location of the instance to (4.14, 41.4) in micron +inst.setOrigin(int(4.14*block.getDbUnitsPerMicron()),int(41.4*block.getDbUnitsPerMicron()))","Show me how I can move the instance 'and_no_123' to (4.14, 41.4) in micron" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'and_no_123' as mentioned in the prompt +inst = block.findInst('and_no_123') +#Set the placing location of the instance to (4.14, 41.4) in um +inst.setOrigin(int(4.14*block.getDbUnitsPerMicron()),int(41.4*block.getDbUnitsPerMicron()))","Show me how I can move the instance 'and_no_123' to (4.14, 41.4) in um" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'split30' as mentioned in the prompt +inst = block.findInst('split30') +#Set the placing location of the instance to (10.81, 3.6) in um +inst.setOrigin(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","Set the location of the instance 'split30' to (10.81, 3.6) in um" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'split30' as mentioned in the prompt +inst = block.findInst('split30') +#Set the placing location of the instance to (10.81, 3.6) in micrometer +inst.setOrigin(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","Set the location of the instance 'split30' to (10.81, 3.6) in micrometer" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'split30' as mentioned in the prompt +inst = block.findInst('split30') +#Set the placing location of the instance to (10.81, 3.6) in micrometer +inst.setOrigin(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","Move the instance 'split30' to (10.81, 3.6) in micrometer" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name '_11991_' as mentioned in the prompt +inst = block.findInst('_11991_') +#Set the placing location of the instance to (10.81, 3.6) in micrometer +inst.setOrigin(int(10.81*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","How can I move the instance '_11991_' to (10.81, 3.6) in micrometer?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name '_11991_' as mentioned in the prompt +inst = block.findInst('_11991_') +#Set the placing location of the instance to (20, 3.6) in micrometer +inst.setOrigin(int(20*block.getDbUnitsPerMicron()),int(3.6*block.getDbUnitsPerMicron()))","How can I move the instance '_11991_' to (20, 3.6) in micrometer?" diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/DB/circuit_modification.xlsx b/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/DB/circuit_modification.xlsx new file mode 100644 index 0000000..f218ac1 Binary files /dev/null and b/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/DB/circuit_modification.xlsx differ diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/DB/query.csv b/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/DB/query.csv new file mode 100644 index 0000000..0d6505b --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/DB/query.csv @@ -0,0 +1,6351 @@ +code,prompt +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() + +# Retrieve all instances present in the design block +insts = block.getInsts() + +# Initialize an empty list to store the names of library cell type for each instance +masters_list = [] + +# Iterate over each instance in the design block +for inst in insts: + # Retrieve the library cell type of the current instance + master_type = inst.getMaster() + # Get the name of the library cell type + master_type_name = master_type.getName() + # Append the name of the library cell type to the list + masters_list.append(master_type_name) + +# Return the list containing the names of library cell type for every instance +return masters_list",Give me the names of library cell type of every instance +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Retrieve all instances present in the design block +insts = block.getInsts() +loc = [] +for inst in insts: + # Append the location of the instance to the list + loc.append(inst.getLocation()) +return loc",Give methe location of every instance in the design and return it in a list called loc. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Retrieve all instances present in the design block +insts = block.getInsts() +placement_status_with_name = {} +# Iterate over each instance in the design block +for inst in insts: + # Get the name of particular instance + name = inst.getName() + # Get the placement status of the instance + status = inst.getPlacementStatus() + # Add the respective instance name and its status + placement_status_with_name[name] = status +return placement_status_with_name",Get the name of every instance with its placement status as a dictionary +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Retrieve all instances present in the design block +insts = block.getInsts() +placed_instances = [] +# Iterate over each instance in the design block +for inst in insts: + # Check if this instance is placed + if inst.isPlaced()==True: + # Append the instance name to the array + placed_instances.append(inst.getName()) +return placed_instances",Get the names of every instance which are placed and return a list of names +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Retrieve all instances present in the design block +insts = block.getInsts() +level_of_instance = {} +# Iterate over each instance in the design block +for inst in insts: + # Retrieve the name of the instance and its level, then store it in the dictionary + level_of_instance[inst.getName()] = inst.getLevel() +return level_of_instance",Get the level of all instances with the instance name as a dictionary. Key of the dictionary is name of the instance and value is the level of the instance +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Retrieve all instances present in the design block +insts = block.getInsts() +const_name= [] +# Iterate over each instance in the design block +for inst in insts: + # Append the Const name of the instance + const_name.append(inst.getConstName()) +return const_name",Get all the Constant names of the instances and return as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +print("" name | net_type | pin&wire_capacitance"") +# Retrieve all nets present in the design block +nets = block.getNets() +# Iterate over each net in the design block +for net in nets: + # Get the net capacitance + pin_and_wire_cap = timing.getNetCap(net, corner, timing.Max) + # Get the name of the net + net_name = net.getName() + # Get the signal Type of the net + net_type = net.getSigType() + print(f""{net_name:<12}| {net_type:<9}| {pin_and_wire_cap:19.4e}"")","Write a code to Print the name of the net, its net type, and the wire capacitance of all the nets" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Retrieve all instances present in the design block +insts = block.getInsts() +print("" name | rise_arrival_time | fall_arrival_time | rise_slack | fall_slack | slew"") +# Iterate over each instance in the design block +for inst in insts: + # Get the pins associated with the instance + inst_ITerms = inst.getITerms() + # Iterate through all the pins + for pin in inst_ITerms: + # Check if the pin is in supply + if design.isInSupply(pin): + continue + # Get the pin name + pin_name = design.getITermName(pin) + # Get the pin rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Get the pin fall arrival time + pin_fall_arr = timing.getPinArrival(pin, timing.Fall) + # Get the pin rise slack + pin_rise_slack = timing.getPinSlack(pin, timing.Fall, timing.Max) + # Get the pin fall slack + pin_fall_slack = timing.getPinSlack(pin, timing.Rise, timing.Max) + # Get the pin slew + pin_slew = timing.getPinSlew(pin) + print(f""{pin_name:<12} | {pin_rise_arr:17.4e} | {pin_fall_arr:17.4e} | {pin_rise_slack:10.4e} | {pin_fall_slack:10.4e} | {pin_slew:6.4e}"") ","Write a code to print all the pin names, rising arrival time, fall arrival time, rise stack, fall stack and slew of all the pins" +"#Get the OpenROAD database +db = ord.get_db() +#Get the number of library cell types +return db.getNumberOfMasters()",Get the number of library cells in the library +"# Get the design block +block = ord.get_db_block() +# Get the die area of the design +area = block.getDieArea() +# Get the width and height of the die area +dx = area.dx() +dy = area.dy() +# Calculate the die area +die_area = dx*dy +# Return the calculated die area +return die_area",Get the die area +"# Get the design block +block = ord.get_db_block() +# Get the core area of the design +area = block.getCoreArea() +# Get the width and height of the core area +dx = area.dx() +dy = area.dy() +# Calculate the core area +core_area = dx*dy +# Return the calculated core area +return core_area",Get the core area +"# Get the design block +block = ord.get_db_block() +# Report global connection of the design +global_connection = block.reportGlobalConnect() +# Return the global connections +return global_connection",Report all the global connection rules +"# Get the design block +block = ord.get_db_block() +# Initialize a variable to store the total number of pins +total_pins = 0 +# Get instances +insts = block.getInsts() + +# Iterate over instances +for inst in insts: + # Add the number of pins of the instance to the total + total_pins += len(inst.getITerms()) + +# Return the total number of pins +return total_pins",Get the total number of pins +"# Get the design block +block = ord.get_db_block() +# Get instances +insts = block.getInsts() +# Initialize a list to store instance names +inst_name =[] + +# Iterate over instances and append their names to the list +for inst in insts: + inst_name.append(inst.getName()) + +# Return the list of instance names +return inst_name",List all the instances name +"# Get the design block +block = ord.get_db_block() +# Initialize a list to store clock nets +clock_nets = [] +# Get all nets +nets = block.getNets() +# Iterate over nets +for net in nets: + # Check if the net is a CLOCK net + if net.getSigType() == 'CLOCK': + # Check if the net is a CLOCK net + clock_nets.append(net) +# Check if CLOCK nets exist +if len(clock_nets) > 0: + return True +else: + return False",Check if the design has any clock nets +"# Get the design block +block = ord.get_db_block() +# Initialize variables to count power and ground nets +power_nets = 0 +ground_nets = 0 +# Get all nets +nets = block.getNets() +# Iterate over nets +for net in nets: + # Check if the net is a POWER net + if net.getSigType() == 'POWER': + power_nets += 1 + # Check if the net is a GROUND net + elif net.getSigType() == 'GROUND': + ground_nets += 1 +# Return the counts of power and ground nets +return power_nets, ground_nets",Get the total number of power and ground nets +"# Get the chip associated with the design's block. + +# Retrieve the design block +block = design.getBlock() + +# Get the chip associated with the design block. +chip = block.getChip() + +# Return the chip associated with the design block. +return chip ",Give me the chip of a given block +"# Get the nets in a given block + +# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# Return the list of nets +return nets",Get all nets in a given block +design.getBlock().getName(),Get the name of the design block +"# Get the logic ports for a given block + +# Get the design block +block = design.getBlock() + +# Get all logic ports +logic_ports = block.getLogicPorts() + +# Return the list of logic ports +return logic_ports",Get the logic ports for a given block +"# Get the location of all instances +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Iterate through all instances +for inst in insts: + # Print the instance name and its location + print(inst.getName(), ""Location:"", inst.getLocation())",Get the location of all instances +"# Check if the instance 'FILLER_0_0_1' is placed or not + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Name of the instance to check placement status +inst_name = 'FILLER_0_0_1' + +# Iterate through all instances +for inst in insts: + # Check if the instance name matches the target instance + if inst.getName() == inst_name: + # Return the placement status of the instance + return inst.isPlaced()",Check if the instance 'FILLER_0_0_1' placed or not +"# Get the children of 'FILLER_0_0_1' instance + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Name of the instance whose children are to be retrieved +inst_name = 'FILLER_0_0_1' + +# Initialize a list to store children instances +children = [] + +# Iterate through all instances +for inst in insts: + # Check if the instance name matches the target instance + if inst.getName() == inst_name: + # Get the children instances of the target instance + children = inst.getChildren() + break + +# Return the list of children instances +return children",Get the children of 'FILLER_0_0_1' instance +"# Get the design block +block = ord.get_db_block() +# Get all nets +nets = block.getNets() +# Initialize variables to track the net with the maximum capacitance +max_cap_net = None +max_cap = float('-inf') +# Iterate over nets +for net in nets: + # Get the total capacitance of the net + cap = timing.getNetCap(net, corner, timing.Max) + # Check if the capacitance of the current net is greater than the maximum capacitance found so far + if cap > max_cap: + # Update the maximum capacitance and the corresponding net + max_cap = cap + max_cap_net = net +# Return the net with the maximum capacitance +return max_cap_net.getName()",Identify the nets with the highest capacitance +"# Get the design block +block = ord.get_db_block() +# Find the instance named ""split30"" +return block.findInst(""split30"")",Find instance split30 +"# Get the design block +block = ord.get_db_block() +# Get all nets +nets = block.getNets() +# Define the fanout threshold +gt_fanout = 10 +# Initialize a list to store nets with fanout greater than the threshold +net_fanout = [] +# Iterate over nets +for net in nets: + # Get the name of the net + net_name = net.getName() + # Initialize a list to store output pins + output_pins = [] + # Get all ITerms associated with the net + net_ITerms = net.getITerms() + # Iterate over ITerms + for net_ITerm in net_ITerms: + # Check if the ITerm represents an input signal + if (net_ITerm.isInputSignal()): + # Get the name of the pin + pin_name = design.getITermName(net_ITerm) + # Append the pin name to the list of output pins + output_pins.append(pin_name) + # Check if the number of output pins exceeds the fanout threshold + if len(output_pins) > gt_fanout: + # Append the net name and its fanout to the list + net_fanout.append([net_name, len(output_pins)]) +# Return the list of nets with fanout greater than the threshold +return net_fanout",Give me a list of nets with a fanout greater than 10 +"# Get the design block +block = ord.get_db_block() +# Get all nets +nets = block.getNets() +# Initialize variables to store maximum fanout and its corresponding net +max_fanout = 0 +# Lists to store net names and their corresponding fanouts +net_fanout_list = [] +net_name_list = [] +# Iterate over nets +for net in nets: + # Get the name of the net + net_name = net.getName() + # Initialize a list to store output pins + output_pins = [] + # Get all ITerms associated with the net + net_ITerms = net.getITerms() + # Iterate over ITerms + for net_ITerm in net_ITerms: + # Check if the ITerm represents an input signal + if (net_ITerm.isInputSignal()): + # Get the name of the pin + pin_name = design.getITermName(net_ITerm) + # Append the pin name to the list of output pins + output_pins.append(pin_name) + # Append the net name and its fanout to the respective lists + net_name_list.append(net_name) + net_fanout_list.append(len(output_pins)) +# Find the maximum fanout +max_fanout = max(net_fanout_list) +# Find the index of the net with the maximum fanout +max_fanout_index = net_fanout_list.index(max_fanout) +# Get the name of the net with the maximum fanout +max_fanout_net = net_name_list[max_fanout_index] +# Return the net with the maximum fanout +return max_fanout_net",Give me a list of nets with the maximum fanout +"# Get the design block +block = ord.get_db_block() +# Get all instances +insts = block.getInsts() +# Initialize a list to store unique name of library cell types +masters_list = [] +# Iterate over instances +for inst in insts: + # Get the master associated with the instance + mast = inst.getMaster() + mast_name = mast.getName() + # Check if the library cell name is not already in the list + if mast_name not in masters_list: + # Append the library cell name to the list + masters_list.append(mast_name) +# Return the list of unique library cell names +return masters_list",List all the library cells used +"# Get the design block +block = ord.get_db_block() +# Get the total number of connections (nets) +total_connections = len(block.getNets()) +# Return the total number of connections +return total_connections",Get the total number of connections (nets) +"# Get all the input/output nets for a given block + +# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# Initialize a list to store input/output nets +io_nets = [] + +# Iterate through all nets +for net in nets: + # Check if the net is an input/output net + if net.isIO(): + # If it's an input/output net, add it to the list + io_nets.append(net) + +# Return the list of input/output nets +return io_nets",get all the input output nets for a given block +"# Get a list of all the output pins + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a list to store output pins +output_pins_list = [] + +# Iterate through all instances +for inst in insts: + # Get all input pins (ITerms) of the instance + pins = inst.getITerms() + # Iterate through all input pins + for pin in pins: + # Check if the pin is an output signal + if pin.isOutputSignal(): + # If it's an output signal, add it to the list + output_pins_list.append(pin) + +# Return the list of output pins +return output_pins_list",get a list of all the output pins +"#Give me all nets connecting to the instance '_411_' + +# Instance name to search for +inst_name = ""_411_"" + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a variable to store the nets of the instance +nets = None + +# Iterate through all instances +for inst in insts: + # Check if the instance name matches the target instance + if inst.getName() == inst_name: + # Get all pins (ITerms) of the instance and extract their associated nets + nets = [pin.getNet() for pin in inst.getITerms()] + break + +# Return the nets of the instance +return nets +",Give me all nets connecting to the instance '_411_' +"# Get weights of all the instances + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a dictionary to store weights of instances +inst_weight_dict = {} + +# Iterate through all instances +for inst in insts: + # Get the instance name + name = inst.getName() + # Check if the instance name is not already in the dictionary + if name not in inst_weight_dict: + # If not, add the instance name and its weight to the dictionary + inst_weight_dict[name] = inst.getWeight() + +# Return the dictionary containing weights of instances +return inst_weight_dict",get Weights of all the instances +"# Get length and width of the Bounding Box of the instance '_411_' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('_411_') + +# Get the length and width of the Bounding Box of the instance +length = inst.getBBox().getLength() +width = inst.getBBox().getWidth() + +# Return the length and width +return (length, width) +",get length and width of the bounding Box of the instance ''_411_' +"# Get source type of all the instances on level 1 + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a dictionary to store source types of instances on level 1 +lvl1_inst_src_type = {} + +# Iterate through all instances +for inst in insts: + # Check if the instance is on level 1 + if inst.getLevel() == 1: + # Add the instance name and its source type to the dictionary + lvl1_inst_src_type[inst.getName()] = inst.getSourceType() + +# Return the dictionary containing source types of instances on level 1 +return lvl1_inst_src_type +",get source type of all the instance on level 1 +"# Set the placement status of the instance '_411_' to 'UNPLACED' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('_411_') + +# Set the placement status of the instance to 'UNPLACED' +inst.setPlacementStatus('UNPLACED') +",set the placement Status of the instance '_411_' to 'UNPLACED' +"# Get all the blockages + +# Get the design block +block = design.getBlock() + +# Return all blockages +return block.getBlockages()",get all the blockages +"# Reset the tapcell in the design + +# Get the tapcell in the design +tapcell = design.getTapcell() + +# Reset the tapcell +tapcell.reset()",reset the tapcell in the design +"# Retrieve the capacitor-coupled segments + +# Get the design block +block = design.getBlock() + +# Return the capacitor-coupled segments +return block.getCCSegs()",retrieve the capacitor-coupled segments +"# Get the sites of rows + +# Get the design block +block = design.getBlock() + +# Get all rows +rows = block.getRows() + +# Initialize a dictionary to store row names and their corresponding sites +row_site_dict = {} + +# Iterate through all rows +for row in rows: + # Add the row name and its site to the dictionary + row_site_dict[row.getName()] = row.getSite() + +# Return the dictionary containing row names and their sites +return row_site_dict",get the sites of rows +"# Get the height and width of the sites of each row + +# Get the design block +block = design.getBlock() + +# Get all rows +rows = block.getRows() + +# Initialize a dictionary to store row names and their corresponding site dimensions +row_site_dict = {} + +# Iterate through all rows +for row in rows: + # Check if the row has a site + if row.getSite(): + # Add the row name and its site dimensions to the dictionary + row_site_dict[row.getName()] = [row.getSite().getHeight(), row.getSite().getWidth()] + +# Return the dictionary containing row names and their site dimensions +return row_site_dict",get the height and width of the sites of each row +"# Get the location, orientation, direction, and spacing of rows + +# Get the design block +block = design.getBlock() + +# Get all rows +rows = block.getRows() + +# Iterate through all rows +for i in range(len(rows)): + row = rows[i] + # Print row information + print(""Row"", i, row.getName()) + print(""Location:"", row.getOrigin()) + print(""Rotation:"", row.getOrient()) + print(""Direction:"", row.getDirection()) + print(""Block spacing:"", row.getSpacing()) +","get the location, rotation, direction and spacing of rows" +"# Get the rows with hybrid sites + +# Get the design block +block = design.getBlock() + +# Get all rows +rows = block.getRows() + +# Initialize a list to store rows with hybrid sites +hybrid_row_site = [] + +# Iterate through all rows +for i in range(len(rows)): + row = rows[i] + site = row.getSite() + # Check if the site is hybrid + if site.isHybrid(): + # Append the row and its site to the list + hybrid_row_site.append((row, site)) + +# Return the list of rows with hybrid sites +return hybrid_row_site",get the rows with hybrid sites +"# Get all the instances and their halos + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a dictionary to store instances and their halos +inst_halos = {} + +# Iterate through all instances +for inst in insts: + # Add the instance name and its halo to the dictionary + inst_halos[inst.getName()] = inst.getHalo() + +# Return the dictionary containing instances and their halos +return inst_halos",get all the instances and there halos +"# Get the instances and their respective regions + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a dictionary to store instances and their regions +inst_regions = {} + +# Iterate through all instances +for inst in insts: + # Add the instance name and its region to the dictionary + inst_regions[inst.getName()] = inst.getRegion() + +# Return the dictionary containing instances and their regions +return inst_regions",get the instances and their respective regions +"# Get all the do not touch instances and set do not touch to true if false for instances + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a dictionary to store do not touch instances +do_not_touch_elements = {} + +# Iterate through all instances +for inst in insts: + # Check if the instance is marked as do not touch + if inst.isDoNotTouch(): + # Add the instance to the dictionary + do_not_touch_elements[inst.getName()] = inst + else: + # Set do not touch to true for instances marked as false + inst.setDoNotTouch(True) + +# Return the dictionary containing do not touch instances +return do_not_touch_elements",get the all the do not touch instance and set do not touch to true if false for instances +"# Set the EcoCreate and EcoDestroy for instance '_411_' to true + +# Get the design block +block = design.getBlock() + +# Find the instance with name '_411_' +inst = block.findInst('_411_') + +# Set EcoCreate and EcoDestroy to true +inst.setEcoCreate(True) +inst.setEcoDestroy(True) + +# Return the modified instance +return inst",set the EcoCreate and EcoDestroy for instance '_411_' true +"# Mark the first output nets of the instances '_411_' and 'input1' + +# Get the design block +block = design.getBlock() + +# Find the instances '_411_' and 'input1' +inst1 = block.findInst('_411_') +inst2 = block.findInst('input1') + +# Mark the first output net of instance '_411_' +inst1.getFirstOutput().getNet().setMark(True) + +# Mark the first output net of instance 'input1' +inst2.getFirstOutput().getNet().setMark(True) +",mark the first output nets of the instances '_411_' and 'input1' +"# Get the nets that are disconnected from RC network + +# Get the design block +block = design.getBlock() + +# Get all the nets +nets = block.getNets() + +# Initialize a list to store RC disconnected nets +rc_disconnected_nets = [] + +# Iterate through all the nets +for net in nets: + # Check if the net is RC disconnected + if net.isRCDisconnected(): + # Add the net to the list + rc_disconnected_nets.append(net) + +# Return the list of RC disconnected nets +return rc_disconnected_nets",Get the nets that are disconnected from RC network +"# Disconnect the nets of the instance 'input1' from the RC network + +# Get the design block +block = design.getBlock() + +# Find the instance with name 'input1' +inst = block.findInst('input1') + +# Get the pins of the instance +pins = inst.getITerms() + +# Iterate through the pins +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + if net: + # Set the RC disconnected flag for the net + net.setRCDisconnected(True) +",Disconnect the nets of the instance 'input1' from the RC network +"# Get the points of the placement bounding box of the library cell of the instance '_411_' + +# Get the design block +block = design.getBlock() + +# Find the instance with name '_411_' +inst = block.findInst('_411_') + +# Get the library cell associated with the instance +master = inst.getMaster() + +# Get the placement bounding box of the library cell +placement_boundary = master.getPlacementBoundary() + +# Return the points of the placement bounding box +return placement_boundary.getPoints() +",get the points of the placement bounding box of the library cell of the instance '_411_' +"# Clear user flags of instance '_411_' + +# Get the design block +block = design.getBlock() + +# Find the instance with name '_411_' +inst = block.findInst('_411_') + +# Clear user flags 1, 2, and 3 of the instance +inst.clearUserFlag1() +inst.clearUserFlag2() +inst.clearUserFlag3()",clear user flags of instance '_411_' +"# Check if the instance '_411_' is marked as an end cap cell. + +# Get the design block +block = design.getBlock() + +# Find the instance with name '_411_' +inst = block.findInst('_411_') + +# Check if the instance is marked as an end cap +return inst.isEndCap()",Check if the instance '_411_' is marked as an end cap cell. +"# Map nets to the wires + +# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# Initialize a dictionary to store net-wire mappings +net_wire_dict = {} + +# Iterate through all nets +for net in nets: + # Get the name of the net + net_name = net.getName() + + # If the net name is not already in the dictionary, initialize an empty list + if net_name not in net_wire_dict: + net_wire_dict[net_name] = [] + + # Append the wire connected to the net to the list in the dictionary + net_wire_dict[net_name].append(net.getWire()) + +# Return the net-wire dictionary +return net_wire_dict",map nets to the wires +"# Get the MTerms of the master cell of the instance '_411_' + +# Get the design block +block = design.getBlock() + +# Find the instance with name '_411_' +inst = block.findInst('_411_') + +# Get the MTerms of the master cell +mterms = inst.getMaster().getMTerms() + +# Return the MTerms +return mterms",get the MTerms of the master cell of the instance '_411_' +"# Get the IoType of the pins of the instance '_411_' + +# Get the design block +block = design.getBlock() + +# Find the instance with name '_411_' +inst = block.findInst('_411_') + +# Get the MTerms of the master cell +mterms = inst.getMaster().getMTerms() + +# Initialize a dictionary to store IoTypes +iotype_dict = {} + +# Iterate through all MTerms +for term in mterms: + # Store the IoType of each term in the dictionary + iotype_dict[term.getName()] = term.getIoType() + +# Return the dictionary containing IoTypes +return iotype_dict",get the IoType of the pins of the instance '_411_' +"block = design.getBlock() +insts = block.getInsts() +inst_list = [] +for inst in insts: + if not inst.getMaster().isCore(): + inst_list.append(inst) +return inst_list",get the instances whose masters are not of type CORE +"# Get the number of masks of each layer + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers +layers = tech.getLayers() + +# Initialize a dictionary to store the number of masks for each layer +num_masks = {} + +# Iterate through all layers +for layer in layers: + # Store the number of masks for each layer + num_masks[layer.getName()] = layer.getNumMasks() + +# Return the dictionary containing the number of masks for each layer +return num_masks",get the number of masks of each layer +"# Get the clearance measure + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Return the clearance measure +return tech.getClearanceMeasure()",get the measure system +"# Check LEF USEMINSPACING is set or not + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Return whether UseMinSpacingObs is set in the technology +return tech.getUseMinSpacingObs()",Check LEF USEMINSPACING is set or not +"# Get the layers if they are set as isRectOnly + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers +layers = tech.getLayers() + +# Initialize a list to store layers are set as RectOnly +rect_layers = [] + +# Iterate through all layers +for layer in layers: + # Check if the layer is set as RectOnly + if layer.isRectOnly(): + # Append the rectangle-only layer to the list + rect_layers.append(layer) + +# Return the list of rectangle-only layers +return rect_layers",Get the layers if they are set as isRectOnly +"# Get the alias of all the layers + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers +layers = tech.getLayers() + +# Initialize a dictionary to store the Alias of each layer +layer_alias = {} + +# Iterate through all layers +for layer in layers: + # Store the Alias of each layer + layer_alias[layer.getName()] = layer.getAlias() + +# Return the dictionary containing the Alias of all layers +return layer_alias",Get the alias of all the layers +"# Set the alias of the layers by the name convention ''layer i"" where i is the index of the layer + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers +layers = tech.getLayers() + +# Initialize a dictionary to store the Alias of each layer +layer_alias = {} + +# Iterate through all layers +for layer in layers: + # Construct the Alias using the layer index + alias = ""Layer "" + str(layer.getNumber()) + + # Set the Alias of the layer + layer.setAlias(alias) + + # Store the Alias of the layer in the dictionary + layer_alias[layer.getName()] = alias + +# Return the dictionary containing the updated Alias of layers +return layer_alias +","Set the Alias of the layers by the name convention ''layer i"" where i is the index of the layer" +"# Get LEF version + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Return the LEF version of the technology +return tech.getLefVersion()",Get LEF version +"# Get LEF version as a string + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Return the LEF version of the technology as a string +return tech.getLefVersionStr()",Get LEF version as a string +"# Get the resistance of all the layers + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers +layers = tech.getLayers() + +# Initialize a dictionary to store the resistance of each layer +layer_resistance = {} + +# Iterate through all layers +for layer in layers: + # Get the resistance of the layer and store it in the dictionary + layer_resistance[layer.getName()] = layer.getResistance() + +# Return the dictionary containing the resistance of each layer +return layer_resistance",Get the resistance of all the layers +"# Get edge capacitance of all the layers + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers +layers = tech.getLayers() + +# Initialize a dictionary to store the edge capacitance of each layer +layer_edge_capacitance = {} + +# Iterate through all layers +for layer in layers: + # Get the edge capacitance of the layer and store it in the dictionary + layer_edge_capacitance[layer.getName()] = layer.getEdgeCapacitance() + +# Return the dictionary containing the edge capacitance of each layer +return layer_edge_capacitance",get edge capacitance of all the layers +"# Get the upper and lower layer of the layer 'metal5' + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Find the layer 'metal5' +layer = tech.findLayer('metal5') + +# Return the upper and lower layer of 'metal5' +return (layer.getUpperLayer(), layer.getLowerLayer())",get the upper and lower layer of the layer 'metal5' +"# Check if instance '_411_' is buffer and if it is an End Cap cell +block = design.getBlock() + +# Find the instance '_411_' +inst = block.findInst('_411_') + +# Get the master of the instance +master = inst.getMaster() + +# Check if the design is buffer for the master and if the master is End Cap +return design.isBuffer(master) and master.isEndCap()",Check if instance '_411_' is buffer and if it is an End Cap cell +"# Get the instances whose masters are of type sequential and make the master of instance '_411_' sequential + +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# List to store sequential instances +seq_insts = [] + +# Iterate through instances +for inst in insts: + # Get the master of the instance + master = inst.getMaster() + + # Check if the instance is '_411_' + if inst.getName() == '_411_': + # Make the master of instance '_411_' sequential + master.setSequential(True) + + # Check if the master is of type sequential + if master.isSequential(): + seq_insts.append(inst) + +# Return sequential instances +return seq_insts +",Get the instances whose masters are of type sequential and make the master of instance '_411_' sequential +"# Check if the instance '411' has any pin set as clocked +block = design.getBlock() + +# Find the instance '411' +inst = block.findInst('_411_') + +# Get all pins of the instance +pins = inst.getITerms() + +# List to store pins set as clocked +clocked_ports = [] + +# Check if any pin is set as clocked +for pin in pins: + if pin.isClocked(): + clocked_ports.append(pin) + +# Return clocked ports +return clocked_ports",Check if the instance '411' has any pin set as clocked +"# Display the location, orient, direction, and spacing of each row +block = design.getBlock() +rows = block.getRows() + +# Print table header +print(""{:<15} {:<15} {:<15} {:<15}"".format(""Row Name"", ""Location"", ""Direction"", ""Spacing"")) + +# Print data in a table format +for row in rows: + location = str(row.getOrigin()) + direction = str(row.getDirection()) + spacing = str(row.getSpacing()) + + print(""{:<15} {:<15} {:<15} {:<15}"".format(row.getName(), location, direction, spacing))","Display the location, orient, direction, and spacing of each row" +"# Get the rows with 'MX' orient and get the instances and the first output pin of all instances +block = design.getBlock() +rows = block.getRows() +insts = block.getInsts() + +# Initialize dictionaries to store the results +output_pins_dict = {} +MX_rows = [] + +# Iterate over rows to find those with 'MX' rotation +for row in rows: + if row.getOrient() == ""MX"": + MX_rows.append(row) + +# Iterate over instances to find their output pins +for inst in insts: + if inst.getFirstOutput(): + output_pins_dict[inst.getName()] = inst.getFirstOutput() + +# Return the rows with 'MX' orientation and output pins of instances +return (MX_rows, output_pins_dict)",Get the rows with 'MX' rotation and get the instances and the first output pin of all instances. +"# Get all the instances and their halos and regions in a dictionary +block = design.getBlock() +insts = block.getInsts() +inst_halo_region_dict = {} + +# Iterate over instances to collect their halos and regions +for inst in insts: + inst_halo_region_dict[inst.getName()] = (inst.getHalo(), inst.getRegion()) + +# Return the dictionary with instance names as keys and a tuple of halo net and region as values +return inst_halo_region_dict",Get all the instances and their halos and regions in a dictionary with the instance name as the key and a tuple of halo net and region as value +"# Get the all the do not touch instances and set do not touch to true for pad instances +# Also, set the EcoCreate and EcoDestroy for instance '_411_' to True. + +block = design.getBlock() +insts = block.getInsts() +dnt_insts = [] + +# Iterate over instances to set 'Do Not Touch' for pads and collect do not touch instances +for inst in insts: + if inst.isPad(): + inst.setDoNotTouch(True) + + if inst.isDoNotTouch(): + dnt_insts.append(inst) + + #set the EcoCreate and EcoDestroy for instance '_411_' true. + if inst.getName() == ""_411_"": + inst.setEcoCreate(True) + inst.setEcoDestroy(True) + +return dnt_insts",Get the all the do not touch instances and set do not touch to true for pad instances and set the EcoCreate and EcoDestroy for instance '_411_' to True. +"# Mark the first output nets of the instances '411' and 'input1' and set RC disconnected to True for the nets. + +# Get the block of the design +block = design.getBlock() + +# Find the instances '411' and 'input1' +inst1 = block.findInst(""_411_"") +inst2 = block.findInst(""input1"") + +# Mark the first output nets of the instances and set RC disconnected true for the nets +inst1.getFirstOutput().getNet().setMark(True) +inst2.getFirstOutput().getNet().setMark(True) + +# Set RC disconnected true for the net of the first output of instance '411' +inst1.getFirstOutput().getNet().setRCDisconnected(True) + +# Set RC disconnected true for the net of the first output of instance 'input1' +inst2.getFirstOutput().getNet().setRCDisconnected(True)",Mark the first output nets of the instances '411' and 'input1' and set RC disconnected to True for the nets. +"# Set RC disconnected true for the nets of the instance 'input1' +block = design.getBlock() +inst = block.findInst('input1') +nets = [pin.getNet() for pin in inst.getITerms()] +for net in nets: + if net: + net.setRCDisconnected(True) + +# Get the upper-left, lower-left, lower-right, upper-right coordinates of the placement bounding box of the master cell of the instance '411' +placement_boundary = inst.getMaster().getPlacementBoundary() +coordinates = { + ""ul"": placement_boundary.ul(), + ""ll"": placement_boundary.ll(), + ""lr"": placement_boundary.lr(), + ""ur"": placement_boundary.ur() +} +return coordinates","Set the RC disconnected true for the nets of the instance 'input1' and get the upper-left, lower-left, lower-right, upper-right coordinates of the placement bounding box of the master cell of the instance '411'." +"# Get the current block of the design +block = design.getBlock() + +# Find the instance with the name '_411_' +inst = block.findInst('_411_') + +# Get the placement bounding box of the master cell of the instance +placement_boundary = inst.getMaster().getPlacementBoundary() + +# Get the points of the placement bounding box +points = placement_boundary.getPoints() + +# Clear user flag 1 of the instance +inst.clearUserFlag1() + +# Clear user flag 2 of the instance +inst.clearUserFlag2() + +# Clear user flag 3 of the instance +inst.clearUserFlag3() + +# Return the points of the placement bounding box +return points",Get the points of the placement bounding box of the master cell of the instance '411' and clear user flags of instance '_411_'. +"# Get the current block of the design +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a dictionary to store coordinates for each master cell +coordinates = {} + +# Iterate through each instance +for inst in insts: + # Get the master cell of the instance + master = inst.getMaster() + + # Get the placement bounding box of the master cell + placement_boundary = master.getPlacementBoundary() + + # Check if the master cell name is not already in the coordinates dictionary + if master.getName() not in coordinates: + # Store the center x, y coordinates, and minimum and maximum x, y coordinates in the dictionary + coordinates[master.getName()] = { + ""center"": [placement_boundary.xCenter(), placement_boundary.yCenter()], + ""min"": [placement_boundary.xMin(), placement_boundary.yMin()], + ""max"": [placement_boundary.xMax(), placement_boundary.yMax()] + } + +# Return the dictionary containing coordinates for each master cell +return coordinates","Get the center x, y and minimum and maximum x, y coordinates of the placement bounding box of the master cell of the all instance." +"# Get the current block of the design +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers defined in the technology +layers = tech.getLayers() + +# Dictionary to store spacing and number of masks for each layer +spacing_and_mask = {} + +# Iterate through each layer in the technology +for layer in layers: + # Store the spacing and number of masks for the current layer in the dictionary + spacing_and_mask[layer.getName()] = { + ""spacing"": layer.getSpacing(), + ""masks"": layer.getNumMasks() + } + +# Return the dictionary containing spacing and number of masks for each layer +return spacing_and_mask +",Get the spacing and the number of masks of each layer +"# Get the current block of the design +block = design.getBlock() + +# Get all blockages +blockages = block.getBlockages() + +# Get all nets +nets = block.getNets() + +# List to store RC disconnected nets +rc_disconnected_nets = [] + +# Iterate through each net +for net in nets: + # Check if the net is RC disconnected + if net.isRCDisconnected(): + # Append the net to the list of RC disconnected nets + rc_disconnected_nets.append(net) + +# Find the instance 'rebuffer7' +inst = block.findInst('rebuffer7') + +# Get the MTerms of the master cell of instance 'rebuffer7' +mterms = inst.getMaster().getMTerms() + +# Return a tuple containing blockages, RC disconnected nets, and MTerms +return (blockages, rc_disconnected_nets, mterms)","Get all the blockages and get the nets that are RC disconnected, followed by getting the MTerms of the master cell of the instance 'rebuffer7'." +"# Get the current block of the design +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers defined in the technology +layers = tech.getLayers() + +# Define the direction for the layers +direction = 'HORIZONTAL' + +# List to store horizontal tech layers and their capacitance +horizontal_layers = [] + +# Iterate through each layer in the technology +for layer in layers: + # Check if the layer direction is HORIZONTAL + if layer.getDirection() == direction: + # Append the layer and its capacitance to the list of horizontal layers + horizontal_layers.append((layer, layer.getCapacitance())) + +# Retrieve the clearance measure +clearance_measure = tech.getClearanceMeasure() + +# Get the setting of UseMinSpacingObs in the tech file +min_space_obs = tech.getUseMinSpacingObs() + +# Construct a dictionary containing horizontal layers, clearance measure, and minimum spacing obstacle +result = { + ""horizontal_layers"": horizontal_layers, + ""clearance_measure"": clearance_measure, + ""min_space_obs"": min_space_obs +} + +# Return the result dictionary +return result","Get the horizontal layers and their capacitance, then retrieve the clearance measure system and check if UseMinSpacingObs is set for this technology" +"# Get the current block of the design +block = design.getBlock() + +# Get rows and nets +rows = block.getRows() +nets = block.getNets() + +# Dictionary to store row information with row index as key +row_info_dict = {} + +# Dictionary to store sites of rows with row name as key +row_site_dict = {} + +# Dictionary to map nets to wires +net_wire_dict = {} + +# Iterate through each row +for i in range(len(rows)): + row = rows[i] + # Store row information in the row_info_dict + row_info_dict[i] = { + ""Location"": row.getOrigin(), + ""Rotation"": row.getOrient(), + ""Direction"": row.getDirection(), + ""Spacing"": row.getSpacing() + } + + # Store site of the row in the row_site_dict + row_site_dict[row.getName()] = row.getSite() + +# Iterate through each net +for net in nets: + # Map net name to its wire + net_wire_dict[net.getName()] = net.getWire() + +# Return a tuple containing row information, row sites, and net wire mappings +return (row_info_dict, row_site_dict, net_wire_dict)","Get the location, rotation, direction, and spacing of rows as a dictionary with row index as key and get the sites of rows, followed by a dictionary with nets as keys and their wires as values." +"# Get the tapcell and reset it +tap_cell = design.getTapcell() +tap_cell.reset() + +# Get the current block of the design +block = design.getBlock() + +# Find the instance '_411_' +inst = block.findInst('_411_') + +# Set the placement status of the instance to 'UNPLACED' +inst.setPlacementStatus('UNPLACED') + +# Retrieve the capacitor-coupled segments +cc_segs = block.getCCSegs() + +# Return the coupling capacitance segments +return cc_segs","reset the tapcell, set the placement Status of the instance '_411_' to 'UNPLACED' and retrieve the capacitor-coupled segments of the bock" +"# Get the tapcell in the design and reset it +tap_cell = design.getTapcell() +tap_cell.reset() + +# Get the current block of the design +block = design.getBlock() + +# Return all blockages +return block.getBlockages()",Get all the blockages and reset the tapcell in the design. +"# Get the current block of the design +block = design.getBlock() + +# Find the instance '_411_' and 'input1' +inst1 = block.findInst('_411_') +inst2 = block.findInst('input1') + +# Mark the first output nets of the instances '_411_' and 'input1' +inst1.getFirstOutput().getNet().setMark(True) +inst2.getFirstOutput().getNet().setMark(True) + +# Get the placement bounding box of the master cell of the instance '_411_' +placement_boundary = inst1.getMaster().getPlacementBoundary() + +# Extract coordinates of the placement bounding box +coordinates = { + ""ul"": placement_boundary.ul(), + ""ll"": placement_boundary.ll(), + ""lr"": placement_boundary.lr(), + ""ur"": placement_boundary.ur() +} + +# Return the coordinates +return coordinates","Mark the first output nets of the instances '_411_' and 'input1' and get the ul, ll, lr, ur coordinates of the placement bounding box of the master cell of the instance '_411_'." +"# Get the current block of the design +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Get the technology information +tech = block.getTech() + +# Get all layers defined in the technology +layers = tech.getLayers() + +# Define the direction for the layers +direction = 'HORIZONTAL' + +# List to store horizontal tech layers and their capacitance +horizontal_layers = [] + +# List to store instances whose masters are not of type CORE +non_core_master_insts = [] + +# Iterate through each instance +for inst in insts: + # Check if the master cell of the instance is not of type CORE + if not inst.getMaster().isCore(): + # Append the instance to the list of non-core master instances + non_core_master_insts.append(inst) + +# Iterate through each layer in the technology +for layer in layers: + # Check if the layer direction is HORIZONTAL + if layer.getDirection() == direction: + # Append the layer and its capacitance to the list of horizontal layers + horizontal_layers.append((layer, layer.getCapacitance())) + +# Reset the tapcell +tap_cell = design.getTapcell() +tap_cell.reset() + +# Return a tuple containing non-core master instances and horizontal layers +return (non_core_master_insts, horizontal_layers)","Get the instances whose masters are not of type CORE and get the horizontal tech layers and their capacitance, followed by resetting the tapcell" +"# Get the layersthat are set as RectOnly +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers +layers = tech.getLayers() + +# Initialize a list to store layers that are set as RectOnly +rect_layers_alias = [] + +# Iterate through all layers +for layer in layers: + # Check if the layer is set as RectOnly + if layer.isRectOnly(): + # Append the rectangle-only layer Aliases to the list + rect_layers_alias.append(layer.getAlias()) + +# Return the list of rectangle-only layers +return rect_layers_alias",Get the layers that are set as RectOnly and get their alias. +"# Get the current block of the design +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers defined in the technology +layers = tech.getLayers() + +# Dictionary to store resistance of all layers +layer_resistance = {} + +# Iterate through each layer to retrieve resistance +for layer in layers: + layer_resistance[layer.getName()] = layer.getResistance() + +# Dictionary to store edge capacitance of all layers +layer_edge_capacitance = {} + +# Iterate through each layer to retrieve edge capacitance +for layer in layers: + layer_edge_capacitance[layer.getName()] = layer.getEdgeCapacitance() + +# Combine resistance and edge capacitance dictionaries into a single result dictionary +result = { + ""edge_capacitance"": layer_edge_capacitance, + ""layer_resistance"": layer_resistance +} + +# Return the result dictionary +return result +",Get the resistance and edge capacitance of all the layers +"# Get the current block of the design +block = design.getBlock() + +# Find the port named 'req_val' +port = block.findBTerm('req_val') + +# Disconnect the port from the nets it is connected to +port.disconnect() + +# Set the port named 'req_val' to special +port.setSpecial() + +# Get the logic ports +logic_ports = block.getLogicPorts() + +# Return the logic ports +return logic_ports","Disconnect the port named 'req_val' from the nets it is connected to and set the port named 'req_val' to special, and return the logic ports" +"# Get the current block of the design +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# Get the wire_updated nets +updated_nets = block.getWireUpdatedNets(nets) + +# Get the technology information +tech = block.getTech() + +# Get all layers defined in the technology +layers = tech.getLayers() + +# List to store horizontal layers in the technology file +horizontal_layers = [] + +# Iterate through each layer in the technology +for layer in layers: + # Check if the layer direction is HORIZONTAL + if layer.getDirection() == 'HORIZONTAL': + # Append the horizontal layer to the list + horizontal_layers.append(layer) + +# Create a dictionary containing updated nets and horizontal layers +result = { + ""nets"": updated_nets, + ""layers"": horizontal_layers +} + +# Return the result dictionary +return result",Get all the wire_updated nets and get the horizontal layers +"# Get the current block of the design +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get the count of layers +layer_count = tech.getLayerCount() + +# Get the Routing Layer Count +routing_layer_count = tech.getRoutingLayerCount() + +# Get the logic ports +logic_ports = block.getLogicPorts() + +# Create a dictionary containing layer count, routing layer count, and logic ports +result = { + ""layer_count"": layer_count, + ""routing_layer_count"": routing_layer_count, + ""logic_ports"": logic_ports +} + +# Return the result dictionary +return result","Get the count of layers and get the routing layer count, along with the logic ports" +"# Get the current block of the design +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get the count of Manufacturing Grid +mfg = tech.getManufacturingGrid() + +# Find the net with name ""req_msg[13]"" +net = block.findNet(""req_msg[13]"") + +# Set the Capacitance Coupling Adjust Order of the net to 1 +net.setCcAdjustOrder(1) + +# Return the count of Manufacturing Grid +return mfg","Get the count of manufacturing grid and set the capacitance Coupling Adjust Order of the net with name ""req_msg[13]"" to 1." +"# Get the current block of the design +block = design.getBlock() + +# Find the net with name ""req_msg[11]"" +net1 = block.findNet(""req_msg[11]"") +# Set the Capacitance Coupling Adjust Factor to 1 +net1.setCcAdjustFactor(1) + +# Find the net with name ""req_msg[12]"" +net2 = block.findNet(""req_msg[12]"") +# Set the Capacitance Coupling Calibration Factor to 2 +net2.setCcCalibFactor(2)","Set the Capacitance Coupling Adjust Factor of the net with name ""req_msg[11]"" to 1 and set the Capacitance Coupling Calib Factor of the net with name ""req_msg[12]"" to 2." +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Retrieve all nets present in the design block +nets = block.getNets() +result = [] +# Iterate over each net in the design block +for net in nets: + # Check the signal type of the net + if net.getSigType() != 'POWER' and net.getSigType() != 'GROUND': + # Get the name of the net + net_name = net.getName() + # Get the total Capacitance of the net + net_cap = net.getTotalCapacitance() + # Get the total resistance of the net + net_res = net.getTotalResistance() + # Get the total coupling capacitance of the net + net_coupling = net.getTotalCouplingCap() + # Append the net name, net capacitance, net resistance and net coupling + result.append([net_name,net_cap,net_res,net_coupling]) +return result","Get the total capacitance, total resistance, Coupling Capacitance of all the nets except the nets that are connected to Ground and Power External Power Supply. Get them as list of lists, in which each list contains the net name, net capacitance, net resistance and net coupling." +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the pins (which are also called Iterms in OpenROAD) +pins = block.getITerms() +result = [] +#Iterate through all the pins +for pin in pins: + # Check if the pin is in clock + if design.isInClock(pin.getInst()): + # Append the pin to the result + result.append(pin) +return result",Get all the Pins which are in clock net as a list. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""input1"" as mentioned in the prompt +inst = block.findInst(""input1"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the X Minimum of the Bounding Box of the instance +xmin = BBox.xMin() +# Get the Y Minimum of the Bounding Box of the instance +ymin = BBox.yMin() +# Get the X Maximum of the Bounding Box of the instance +xmax = BBox.xMax() +# Get the Y Maximum of the Bounding Box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","Get the Bounding Box of an instance named ""input1"". Return a list of coordinates (Xmin, Ymin in one list and Xmax, Ymax in next list) " +"# Get all the libraries in the database +libs = db.getLibs() +d = {} +# Iterate through all the libraries files +for lib in libs: + # Get the library cells of the library + masterCells = lib.getMasters() + cells = [] + # Iterate through all the library cells + for master in masterCells: + # Append the library cell to the cells + cells.append(master) + d[lib.getName()] = cells +return d",Get all the library cells as a dictionary of list. Key of the dictionary is library name and the value is the list of all the library cells in the library file +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Retrieve all nets present in the design block +nets = block.getNets() +result = [] +# Iterate over each net in the design block +for net in nets: + # Get the Pins of the net + pins = net.getITerms() + # Check if the length of number of pins of net is Zero + if len(pins)==0: + # Append the net to the result + result.append(net) +return result",Get all the nets which are not connected to any pins and return them as list. +"# Get OpenDB +db = ord.get_db() +# Get all read libraries +libs = db.getLibs() +# Create a list to store the names +libcell_name_list = [] +# Iterate through all libraries +for lib in libs: + # Get all library cells in this library file + lib_masters = lib.getMasters() + # Iterate through all library cells + for master in lib_masters: + # Get the name of the library cell + libcell_name = master.getName() + # Add the name to the list + libcell_name_list.append(libcell_name) +return libcell_name_list",Get the name of every liberty cell +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +orientation = [] +# Retrieve all instances present in the design block +insts = block.getInsts() +# Iterate over each instance in the design block +for inst in insts: + # Append the get rotation of the instance + orientation.append([inst.getName(), inst.getOrient()]) +return orientation",Get the rotations of all instances as a list of lists +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input1' as mentioned in the prompt +inst = block.findInst('input1') +# Set the rotation of the instance as ""MX"" +inst.setOrient('MX')",Set the rotation of an instance 'input1' as 'MX' +"# Get the current block from the design +block = design.getBlock() + +# Retrieve the instance ""output53"" within the design +inst = block.findInst('output53') + +# Initialize a list to store the net of the output pin +output_nets = [] + +pins = inst.getITerms() + +# Iterate through each pin of the instance +for pin in pins: + # Check if the pin represents as an output signal + if pin.isOutputSignal(): + # Retrieve the net associated with this output pin + net = pin.getNet() + # If net is not None then append it to the output_net + if net: + output_nets.append(net) + +# Return the net connected to the output pin of the specified instance +return output_nets",get the nets of the output pins of the instance 'output53' +"# Get the width and height of the bounding box of instance '_411_' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('_411_') + +# Get the Bounding Box +bounding_box = inst.getBBox() + +# Get the DX and DY of the Bounding Box of the instance +return (bounding_box.getDX(), bounding_box.getDY())",Get the width and height of the bounding box of instance '_411_' +"# Set the level of all 'AND2_X1' gate instances in the design to 1 + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Iterate through all instances +for inst in insts: + # Check if the instance's master name contains 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Set the level of the instance to 1 + inst.setLevel(1, False)",set the level of all 'AND2_X1' gate instance in the design to 1 +"# Get the coordinates of the lower-left corner of the bounding box of the instances whose library cell type is 'AND2_X1' + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a dictionary to store the coordinates of the lower-left corner of the bounding box of the instances +inst_to_master_transform_offset = {} + +# Iterate through all instances +for inst in insts: + + # Check if the name of the library cell type is 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Add the instance name and the coordinates of the lower-left corner of the bounding box to the dictionary + inst_to_master_transform_offset[inst.getName()] = inst.getTransform().getOffset() + +# Return the dictionary containing the coordinates of the lower-left corner of the bounding box of the instances +return inst_to_master_transform_offset",Get the coordinates of the lower-left corner of the bounding box of the instances whose library cell type is 'AND2_X1' +"# Get the coordinates of the lower-left corner of the bounding box of the instances whose library cell type is 'AND2_X1' + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a dictionary to store the coordinates of the lower-left corner of the bounding box of the instances +inst_to_master_transform_offset = {} + +# Iterate through all instances +for inst in insts: + + # Check if the name of the library cell type is 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Add the instance name and the coordinates of the lower-left corner of the bounding box to the dictionary + inst_to_master_transform_offset[inst.getName()] = inst.getOrigin() + +# Return the dictionary containing the coordinates of the lower-left corner of the bounding box of the instances +return inst_to_master_transform_offset",Get the coordinates of the lower-left corner of the bounding box of the instances whose library cell type is 'AND2_X1' +"# Retrieve the orientation of instances that have 'AND2_X1' as their library cell type. + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a dictionary to store the orientation of instances +inst_to_master_transform_orient = {} + +# Iterate through all instances +for inst in insts: + # Check if the master name is 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Add the instance name and its rotation to the dictionary + inst_to_master_transform_orient[inst.getName()] = inst.getTransform().getOrient() + +# Return the dictionary containing the orientation of instances +return inst_to_master_transform_orient",Retrieve the rotation of instances that have 'AND2_X1' as their library cell type. +"# Retrieve the orientation of instances that have 'AND2_X1' as their library cell type. + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a dictionary to store the orientation of instances +inst_to_master_transform_orient = {} + +# Iterate through all instances +for inst in insts: + # Check if the master name is 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Add the instance name and its rotation to the dictionary + inst_to_master_transform_orient[inst.getName()] = inst.getOrient() + +# Return the dictionary containing the orientation of instances +return inst_to_master_transform_orient",Retrieve the rotation of instances that have 'AND2_X1' as their library cell type. +"# Get the first output pin of an instance and map it to the instance names as the value in the dictionary. + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a dictionary to store instances and their output pins +inst_outputs = {} + +# Iterate through all instances +for inst in insts: + # Add the instance name and its first output pin to the dictionary + inst_outputs[inst.getName()] = inst.getFirstOutput() + +# Return the dictionary containing instances and their output pins +return inst_outputs",Get the first output pin of an instance and map it to the instance names as the value in the dictionary. +"# Set the user-defined flags 1and 3 to true for instance '_411_' and return the instance + +# Get the design block +block = design.getBlock() + +# Find the instance with name '_411_' +inst = block.findInst('_411_') + +# Set the user-defined flags 1 and 3 to true +inst.setUserFlag1() +inst.setUserFlag3() + +# Return the modified instance +return inst",Set the user-defined flags 1and 3 to true for instance '_411_' and return the instance +"# Get the ul, ll, lr, ur coordinates of the placement bounding box of the master cell of the instance '_411_' + +# Get the design block +block = design.getBlock() + +# Find the instance with name '_411_' +inst = block.findInst('_411_') + +# Get the master cell associated with the instance +master = inst.getMaster() + +# Get the placement bounding box of the master cell +placement_boundary = master.getPlacementBoundary() + +# Get the coordinates of the placement bounding box + +# Upper Left placement bounding box +ul = placement_boundary.ul() + +# Lower Left Left placement bounding box +ll = placement_boundary.ll() + +# Lower Right placement bounding box +lr = placement_boundary.lr() + +# Upper Right placement bounding box +ur = placement_boundary.ur() + +# Return the coordinates +coordinates = [ul, ur, lr, ll] +return coordinates","get the upper left, upper right, lower left, lower right coordinates of the placement bounding box of the master cell of the instance '_411_'" +"# Get the current block of the design +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Find the instance '_411_' +inst = block.findInst('_411_') + +# Check if instance '_411_' is type ENDCAP or any of its subtypes +inst_is_endcap = inst.isEndCap() + +# Clear user-defined flags of instance '_411_' +inst.clearUserFlag1() +inst.clearUserFlag2() +inst.clearUserFlag3() + +# List to store instances having hierarchy and whose library cell name is ""AND2X_1"" and on level 1 +inst_list = [] + +# Iterate through each instance +for inst in insts: + # Check if the instance is hierarchical, its library cell name is ""AND2X_1"", and is level 1 + if inst.isHierarchical() and inst.getMaster().getName() == ""AND2X_1"" >= 0 and inst.getLevel() == 1: + # Append the instance to the list + inst_list.append(inst) + +# Return a tuple containing the status of the instance '_411_' to determine if it is of type ENDCAP or any of its subtypes, along with a list of instances that have a hierarchy. +return (inst_is_endcap, inst_list) +","Check if the instance '_411_' is type ENDCAP or any of its subtypes, and clear user-defined flags of instance '_411_', then get all the instances with hierarchicy and whose library cell is AND2X_1 and the instance is level 1." +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input1' as mentioned in the prompt +inst = block.findInst('input1') +# Get the corresponding design block of the instance +return inst.getBlock()","Given the instance name 'input1', get the design block this instance belongs to." +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the DB units per micron +return block.getDbUnitsPerMicron()",Convert 1 um to units used in this technology in OpenROAD +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the DEF units of this technology +return block.getDefUnits()",Get the DEF units of this technology. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the db rows +rows = block.getRows() +d = {} +# Iterate through all the rows +for row in rows: + # Get the name of the db row + name = row.getName() + # Get the spacing of the db row + spacing = row.getSpacing() + d[row] = [name, spacing] +return d","Get the rows with its name and spacing in a form of a dictionary. The key of the dictionary is the row object, the value is a list containing name and spacing of the row object" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the unit used in def file to 3000 as mentioned in the prompt +block.setDefUnits(3000)",Set the def units per micron to 3000 +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the modules +modules = block.getModules() +module_names = [] +# Iterate through all the modules +for module in modules: + # Append the names of the module + module_names.append(module.getName()) +return module_names",Get all the modules and return the names of modules as a list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input1' as mentioned in the prompt +inst = block.findInst(""inpu1"") +inst.setUserFlag1()","Set user-defined flag 1 to ture on the instance with name ""input1""" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the nets +nets = block.getNets() +adjust_factor = [] +# Iterate through all the nets +for net in nets(): + # Append the capacitance coupling adjust factor of the net + adjust_factor.append(net.getCcAdjustFactor()) +return adjust_factor",Get the capacitance coupling Adjust Factor of every net and return them as a list. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the nets +nets = block.getNets() +adjust_order = [] +# Iterate throgh all the nets +for net in nets(): + # Append the capacitance coupling adjust order of the net + adjust_order.append(net.getCcAdjustOrder()) +return adjust_order",Get the capacitance coupling Adjust Order of every net and return them as a list. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the nets +nets = block.getNets() +track_list = [] +# Iterate throgh all the nets +for net in nets: + # Get the tracks of the net + tracks = net.getTracks() + # Append the tracks to the track list + track_list.append(tracks) +return track_list",Get the tracks of every net as a list of lists. Each list in the output list should contain the tracks of respective net +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input1' as mentioned in the prompt +inst = block.findInst(""input1"") +# Get the nets of the instance +nets = inst.getNets() +track_list = [] +# Iterate through all the nets +for net in nets: + # Get the tracks of the net + tracks = net.getTracks() + track_list.append(tracks) +return track_list","Get the tracks of nets that are connected to instance with name ""input1"" as a list of list. Each list in the output list should contain the tracks of respective net" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the nets +nets = block.getNets() +types = [] +# Iterate through all the nets +for net in nets: + # Append the wire type of the net + types.append(net.getWireType()) +return types",Get the wire type of each net and return them as a list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the nets +nets = block.getNets() +termsCount = [] +# Iterate through all the nets +for net in nets: + # Get term counts of the net and append to the array + termsCount.append(net.getTermCount()) +return termsCount",Get term count of every net and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +insts = block.getInsts() +# Iterate through all the instances +for inst in insts: + # Get all the pins connected to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rise arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than 0.5 second as mentioned in the prompt + if pin_rise_arr > 0.5: + output.append(pin) +return output",Get all the pins which has the rising arrival time greater than 0.5 sec and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +insts = block.getInsts() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins connected to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is less than or equal 0.5 second as mentioned in the prompt + if pin_rise_arr <= 0.5: + output.append(pin) + +return output",Get all the pins which has the rising arrival time less than or equal to 0.5 second and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +insts = block.getInsts() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins connected to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_fall_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the fall arrival time is greater than 0.8 second as mentioned in the prompt + if pin_fall_arr > 0.8: + # Append the pin to the output + output.append(pin) + +return output",Get all the pins which has Pin Fall Arrival Time greater than 0.8 sec and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the nets +nets = block.getNets() +# Iterate through all the nets +for net in nets: + # Check if the wire is replaced with a new wire + if net.isWireAltered(): + return True +return False",Check all the nets and check if any of its wires is replaced with a new wire. Return True if Altered and false otherwise +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the ports (which are known of BTerms in OpenROAD) +ports = block.getBTerms() +d = {} +# Iterate through all the ports +for port in ports: + # Append the name and net of the port in the dictionary + d[port.getName()] = port.getNet() +return d",Get all the net of ports and return a dictionay with port name as key and Net of the port as Value of the dictionary +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the ports (which are known of BTerms in OpenROAD) +ports = block.getBTerms() +d = {} +# Iterate through all the ports +for port in ports: + # Append the name and block pins objects of the port in the dictionary + d[port.getName()] = port.getBPins() +return d",Get all the design block pins objects of ports and return a dictionay with port name as key and pins of the port as Value of the dictionary +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the design block ports (which are known of BTerms in OpenROAD) +ports = block.getBTerms() +placement_status_with_name = {} +# Iterate through all the ports +for port in ports: + # Get the name of the port + name = port.getName() + # Get the placement status of the port + status = port.getFirstPinPlacementStatus() + # Append the placement status and name of the port to the dictionary + placement_status_with_name[name] = status +return placement_status_with_name",Get the name of every design block port with the placement status of the first pin as a dictionary +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the ports (which are known of BTerms in OpenROAD) +ports = block.getBTerms() +d = {} +output = [] +# Iterate through all the ports +for port in ports: + # Append the port name and signal type of the port to the dictionary + d[port.getName()] = port.getSigType() +return d",Get the name of every block port with its signal type as a dictionary +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the ports (which are known of BTerms in OpenROAD) +ports = block.getBTerms() +d = {} +output = [] +# Iterate through all the ports +for port in ports: + # Append the port name and IO type of the port to the dictionary + d[port.getName()] = port.getIoType() +return d",Get all the I/O types of ports and return a dictionay with port name as keys and IO Type of the port as values +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""req_val"" +port = block.findBTerm(""req_val"") +# Find the boundary box of the port +BBox = port.getBBox() +# Get the X Min of the bounding box +xmin = BBox.xMin() +# Get the Y Min of the bounding box +ymin = BBox.yMin() +# Get the X Max of the bounding box +xmax = BBox.xMax() +# Get the Y Max of the bounding box +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","Get the Bounding Box of a port named ""req_val"". Return a list of coordinates (Xmin, Ymin in one list and Xmax, Ymax in another list) " +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""req_val"" +port = block.findBTerm('req_val') +# Set SPECIAL attribute to the port +port.setSpecial()",Set SPECIAL attribute port named 'req_val' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""req_val"" +port = block.findBTerm('req_val') +# Return whether the port has SPECIAL +return port.isSpecial()",Check if the port named 'req_val' has SPECIAL attribute +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the nets +nets = block.getNets() +# get and report wire_updated nets +return block.getWireUpdatedNets(nets)",Get the of nets for any wire changes and report the statistics of the nets with changed wires. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Return the technology layers +return tech.getLayers()",Get the technolgy layers. The layers are ordered from the bottom mask number to the top mask number. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Return the number of layers in this technology. +return tech.getLayerCount()",Get the number of layers in this technology. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Return the number of routing-layers in this technology. +return tech.getRoutingLayerCount()",Get the number of routing-layers in this technology. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Return the number of vias in this technolgy. +return tech.getViaCount()",Get the number of vias in this technolgy. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Return the via generate rules in this technolgy +return tech.getViaGenerateRules()",Get the via generate rules in this technolgy. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Get the technolgy vias. This includes non-default-rule-vias. +return tech.getVias()",Get the technolgy vias +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Get LEF CLEARANCEMEASURE +return tech.getClearanceMeasure()",Get LEF CLEARANCEMEASURE +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Return MANUFACTURINGGRID +# NOTE: Assumes conversion to internal DB units, +# NOT microns or LEF/DEF units +return tech.getManufacturingGrid()",Get MANUFACTURINGGRID +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the net with name ""req_msg[11]"" +net = block.findNet(""req_msg[11]"") +# Set the capacitance coupling adjust factor of the net to 1 +net.setCcAdjustFactor(1)","Set the capacitance coupling adjust factor of the net with name ""req_msg[11]"" to 1" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the net with name ""req_msg[11]"" +net = block.findNet(""req_msg[11]"") +# Set the capacitance coupling calibration factor of the net to 2 +net.setCcCalibFactor(2)","Set the capacitance coupling calibration factor of the net with name ""req_msg[11]"" to 2" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the nets +nets = block.getNets() +output = {} +# Iterate through all the nets +for net in nets: + # Append the net name and capacitance coupling match ratio against the net to a dictionary + output[net.getName()] = net.getCcMatchRatio() +return output",Get the capacitance coupling match ratio against this nets with the name of the net. Return a dictionary with key being the name of the net and value of the dictionary is the capacitance coupling match ratio against the net +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Iterate through the net names ""req_msg[13] and ""clk"" as mentioned in the prompt +for net_name in [""req_msg[13]"", ""clk""]: + # Find the net with net name as parameter + net = block.findNet(net_name) + # Set the coupling capacitance match ratio against the net to 1 + net.setCcMatchRatio(1)","Set the coupling capacitance match ratio against the net with name ""req_msg[13]"" and ""clk"" to 1" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Get the technology layers +layers = tech.getLayers() +output = [] +# Iterate through all the layers +for layer in layers: + # Get the names of the technology layers + output.append(layer.getName()) +return output",Get the names of the technology layers +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Get all the tehnology layers +layers = tech.getLayers() +output = {} +# Iterate through all the technology layers +for layer in layers: + # Append the layer name and AREA parameter to the dictionary + output[layer.getName()] = layer.getArea() +return output",Get the AREA parameter of the technology layers with their name. Return a dictionary with key as the layer name and value as the AREA parameter +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Get all the technology layers +layers = tech.getLayers() +output = {} +# Iterate through all the layers +for layer in layers: + # Append the layer name and layer direction to the dictionary + output[layer.getName()] = layer.getDirection() +return output",Get the directions of the technology layers with their name. Return a dictionary with key as the layer name and value as the layer direction +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name 'metal8' +layer = tech.findLayer('metal8') +# Return the routing layer corner spacing rule +return layer.getTechLayerCornerSpacingRules()",Get the routing layer corner spacing rules of technology layer with name 'metal8' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the technology layer with name 'metal8' +layer = tech.findLayer('metal8') +# Return the cut layer class rule +return layer.getTechLayerCutClassRules()",Get the cut layer class rule of layer with name 'metal8' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the technology layer with name 'metal8' +layer = tech.findLayer('metal8') +# Get the cut layer spacing rules +return layer.getTechLayerCutSpacingRules()",Get the cut layer spacing rules of layer with name 'metal8' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal10"" +layer = tech.findLayer('metal10') +# Return the end of line extension rules +return layer.getTechLayerEolExtensionRules()",Get the end of line extension rules of the technology layer with name 'metal10' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology object with technology information +tech = block.getTech() +# Find the layer with name ""via8"" +layer = tech.findLayer('via8') +# Return the tech layer forbidden spacing rules +return layer.getTechLayerForbiddenSpacingRules()",Get the forbidden spacing rules of the technology layer with name 'via8' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""via1"" +layer = tech.findLayer('via1') +# Return the keepout zone rules +return layer.getTechLayerKeepOutZoneRules()",Get the keepout zone rules of the technology layer with name 'via1' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the technology layer called ""OVERLAP"" +layer = tech.findLayer('OVERLAP') +# Return two widths spacing rules +# API for version 5.7 two widths spacing rules, expressed as a 2D matrix +# with index tables +return layer.getTwoWidthsSpacingTableNumWidths()",Get the two widths spacing rules of the technology layer with name 'OVERLAP' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the technology layer with name ""metal1"" +layer = tech.findLayer('metal1') +# Return the min cut rules +return layer.getTechLayerMinCutRules()",Get the minimum cut rules of the technology layer with name 'metal1' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the technology layer with name ""via2"" +layer = tech.findLayer('via2') +# Return the minimum step rules +return layer.getTechLayerMinStepRules()",Get the minimum step rules of the technology layer with name 'via2' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal3"" +layer = tech.findLayer('metal3') +# Return the collection of spacing rules for the object, assuming +# coding in LEF 5.4 format. +return layer.getV54SpacingRules()",Get the collection of spacing rules for the layer with name 'metal3' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal4"" +layer = tech.findLayer('metal4') +# Return the spacing end of line rules +return layer.getTechLayerSpacingEolRules()",Get the spacing end of line rules of layer with name 'metal4' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal5"" +layer = tech.findLayer('metal5') +# Return the layer type +return layer.getType()",Get the type of technology layer with name 'metal5' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""via3"" +layer = tech.findLayer('via3') +# Return the wrong direction spacing rules +return layer.getTechLayerWrongDirSpacingRules()",Get the wrong direction spacing rules of layer with name 'via3' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal1"" +layer = tech.findLayer('metal1') +# Return the x-axis offset +return layer.getOffset()",Get the offset along the x-axis of the technology layer with name 'metal1' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal2"" +layer = tech.findLayer('metal2') +# Return the x-axis offset +return layer.getOffsetX()",Get the offset along the x-axis of the technology layer with name 'metal2' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal3"" +layer = tech.findLayer('metal3') +# Return the y-axis offset +return layer.getOffsetY()",Get the offset along the y-axis of the technology layer with name 'metal3' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal3"" +layer = tech.findLayer('metal3') +# Return the y-axis offset +layer.setOffsetXY(0.2, 0.15)",Change the offset setting along the x-axis to 0.2 microns and the y-axis to 0.15 microns for the technology layer named 'metal3'. +"# Retrieve block information +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Get the technology information +tech = block.getTech() + +# Initialize a dictionary to store instance halos +inst_halos = {} + +# Iterate through each instance +for inst in insts: + # Store the halo information for each instance + inst_halos[inst.getName()] = inst.getHalo() + +# Find layer information for 'metal4' +layer1 = tech.findLayer('metal4') + +# Get technology layer spacing End-of-Line (EOL) rules for 'metal4' +layer_spacing_eol_rules = layer1.getTechLayerSpacingEolRules() + +# Find layer information for 'metal8' +layer2 = tech.findLayer('metal8') + +# Get technology layer corner spacing rules for 'metal8' +layer2_corner_spacing_rules = layer2.getTechLayerCornerSpacingRules() + +# Find layer information for 'metal5' +layer3 = tech.findLayer('metal5') + +# Get technology layer cut class rules for 'metal5' +layer_cut_class_rules = layer3.getTechLayerCutClassRules() + +# Store all the collected information in a dictionary +result = { + ""halos"": inst_halos, + ""metal4_EOL"": layer_spacing_eol_rules, + ""metal8_corner_spacing_rules"": layer2_corner_spacing_rules, + ""cut_class_rules"": layer_cut_class_rules +} + +# Return the collected information +return result","Get the following in a dictionary, with the given key names: +1. get all the halos of the instances with inst name as key. the key should be halos. +2. Get the routing layers spacing EOL rules of layer with name 'metal4'. The key should be metal4_EOL. +3. Get the routing layers corner spacing rules of layer with name 'metal8'. The key should be metal8_corner_spacing_rules. +4. get the routing layers cut class rules of layer with name 'metal8'. The key name for this will be cut_class_rules." +"# Get the current design block +block = design.getBlock() + +# Retrieve the capacitor-coupled segments +cc_segments = block.getCCSegs() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store source type of instances on level 1 whose master cells are either NAND or NOR +src_type = {} + +# Iterate through each instance +for inst in insts: + # Get the library cell of the instance + master = inst.getMaster() + + # Check if the library cell is special power type + if master.isSpecialPower(): + # Set the master of the instance as frozen so dbMTerms cannot be added or delete from the master once it is frozen. + inst.getMaster().setFrozen(True) + + # Check if the name of library cell is ""NAND2_X1"" or ""NOR3_X1"" and the instance is on level 1 + if (master.getName() == ""NAND2_X1"" or master.getName() == ""NOR3_X1"") and inst.getLevel() == 1: + # Store the source type of the instance in the dictionary + src_type[inst.getName()] = inst.getSourceType() + +# Return the tuple containing the cc_segments and the source type dictionary of instances +return (cc_segments, src_type)","Retrieve the capacitor-coupled segments and frozen the library cells with special power type, then get source type of all the instances on level 1 whose master cells are either ""NAND2_X1"" or ""NOR3_X1""." +"# Get the current design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Find the instance '_411_' +inst1 = block.findInst('_411_') + +# Set user-defined flags 1 and 3 for instance '_411_' +inst1.setUserFlag1() +inst1.setUserFlag3() + +# Find the instance 'input1' +inst2 = block.findInst('input1') + +# Mark the first output nets of the instances '_411_' and 'input1' +net1 = inst1.getFirstOutput().getNet() + +# Dictionary to store instance transform offsets +inst_transform_offset_dict = {} + +# Iterate through each instance +for inst in insts: + # Check if the master cell name is ""AND2X_1"" + if inst.getMaster().getName() == ""AND2X_1"": + # Store the offset of the instance with master 'AND2_X1' + inst_transform_offset_dict[inst.getName()] = inst.getTransform().getOffset() + +# Return the dictionary containing instance transform offsets +return inst_transform_offset_dict","Set user-defined flags 1 and 3 for instance '_411_' and mark the first output nets of the instances '_411_' and 'input1', followed by getting the offset of the instances whose master is 'AND2_X1' in the form of dictionary with instance name as key." +"# Get the current design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store instances and their respective regions +inst_regions = {} + +# List to store pad instances on level 0 +inst_list = [] + +# Iterate through each instance +for inst in insts: + # Store instance name and its region in the inst_regions dictionary + inst_regions[inst.getName()] = inst.getRegion() + + # Check if the instance is a pad and it's on level 0 + if inst.isPad() and inst.getLevel() == 0: + # Append the instance to the list of pad instances + inst_list.append(inst) + + # Check if the instance name is ""input1"" + if inst.getName() == ""input1"": + # Iterate through each pin of the instance + for pin in inst.getITerms(): + # Get the net connected to the pin + net = pin.getNet() + # Check if the net exists + if net: + # Set RC disconnected for the net + net.setRCDisconnected(True) + +# Return the list of pad instances +return inst_list",Retrieve the instances and their corresponding areas if they are PAD or any of its subtypes and set as level 0. Proceed to disconnect the RC for the networks associated with the 'input1' instance. +"# Get the current design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store offsets of instances whose master cell is 'NAND2_X1' +NAND_offsets = {} + +# Iterate through each instance +for inst in insts: + # Check if the library cell name is ""NAND2_X1"" + if inst.getMaster().getName() == ""NAND2_X1"": + # Store the xy location of the instance + NAND_offsets[inst.getName()] = inst.getTransform().getOffset() + + # Check if the instance name is ""_411_"" + if inst.getName() == ""_411_"": + # Iterate through each pin of the instance + for pin in inst.getITerms(): + # Get the net connected to the pin + net = pin.getNet() + # Check if the net exists + if net: + # Set RC disconnected for the net + net.setRCDisconnected(True) + +# Return the dictionary containing offsets of instances +return NAND_offsets",Get the offset of all 'NAND2_X1' cells and set the RC disconnected for the nets of the instance 'input1'. +"block = design.getBlock() + +# find the instance 'output53' +inst = block.findInst('output53') + +# Initialize a list to store the input pins of the instance +input_pins = [] + + +# Obtain all pins associated with this instance +pins = inst.getITerms() + +# Iterate through each pin of the instance +for pin in pins: + # Check if the pin represents an input signal + if pin.isInputSignal() and pin: + # Append the input pin to the list of input pins + input_pins.append(pin) + +# Return the list of input pins connected to the instance +return input_pins",get the input pins of the instance 'output53' +"# Get the nets of the input pins of instance 'output53' + +block = design.getBlock() + +# find the instance 'output53' +inst = block.findInst('output53') + +# Initialize a list to store nets of input pins +input_nets = [] + +# Get all input pins (ITerms) of the instance +pins = inst.getITerms() + +# Iterate through all input pins +for pin in pins: + # Check if the pin is an input signal + if pin.isInputSignal() and pin: + # If it's an input signal, add its net to the list + input_nets.append(pin.getNet()) + +# Return the list of nets of input pins of the instance +return input_nets",get the nets connected to the input pins of the instance 'output53' +"# Retrieve all instances that have a hierarchy and whose library cell type is 'AND2_X1' and are on level 1. + +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a list to store matching instances +inst_list = [] + +# Iterate through all instances +for inst in insts: + # Check if the instance has hierarchy, its library cell is 'AND2_X1', and it is on level 1 + if inst.isHierarchical() and inst.getMaster().getName()==""AND2_X1"" and inst.getLevel() == 1: + # Add the instance to the list + inst_list.append(inst) + +# Return the list of matching instances +return inst_list +",Retrieve all instances that have a hierarchy and whose library cell type is 'AND2_X1' and are on level 1. +"# Get the resistor segments + +# Get the design block +block = design.getBlock() + +# Return the resistor segments +return block.getRSegs()",get the resistor segments of the design block +"# Retrieve the LEQ (Logical equivalent) information associated with the library cell of instance '_411_' + +# Get the design block +block = design.getBlock() + +# Find the instance with name '_411_' +inst = block.findInst('_411_') + +# Get the library cell associated with the instance +master = inst.getMaster() + +# Retrieve the LEQ information +leq_info = master.getLEQ() + +# Return the LEQ information +return leq_info",Retrieves the LEQ (Logical equivalent) information associated with the library cell of instance '_411_' +"# Get all the pad and set as level 1 + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a list to store matching instances +inst_list = [] + +# Iterate through all instances +for inst in insts: + # Check if the instance is a pad and it is level 1 + if inst.isPad() and inst.getLevel() == 1: + # Add the instance to the list + inst_list.append(inst) + +# Return the list of matching instances +return inst_list",get all the pad instances that are level 1 +"# Get the vertical thickness multiplier for the IO pin placer's parameters and set corner avoidance to 50 + +# Get the IO pin placer +iop = design.getIOPlacer() + +# Get the parameters of the IO pin placer +parameters = iop.getParameters() + +# Set corner avoidance to 50 +parameters.setCornerAvoidance(50) + +# Return the vertical thickness multiplier +return parameters.getVerticalThicknessMultiplier()",get the vertical thickness multiplier for the IO pin placer's parameters and set corner avoidance to 50 +"# Get the design block +block = design.getBlock() + +# Find the instance named ""FILLER_0_17_159"" +inst = block.findInst(""FILLER_0_17_159"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Reverse the resistor segment sequence of the net + net.reverseRSegs() +",Reverse the resistor segment seqence of the nets of the instance FILLER_0_17_159 +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store nets with wire-ordered flag set as True +ordered_wires = [] + +# Iterate through each net +for net in nets: + # Check if the wire-ordered flag is set to true + if net.isWireOrdered(): + # Append the net to the list + ordered_wires.append(net) + +# Return the list of nets with ordered wires +return ordered_wires +","Get the nets if their wire-ordered flag is set as True, and return it as a list" +"# Get the design block +block = design.getBlock() + +# List of net names to set wire type as ROUTED +nets = [ + ""_000_"", + ""_001_"", + ""_002_"", + ""_003_"", + ""_004_"", + ""_005_"", + ""_006_"", + ""_007_"", + ""_008_"", + ""_009_"", + ""_010_"" +] + +# Iterate through each net name +for name in nets: + # Find the net object by name + net = block.findNet(name) + + # Set the wire type of the net as ROUTED + net.setWireType('ROUTED') + + +","Set the following nets wire type to ROUTED: _000_, _001_, _002_, _003_, _004_, _005_, _006_, _007_, _008_, _009_, _010_ +" +"# Get the design block +block = design.getBlock() + +# List to store nets with ordered wires +ordered_wires = [] + +# List of net names +nets = [ + ""net1"", + ""net10"", + ""net11"", + ""net12"", + ""net13"", + ""net14"", + ""net15"", + ""net16"", + ""net17"", + ""net18"", + ""net19"" +] + +# Iterate through each net name +for name in nets: + # Find the net object by name + net = block.findNet(name) + + # Set the wire ordered flag to true + net.setWireOrdered(True) + + # Append the net to the list of nets with ordered wires + ordered_wires.append(net) + +# Return the list of nets with ordered wires +return ordered_wires +","Set the wires ordered flag to true for the following nets and return a list of these nets: net1, net10, net11, net12, net13, net14, net15, net16, net17, net18, net19 +" +"# Get the design block +block = design.getBlock() + +# List to store nets +altered_wires_net = [] + +# List of net names +nets = [ + ""_000_"", + ""_001_"", + ""_002_"", + ""_003_"", + ""_004_"", + ""_005_"", + ""_006_"", + ""_007_"", + ""_008_"", + ""_009_"", + ""_010_"" +] + +# Iterate through each net name +for name in nets: + # Find the net object by name + net = block.findNet(name) + + # Set the wire update flag to true + net.setWireAltered(True) + + # Append the net to the list of nets + altered_wires_net.append(net) + +# Return the list of the nets +return altered_wires_net +","Set the wire update flag to true for the wires of the following nets and return a list of these nets: _000_, _001_, _002_, _003_, _004_, _005_, _006_, _007_, _008_, _009_, _010_ +" +"# Get the design block +block = design.getBlock() + +# List to store selected nets +selected_nets = [] + +# List of net names to select +net_names = [ + ""net1"", + ""net10"", + ""net11"", + ""net12"", + ""net13"", + ""net14"", + ""net15"", + ""net16"", + ""net17"", + ""net18"", + ""net19"" +] + +# Iterate through each net name +for name in net_names: + # Find the net object by name + net = block.findNet(name) + + # Set the net as selected + net.setSelect(True) + + # Append the selected net to the list + selected_nets.append(net) + +# Return the list of selected nets +return selected_nets +","set the select flag true for the following nets and return the list of these nets: net1, net10, net11, net12, net13, net14, net15, net16, net17, net18, net19 +" +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store nets +wild_connected_nets = [] + +# Iterate through each net +for net in nets: + # Check if the net is connected using a wild-card + if net.isWildConnected(): + # Append the net to the list + wild_connected_nets.append(net) + +# Return the list of nets +return wild_connected_nets +",Get the nets connected using a wild-card. +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store nets marked as ""do not touch"" +do_not_touch_nets = [] + +# Iterate through each net +for net in nets: + # Check if the net is set as ""do not touch"" + if net.isDoNotTouch(): + # Append the net to the list + do_not_touch_nets.append(net) + +# Return the list of nets set as ""do not touch"" +return do_not_touch_nets",Get the nets that are set as do not touch and return as a list +"# Get the design block +block = design.getBlock() + +# Find the instance named ""input6"" +inst = block.findInst(""input6"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective coupled capacitor adjust orders +net_Cc_adjust_order = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its coupled capacitor adjust order in the dictionary + net_Cc_adjust_order[net.getName()] = net.getCcAdjustOrder() + +# Return the dictionary containing net names and their Cc adjust orders +return net_Cc_adjust_order",Get the coupled capacitor adjust order for the nets of the instance input6 and return the result as a dict with key being net name and value being the coupled capacitor adjust order +"# Get the design block +block = design.getBlock() + +# Find the instance named ""input6"" +inst = block.findInst(""input6"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective wire types +net_wire_type = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its wire type in the dictionary + net_wire_type[net.getName()] = net.getWireType() + +# Return the dictionary containing net names and their wire types +return net_wire_type",Get the wire types of the nets connecting to the instance input6 and return the result as a dictionary with key being net name and value being the wire type +"# Get the design block +block = design.getBlock() + +# List to store marked nets +marked_nets = [] + +# List of net names to mark +nets_to_mark = [ + ""resp_msg[4]"", + ""resp_msg[5]"", + ""resp_msg[6]"", + ""resp_msg[7]"", + ""resp_msg[8]"", + ""resp_msg[9]"", + ""resp_rdy"", + ""resp_val"" +] + +# Iterate through each net name +for name in nets_to_mark: + # Find the net object by name + net = block.findNet(name) + + # Set the mark flag of the net to True + net.setMark(True) + + # Append the marked net to the list + marked_nets.append(net) + +# Return the list of marked nets +return marked_nets","Set mark flags to the nets resp_msg[4], resp_msg[5], resp_msg[6], resp_msg[7], resp_msg[8], resp_msg[9], resp_rdy, resp_val and return the list of market nets." +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store selected nets +selected_nets = [] + +# Iterate through each net +for net in nets: + # Check if the net is selected + if net.isSelect(): + # Append the net to the list + selected_nets.append(net) + +# Return the list of selected nets +return selected_nets",Get the selected nets +"# Get thedesign block +block = design.getBlock() + +# Find the instance named ""input6"" +inst = block.findInst(""input6"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective total resistances +net_total_resistance = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its total resistance in mil ohms in the dictionary + net_total_resistance[net.getName()] = net.getTotalResistance() + +# Return the dictionary containing net names and their total resistances +return net_total_resistance +","Get the total resistance in mil ohms of the nets connecting to the instance ""input6"" and return the result as a dict using net name as key and resistance as value" +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store nets connected by abutment +abutment_nets = [] + +# Iterate through each net +for net in nets: + # Check if the net have its pins connected by abutment + if net.isConnectedByAbutment(): + # Append the net to the list + abutment_nets.append(net) + +# Return the list of nets connected by abutment +return abutment_nets",Get the nets that have their pins connected by abutment and return as a list +"# Get the design block +block = design.getBlock() + +# Find the instance named ""_699_"" +inst = block.findInst(""_699_"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective coupled capacitor match ratio +net_cc_match_ratio = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its coupled capacitor match ratio in the dictionary + net_cc_match_ratio[net.getName()] = net.getCcMatchRatio() + +# Return the dictionary containing net names and their Cc Match ratios +return net_cc_match_ratio +","Get the coupled capacitor match ratio of the nets connecting to the instance ""_699_"" and return as a dict using net name as key and coupled capacitor match ratio as value" +"# Get the design block +block = design.getBlock() + +# Find the instance named ""input10"" +inst = block.findInst(""input10"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective node capacitors +net_cap_nodes = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its cap nodes in the dictionary + net_cap_nodes[net.getName()] = net.getCapNodes() + +# Return the dictionary containing net names and their cap nodes +return net_cap_nodes","Get the node capacitor of the RC segment belong to each net connecting to the instance input10, and return the result as a dict with net name being keys and node capacitors as values" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal4"" +layer = tech.findLayer('metal4') +# Return the pitch of the layer +return layer.getPitch()","Get the pitch setting of ""metal 4"" layer" +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store extracted nets +extracted_nets = [] + +# Iterate through each net +for net in nets: + # Check if the net is extracted + if net.isExtracted(): + # Append the extracted net to the list + extracted_nets.append(net) + +# Return the list of extracted nets +return extracted_nets",Get all extracted nets as a list +"# Get the design block +block = design.getBlock() + +# Find the instance named ""input10"" +inst = block.findInst(""input10"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective routing guides +net_guides = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its routing guides in the dictionary + net_guides[net.getName()] = net.getGuides() + +# Return the dictionary containing net names and their routing guides +return net_guides","Get the routing guides of the nets connecting to the instance ""input10"" as a dictionary, using net name as keys and routing guide as values" +"# Get the design block +block = design.getBlock() + +# Find the instance named ""FILLER_0_17_13"" +inst = block.findInst(""FILLER_0_17_13"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective tracks +net_tracks = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its tracks in the dictionary + net_tracks[net.getName()] = net.getTracks() + +# Return the dictionary containing net names and their tracks +return net_tracks","Get the tracks of the nets connecting to the instance ""FILLER_0_17_13"", and return it as a dict using net name as keys and tracks as values" +"# Get the design block +block = design.getBlock() + +# Find the instance named ""rebuffer29"" +inst = block.findInst(""rebuffer29"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Reverse the coupled capacitor segments of the net + net.reverseCCSegs()",Reverse the coupled capacitor segments of the nets connecting to the instance called rebuffer29 +"# Get the design block +block = design.getBlock() + +# Find the instance named ""rebuffer9"" +inst = block.findInst(""rebuffer9"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective driving ITerms +net_driving_iterm = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its driving term id assigned of this net. -1 if not set, 0 if non existent + net_driving_iterm[net.getName()] = net.getDrivingITerm() + +# Return the dictionary containing net names and their driving ITerms +return net_driving_iterm","Get the driving term ids for the nets connecting to the instance rebuffer9, and return the rsult as a dict using net name as keys and driving term ids as values" +"# Get the design block +block = design.getBlock() + +# Find the instance named ""output52"" +inst = block.findInst(""output52"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Print the net name + print(""Net:"", net.getName()) + + # Print the wire opcodes + net.printWire()",Print the wire opcode information of the the nets connecting to the instance output52 +"# Get the design block +block = design.getBlock() + +# Find the instance named ""_706_"" +inst = block.findInst(""_706_"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective Cap node counts +net_cap_node_count = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its node capacitor count in the dictionary + net_cap_node_count[net.getName()] = net.getCapNodeCount() + +# Return the dictionary containing net names and their Cap node counts +return net_cap_node_count +","Get the node capacitor count of RC segments of the nets connecting to the instance _706_, and return the result as a dictionary with keys being net name, and values being node capacitor count " +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store nets that are RC graphs +rc_graph_nets = [] + +# Iterate through each net +for net in nets: + # Check if the rc_graph flag set, and the flag is set when Rseg and CapNodes were created + if net.isRCgraph(): + # Append the net to the list + rc_graph_nets.append(net) + +# Return the list of nets that are RC graphs +return rc_graph_nets +","Get all the nets if their rc_graph flag is set, and return the result as a list" +"# Get the design block +block = design.getBlock() + +# Find the instance named ""split30"" +inst = block.findInst(""split30"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective term counts +net_term_count = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and the amount of pins and ports of this net in the dictionary + net_term_count[net.getName()] = net.getTermCount() + +# Return the dictionary containing net names and their amount of pins and ports +return net_term_count","Get the amount of pins and ports of the nets connecting to the instance ""split30"" and return it as a dictionary with net name being keys" +"# Get the design block +block = design.getBlock() + +# Find the instance named ""clkbuf_0_clknet_2_3__leaf_clk"" +inst = block.findInst(""clkbuf_0_clknet_2_3__leaf_clk"") + +# Get all pins (interface terms) connecting to the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective x-talk classes +net_X_Talk_class = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its x-talk class in the dictionary + net_X_Talk_class[net.getName()] = net.getXTalkClass() + +# Return the dictionary containing net names and their x-talk classes +return net_X_Talk_class","Get the x-talk-class of the nets connecting to the instance ""clkbuf_0_clknet_2_3__leaf_clk"", as a dictionary with the net names as key values." +"# Get the design block +block = design.getBlock() + +# Find the instance named ""rebuffer5"" +inst = block.findInst(""rebuffer5"") + +# Get all pins (interface terms) connecting to the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective first BTerms +net_first_bterms = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its first BTerm in the dictionary + net_first_bterms[net.getName()] = net.get1stBTerm() + +# Return the dictionary containing net names and their first BTerms +return net_first_bterms","Get the first port of the nets connecting to the instance rebuffer5, as a dictionary with the net names as key values." +"# Get the design block +block = design.getBlock() + +# Find the instance named ""input22"" +inst = block.findInst(""input22"") + +# Get all pins (interface terms) connecting to the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective R segment counts +net_R_seg_count = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its R segment count in the dictionary + net_R_seg_count[net.getName()] = net.getRSegCount() + +# Return the dictionary containing net names and their R segment counts +return net_R_seg_count","Get the R segment count of the RC network connected to the nets of the instance input22, return the result as a dictionary with net names as key values." +"# Get the design block +block = design.getBlock() + +# Find the instance named ""_686_"" +inst = block.findInst(""_686_"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective nondefault rule applied for wiring +net_non_default_rule = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and the nondefault rule applied to this net for wiring in the dictionary, returns nullptr if there is no nondefault rule. + net_non_default_rule[net.getName()] = net.getNonDefaultRule() + +# Return the dictionary containing net names and their nondefault rule applied to this net for wiring +return net_non_default_rule",Get the nondefault rule applied to the nets connected to the instance _686_ as a dictionary with the net names as key values. +"# Get the design block +block = design.getBlock() + +# Find the instance named ""_706_"" +inst = block.findInst(""_706_"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective zeroth R segments +net_zero_R_segment = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its zeroth R segment in the dictionary + net_zero_R_segment[net.getName()] = net.getZeroRSeg() + +# Return the dictionary containing net names and their zeroth R segments +return net_zero_R_segment",Get the zeroth R segment of the nets of the instance _706_ as a dictionary with the net names as key values. +"# Get the current design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers defined in the technology +layers = tech.getLayers() + +# Dictionary to store layer directions with their names +layer_direction_dict = {} + +# Dictionary to store upper and lower layers of the 'poly' layer +poly_upper_lower_layers = {} + +# Iterate through each layer +for layer in layers: + # Store the direction of the layer with its name in the dictionary + layer_direction_dict[layer.getName()] = layer.getDirection() + + # If the layer name is 'poly', store its upper and lower layers + if layer.getName() == ""poly"": + poly_upper_lower_layers = { + ""upper"": layer.getUpperLayer(), + ""lower"": layer.getLowerLayer() + } + +# Create a result dictionary containing layer directions and 'poly' upper and lower layers +result = { + ""layer_directions"": layer_direction_dict, + ""poly"": poly_upper_lower_layers +} + +# Return the result dictionary +return result","Get the routing directions of the layers with their names as keys and also get the layers above and below the layer with name 'poly'. Finally, return them as dict of dicts" +"# Get the current design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# Dictionary to store Capacitance Coupling Match Ratio of each net +net_cc_match_ratio = {} + +# Iterate through each net and store its Capacitance Coupling Match Ratio +for net in nets: + net_cc_match_ratio[net.getName()] = net.getCcMatchRatio() + +# List of net names to set Capacitance Coupling Match Ratio to 1 +nets = [""req_msg[13]"", ""clk""] + +# Iterate through each net name in the list and set its Capacitance Coupling Match Ratio to 1 +for net_name in nets: + net = block.findNet(net_name) + net.setCcMatchRatio(1) + +# Return the dictionary containing Capacitance Coupling Match Ratio of each net +return net_cc_match_ratio +","Calculate the Capacitance Coupling Match Ratio for each net and organize the results into a dictionary. Use the net names as keys and their corresponding Capacitance Coupling Match Ratios as values. Additionally, ensure that the Capacitance Coupling Match Ratios for the nets named ""req_msg[13]"" and ""clk"" are set to 1." +"# Get the current design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get the vias defined in the technology +vias = tech.getVias() + +# Get the Via Count of the technology +via_count = tech.getViaCount() + +# Set the Clearance Measure of the technology to 500 +print(tech.getClearanceMeasure()) + +# Create a dictionary containing vias and the count of vias +result = { + ""vias"": vias, + ""count"": via_count +} + +# Return the result dictionary +return result","Get the vias and via count as a dictionary with ""vias"" and ""count"" as keys, and print the Clearance Measure." +"# Get the current design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers defined in the technology file +layers = tech.getLayers() + +# Dictionary to store areas of layers with their names +layer_area_dict = {} + +# Iterate through each layer +for layer in layers: + # Store the area of the layer with its name in the dictionary + layer_area_dict[layer.getName()] = layer.getArea() + +# Create a result dictionary containing layer area dictionary and list of layer names +result = { + ""area_dict"": layer_area_dict, + ""layer_names"": list(layer_area_dict.keys()) +} + +# Return the result dictionary +return result","Retrieve the layer names defined in the technology as a list and obtain the corresponding areas of these layers of the technology, associating each area with its respective layer name in a dictionary. Return this result encapsulated in a dictionary with ""area_dict"" representing the areas of the layers and ""layer_names"" representing the list of layer names." +"# Get the current design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get the Via Count of the technology +via_count = tech.getViaCount() + +# Get the Via Generate Rules of the technology +via_rules = tech.getViaGenerateRules() + +# Get the current value of database units per micron and add 500 +db_microns = block.getDbUnitsPerMicron() + 500 + +# Set the new value of database units per micron +tech.setDbUnitsPerMicron(db_microns) + +# Create a dictionary containing via count, via rules, and the updated value of database units per micron +result = { + ""count"": via_count, + ""rules"": via_rules +} + +# Return the result dictionary +return result","Retrieve the via count and via generate rules of the technology. Return the result as a dictionary with ""count"" and ""rules"" as keys for the via count and via generate rules, respectively." +"# Get the current design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store rotation of the instances whose library cells are of type 'NOR2_X1' +NOR_transform_orient = {} + +# Iterate through each instance +for inst in insts: + # Check if the library cell name is ""NOR2_X1"" + if inst.getMaster().getName() == ""NOR2_X1"": + # Store the rotation of the instance + NOR_transform_orient[inst.getName()] = inst.getTransform().getOrient() + + # Check if the instance name is ""_411_"" or ""input1"" + if inst.getName() == ""_411_"" or inst.getName() == ""input1"": + # Mark the first output net of the instance + inst.getFirstOutput().getNet().setMark(True) + +# Return the dictionary containing orientation of instance +return NOR_transform_orient","Get the rotation of the instances whose library cells are of type 'NOR2_X1' and return as a dict with instance name as keys, and mark the first output nets of the instances '_411_' and 'input1'." +"# Get the current design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Iterate through each instance +for inst in insts: + # Check if the master cell name contains ""NAND2_X1"" + if inst.getMaster().getName() == ""NAND2_X1"": + # Invert the instance + inst.getTransform().invert() + + # Check if the instance name is ""_411_"" or ""input1"" + if inst.getName() == ""_411_"" or inst.getName() == ""input1"": + # Get the transform of the instance + transform = inst.getTransform() + # If the orientation is 'R0', set it to 'MX'; if 'MX', set it to 'R0' + if transform.getOrient() == 'R0': + transform.setOrient('MX') + elif transform.getOrient() == 'MX': + transform.setOrient('R0')",Invert the offset and the rotation of instances whose library cells are 'NAND2_X1' and set the orient of the instance '_411_' to 'R0' if 'MX' or 'MX' if 'R0'. +"# Get the current design block +block = design.getBlock() + +# Find the instance '_411_' +inst = block.findInst('_411_') + +# Set the orientation of the instance '_411_' to 'MX' +inst.getTransform().setOrient('MX') + +# Get all instances +insts = block.getInsts() + +# Dictionary to store halos of instances +inst_halos = {} + +# Iterate through each instance +for inst in insts: + # Store the halo of the instance in the inst_halos dictionary + inst_halos[inst.getName()] = inst.getHalo() + +# Return the dictionary containing halos of instances +return inst_halos",Set the orientation of the instance '_411_' to 'MX' and retrieve all the halos of instances. Return the result as a dictionary with each instance's name as the key mapped to their halo. +"# Get the current design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Get the technology information +tech = block.getTech() + +# Get all layers defined in the technology +layers = tech.getLayers() + +# Initialize lists to store non-core instances and vertical tech layers with capacitance +vertical_layers = [] +non_core_insts = [] + +# Define the direction for the layers +direction = 'VERTICAL' + +# Iterate through each instance +for inst in insts: + # Check if instance is not core instance + if not inst.getMaster().isCore(): + # Add the instance to the list of non-core instances + non_core_insts.append(inst) + +# Iterate through each layer in the technology +for layer in layers: + # Check if the layer direction is VERTICAL + if layer.getDirection() == direction: + # Add the layer and its capacitance to the list of vertical layers + vertical_layers.append((layer, layer.getCapacitance())) + +# Return the list of non-core instances and horizontal layers with their capacitance +return (non_core_insts, horizontal_layers)",Get a list of all the non-core instances and a list of the vertical layers and their capacitance as a list of tuples. +"# Get the current design block +block = design.getBlock() + +# Get all the instances +insts = block.getInsts() + +# Find the instance with the name '_411_' +inst = block.findInst('_411_') + +# Dictionary to store signal types in nets +signal_type_dict = {} + +# Check if instance '411' is type ENDCAP or any of its subtypes +print(""End cap status of cell '_411_':"", inst.isEndCap()) + +# Loop through all instances +for inst in insts: + # Check if any of the user flags are set to true + if inst.getUserFlag1() or inst.getUserFlag2() or inst.getUserFlag3(): + # Set the level of the instance to 1 + inst.setLevel(1) + + # Check if the instance name is 'input1' + if inst.getName() == ""input1"": + # Get the nets connected to 'input1' instance + nets = [pin.getNet() for pin in inst.getITerms()] + + # Iterate through each net + for net in nets: + # Check if the net exists + if net: + # Store the signal type of the net in the dictionary + signal_type_dict[net.getName()] = net.getSigType() + break + +# Return the dictionary containing signal types in nets +return signal_type_dict","Check if the library cell of instance '_411_' is type ENDCAP and get all the instances whose user flags are set and set those instances to level 1, also get the signal types in the nets of instance 'input1'" +"# Set userFlags 1 and 3 true for instance '411' and retrieve the LEQ (Logic Equivalent) information associated with the library cell of instance '411'. + +# Get the dsign block +block = design.getBlock() + +# Find the instance '411' +inst = block.findInst(""_411_"") + +# Set userFlags 1 and 3 true +inst.setUserFlag1() +inst.setUserFlag3() + +# Get the library cell of instance '411' +master = inst.getMaster() + +# Retrieve the LEQ information associated with the library cell +LEQ = master.getLEQ() + +# Return LEQ +return LEQ",Set userFlags 1and 3 true for instance '411' and retrieves the LEQ (Logic Equivalent) information associated with the library cell of instance '411'. +"# Get the location of the instances whose library cell is 'AND2_X1' and get rotation of instance whose library cells are of type 'NAND2_X1'. + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store offset of 'AND2_X1' instances and location of 'NAND2_X1' instances +offset_dict_AND = {} +orient_dict_NAND = {} + +# Iterate through instances +for inst in insts: + # Check if the master cell name contains 'AND2_X1' + if inst.getMaster().getName() == ""AND2_X1"": + # Get transform and store offset + transform = inst.getTransform() + offset_dict_AND[inst.getName()] = transform.getOffset() + + # Check if the master cell name contains 'NAND2_X1' + if inst.getMaster().getName() == ""NAND2_X1"": + # Get transform and store location + transform = inst.getTransform() + orient_dict_NAND[inst.getName()] = transform.getOrient() + +# Return dictionaries of offsets and locations +return (offset_dict_AND, orient_dict_NAND)",Get the location of the instances whose library cell is 'AND2_X1' as a dicitonary with instance names as keys and get rotation of instance whose library cells are of type 'NAND2_X1'. +"# Set all the COVER master cells to frozen + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Iterate through instances +for inst in insts: + # Get the master of the instance + master = inst.getMaster() + # Check if the master is of type COVER + if master.isCover(): + # Set the COVER master cell to frozen so dbMTerms cannot be added or delete from the master + master.setFrozen()",set all the COVER master cells to frozen +"# Invert transforms of the instances whose master cells are 'NAND2_X1' +# and get the offset of the transform of instance '411' and 'input1'. + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store offset of transforms for instances '_411_' and 'input1' +inst_transform_offset = {} + +# Iterate through instances +for inst in insts: + # Check if the master cell name is 'NAND2_X1' + if inst.getMaster().getName() == ""NAND2_X1"": + # Get transform and invert + transform = inst.getTransform() + transform.invert() + + # Check if instance name is '411' or 'input1' + if inst.getName() == '_411_' or inst.getName() == 'input1': + # Get transform and store offset + transform = inst.getTransform() + inst_transform_offset[inst.getName()] = transform.getOffset() + +# Return dictionary containing offsets for instances '411' and 'input1' +return inst_transform_offset","Invert the location and rotation of instances whose library cells are 'NAND2_X1'. Then, retrieve the location of the instances '_411_' and 'input1' and return them as a dictionary with the instance names as keys and their respective location as values." +"# Get All the nets of the instances whose signal type is ""SIGNAL"" and get all the blockages. + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# List to store nets with signal type 'SIGNAL' +nets = [] + +# Iterate through instances +for inst in insts: + # Get all pins of the instance + pins = inst.getITerms() + # Iterate through pins + for pin in pins: + # Check if the signal type is 'SIGNAL' + if pin.getSigType() == 'SIGNAL': + # Add the net to the list + nets.append(pin.getNet()) + +# Get all blockages in the block +blockages = block.getBlockages() + +# Return a tuple containing the list of nets and blockages +return (nets, blockages)","Get a list of all the nets of the instances whose signal type is ""SIGNAL"" and get all the blockages. Return the result as a tuple" +"# Get the design block +block =design.getBlock() + +# Reset the tapcell in the design +tapcell = design.getTapcell() +tapcell.reset() + +# Retrieve the coupling capacitance segments +coupling_segments = block.getCCSegs() + +# Return the coupling capacitance segments +return coupling_segments",Reset the tapcell in the design and retrieve the coupling capacitance segments of the design block. +"# Get the list of hierarchical filler cell instances. + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# List to store hierarchical instances with filler cells +inst_list = [] + +# Iterate through instances +for inst in insts: + # Check if the instance is hierarchical and its master is a filler cell + if inst.isHierarchical() and inst.getMaster().isFiller(): + inst_list.append(inst) + +# Return hierarchical instances with filler cells +return inst_list",Get the list of hierarchical filler cell instances. +"# Get the resistor segments and get the sites of rows +block = design.getBlock() +resistor_segments = block.getRSegs() + +# Get the sites of rows +rows = block.getRows() +hybrid_rows = {} +for row in rows: + if row.getSite().isHybrid(): + hybrid_rows[row] = row.getSite() + +# Return resistor segments and hybrid rows +return (resistor_segments, hybrid_rows) +","Get the resistor segments and a dictionary of the hybrid sites of the rows, with the row as the key and the site as the value." +"# Get source type of all the instance on level 1 with filler cells and set the placement Status of the instance 'input1' to 'UNPLACED'. + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store source types +source_dict = {} + +# Iterate through instances +for inst in insts: + # Check if the instance's master is a filler cell and it is set as level 1 + if inst.getMaster().isFiller() and inst.getLevel() == 1: + # Get and store the source type + source_dict[inst.getName()] = inst.getSourceType() + + # Check if the instance is 'input1' and set its placement status to 'UNPLACED' + if inst.getName() == ""input1"": + inst.setPlacementStatus('UNPLACED') + +# Return source types +return source_dict +","Get source type of all the filler cell instances set as level 1 as a dictionary with inst name as keys. Also, set the placement status flag of the instance 'input1' to 'UNPLACED'." +"# Set the alias of the layers by the naming convention ''LayerXi"" where i is the index of the layer and get the status of USEMINSPACING for pins in LEF. return the results as a dict with each requirement as key names. + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers +layers = tech.getLayers() + +# Initialize a dictionary to store the Alias of each layer +layer_alias = {} + +# Iterate through all layers +for layer in layers: + # Construct the Alias using the layer index + alias = ""LayerX"" + str(layer.getNumber()) + + # Set the Alias of the layer + layer.setAlias(alias) + + # Store the Alias of the layer in the dictionary + layer_alias[layer.getName()] = alias + +# Get the status of USEMINSPACING for pins in LEF +min_spacing_pin = tech.getUseMinSpacingPin() + +# Return the dictionary containing the updated Alias of layers +return { + ""Alias"": layer_alias, + ""min_spacing_pin"": min_spacing_pin +}","Set the alias of the layers by the naming convention ''LayerXi"" where i is the index of the layer and get the status of USEMINSPACING for pins in LEF. return the results as a dict with each requirement as key names." +"# Get the current block of the design +block = design.getBlock() + +# Find the instances '_411_' and 'input1' +inst1 = block.findInst('_411_') +inst2 = block.findInst('input1') + +# Get the library cells of the instances +master1 = inst1.getMaster() +master2 = inst2.getMaster() + +# Get the MTerms of the library cell of the instance '_411_' +mterms1 = master1.getMTerms() + +# Get the MTerms of the library cell of the instance 'input1' +mterms2 = master2.getMTerms() + +# List to store input MTerms of the instance 'input1' +input_mterms = [] + +# Iterate through each MTerm of the instance 'input1' +for mterm in mterms2: + # Check if the IoType is 'INPUT' + if mterm.getIoType() == 'INPUT': + # Append the MTerm to the list of input MTerms + input_mterms.append(mterm) + +# Return a tuple containing MTerms of the library cell of instance '_411_' and input MTerms of instance '_411_' +return (mterms1, input_mterms)",Get the MTerms of the library cell of the instance '_411_' and get the list of mterms of the instance 'input1' whose IoType is 'INPUT'. Return the results as a tuple +"# Get the current block of the design +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get the LEF version of the technology +lef_version = tech.getLefVersion() + +# get clearance measure of the technology +clearance_measure = tech.getClearanceMeasure() + +# Set Db units per micron to 1500 for the chip +tech.setDbUnitsPerMicron(1500) + +# Return the clearance measure and the LEF version of the technology +return (clearance_measure, lef_version)",Get the clearance measure and set the Db units per micron to 1500 to the chip and get Lef version. return the result as a tuple. +"# Get the current block of the design +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Find the layer 'metal5' in the technology +layer = tech.findLayer('metal5') + +# Get the upper and lower layers of the layer 'metal5' +upper_lower_layer = { + ""upper"": layer.getUpperLayer(), + ""lower"": layer.getLowerLayer() +} + +# Get the top layer of the IO Placer object of the design +iop = design.getIOPlacer() +iop_top_layer = iop.getTopLayer() + +# Return a tuple containing the upper and lower layer of 'metal5' and the top layer used for the IO pin placer +return (upper_lower_layer, iop_top_layer)","Retrieve the upper and lower layers of the 'metal5' layer and encapsulate them in a dictionary with ""upper"" and ""lower"" as keys. Additionally, retrieve the setting of the top layer used for the IO pin placer. Return the results as a tuple." +"# Get the design block +block = ord.get_db_block() +# Get all instances +insts = block.getInsts() +# Initialize a list to store output pins without nets +output_pin_wout_net = [] +# Iterate over instances +for inst in insts: + # Get all pins of the instance + pins = inst.getITerms() + # Iterate over pins + for pin in pins: + # Check if the pin is an output signal + if pin.isOutputSignal(): + # Get the net connected to the pin + nets = pin.getNet() + # Check if the pin has no net connected + if nets == None: + # Append the pin to the list + output_pin_wout_net.append(pin) +# Check if there are no output pins without nets +if len(output_pin_wout_net) == 0: + return True +else: + return False ",Check if all the output pins of all instances have a valid net connection +"# Get the design block +block = ord.get_db_block() +# Get all instances +insts = block.getInsts() +# Initialize a list to store input pins without nets +input_pin_wout_net = [] +# Iterate over instances +for inst in insts: + # Get all pins of the instance + pins = inst.getITerms() + # Iterate over pins + for pin in pins: + # Check if the pin is an input signal + if pin.isInputSignal(): + # Get the net connected to the pin + nets = pin.getNet() + # Check if the pin has no net connected + if nets == None: + # Append the pin to the list + input_pin_wout_net.append(pin) +# Check if there are no input pins without nets +if len(input_pin_wout_net) == 0: + return True +else: + return False",Check if all the input pins of all instances have a valid net connection +"# Get the design block +block = ord.get_db_block() +# Find the instance ""_split30_"" +inst = block.findInst(""_split30_"") +# Set the instance as don't touch type +inst.setDoNotTouch(True)","Set the instance ""_split30_"" as don't touch type" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""_split30_"" +inst = block.findInst(""_split30_"") +# Set the instance as don't touch type +inst.setDoNotTouch(False)","Reset the instance ""_split30_"" as don't touch type" +"# Get the design block +block = ord.get_db_block() +# Get all instances +insts = block.getInsts() +# Create a list to store pin names +pin_name_list = [] +# Loop through all instances +for inst in insts: + # Get the pins of this instance + inst_ITerms = inst.getITerms() + # Loop through all pins + for ITerm in inst_ITerms: + # Append pin names to the list + pin_name_list.append(design.getITermName(ITerm)) +return pin_name_list",Get the name of every pin +"# Get the placement status of all instances + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a list to store unplaced instances +unplaced_instances = [] + +# Iterate through all instances +for inst in insts: + # Print the instance name and its placement status + print(inst.getName(), inst.getPlacementStatus()) + # Check if the instance is not placed + if not inst.isPlaced(): + # If the instance is not placed, add it to the list of unplaced instances + unplaced_instances.append(inst) + +# Return the list of unplaced instances +return unplaced_instances +",get the all the unplaced instance as a list +"# Get the design block +block = ord.get_db_block() +# Get instances from +insts = block.getInsts() +# Initialize a dictionary to store instances with MUX2_X2 master +mux_ins_dict = {} + +# Iterate over instances +for inst in insts: + # Get the master of the instance + mast = inst.getMaster() + # Check if the master is MUX2_X2 + if 'MUX2_X2' == mast.getName(): + # Check if instance name is already in the dictionary + if inst.getName() not in mux_ins_dict: + mux_ins_dict[inst.getName()] = [mast.getName()] + else: + mux_ins_dict[inst.getName()].append(mast.getName()) + +# Return the dictionary +return mux_ins_dict","Return a dictionary with the keys being the names of all MUX2_X2 cells, and the values being the name of the library cell" +"# Get the nets of all input pins + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a list to store nets of input pins +input_net_list = [] + +# Iterate through all instances +for inst in insts: + # Get all input pins (ITerms) of the instance + pins = inst.getITerms() + # Iterate through all input pins + for pin in pins: + # Check if the pin is an input signal + if pin.isInputSignal(): + # If it's an input signal, add its net to the list + input_net_list.append(pin.getNet()) + +# Return the list of nets of input pins +return input_net_list",Get the nets of all input pins +"# Get the nets of all output pins + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a list to store nets of output pins +output_net_list = [] + +# Iterate through all instances +for inst in insts: + # Get all input pins (ITerms) of the instance + pins = inst.getITerms() + # Iterate through all input pins + for pin in pins: + # Check if the pin is an output signal + if pin.isOutputSignal(): + # If it's an output signal, add its net to the list + output_net_list.append(pin.getNet()) + +# Return the list of nets of output pins +return output_net_list",get the nets of all output pins +"# Get each net's fanout count, in the form of a dictionary, with net name as key and number of fanout as value +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a dictionary to store fanout information +fanout_dict = {} + +# Iterate through all instances +for inst in insts: + # Get all pins (ITerms) of the instance + pins = inst.getITerms() + # Iterate through all pins + for pin in pins: + # Get the net associated with the pin + net = pin.getNet() + # Get the name of the net + name = net.getName() if net else None + # Check if the pin is an input signal + if pin.isInputSignal(): + # If it's an input signal, increment the fanout count for the net + if name in fanout_dict: + fanout_dict[name] += 1 + else: + fanout_dict[name] = 1 + else: + # If it's not an input signal, initialize the fanout count for the net to 0 + if name not in fanout_dict: + fanout_dict[name] = 0 + +# Return the fanout dictionary +return fanout_dict","Get each net's fanout count, in the form of a dictionary, with net name as key and number of fanout as value" +"# Get all the instances on level 0 + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Level to filter instances +level = 0 + +# Initialize a list to store instances on the specified level +insts_on_level = [] + +# Iterate through all instances +for inst in insts: + # Check if the instance's level matches the specified level + if inst.getLevel() == level: + # If it's on the specified level, add it to the list + insts_on_level.append(inst) + +# Return the list of instances on the specified level +return insts_on_level",Get all the instances on level 0 +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input1' as mentioned in the prompt +inst = block.findInst('input20') +# Set the orientation of the instance as ""R0"" +inst.setOrient('R0')",Set the orientation of an instance 'input20' as 'R0' +"# Get the output pins of the instance 'output53' + +# Get the design block +block = design.getBlock() + +# Get all instances +inst = block.findInst('output53') + +# Initialize a variable to store the output pin +output_pins = [] + +# Get all input pins (ITerms) of the instance +pins = inst.getITerms() + +# Iterate through all input pins +for pin in pins: + # Check if the pin is an output signal + if pin and pin.isOutputSignal() : + # If it's an output signal, store it as the output pin + output_pins.append(pin) + +# Return the output pin of the specified instance +return output_pins",get the output pins of the instance 'output53' +"# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a list to store instances with pins set as clocked +clock_insts = [] + +# Iterate through all instances +for inst in insts: + + pins = inst.getITerms() + for pin in pins: + if pin.isClocked(): + clock_insts.append(inst) + +# Return the list of instances with pins set as clocked +return clock_insts",get the instances that have pins set as clocked +"# Get all the pins whose 'IO type' is 'INPUT'. + +# Get the design block +block = design.getBlock() + +# Get all pins (ITerms) +pins = block.getITerms() + +# Initialize a list to store input pins +input_pins = [] + +# Iterate through all pins +for pin in pins: + # Check if the pin's IO type is INPUT + if pin.getIoType() == 'INPUT': + # If it's an input pin, add it to the list + input_pins.append(pin) + +# Return the list of input pins +return input_pins",Get all the pins whose 'IO type' is 'INPUT'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the DB units per micron +return block.getDbUnitsPerMicron()",Convert 1 micron to units used in this technology in OpenROAD +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the DB units per micron +return block.getDbUnitsPerMicron()",Convert 1 micrometer to units used in this technology in OpenROAD +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input1' as mentioned in the prompt +inst = block.findInst(""input1"") +# Check if the user-defined flag 1 of the instance is set true +if inst.getUserFlag1()==True: + # Clear the user flag 1 of the instance + inst.clearUserFlag1()","Clear the user-defined flag 1 on the instance with name ""input1"" if the flag is set" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name 'poly' +layer = tech.findLayer('poly') +# Return the layer above the layer +return layer.getUpperLayer()",Get the layer above the layer with name 'poly' +"# Get the design block +block = ord.get_db_block() +# Get all instances +insts = block.getInsts() +# Initialize a list to store output pins without nets +output_pin_wout_net = [] +# Iterate over instances +for inst in insts: + # Get all pins of the instance + pins = inst.getITerms() + # Iterate over pins + for pin in pins: + # Check if the pin is an output signal + if pin.isOutputSignal(): + # Get the net connected to the pin + nets = pin.getNet() + # Check if the pin has no net connected + if nets == None: + # Append the pin to the list + output_pin_wout_net.append(pin) +# Check if there are no output pins without nets +if len(output_pin_wout_net) == 0: + return True +else: + return False ",Check if all the output pins of all instances have a valid net connection +"# Get the design block +block = ord.get_db_block() +# Get all instances +insts = block.getInsts() +# Initialize a list to store input pins without nets +input_pin_wout_net = [] +# Iterate over instances +for inst in insts: + # Get all pins of the instance + pins = inst.getITerms() + # Iterate over pins + for pin in pins: + # Check if the pin is an input signal + if pin.isInputSignal(): + # Get the net connected to the pin + nets = pin.getNet() + # Check if the pin has no net connected + if nets == None: + # Append the pin to the list + input_pin_wout_net.append(pin) +# Check if there are no input pins without nets +if len(input_pin_wout_net) == 0: + return True +else: + return False",Check if all the input pins of all instances have a valid net connection +"# Get the design block +block = ord.get_db_block() +# Get all nets +nets = block.getNets() +# Define the fanout threshold +gt_fanout = 6 +# Initialize a list to store nets with fanout greater than the threshold +net_fanout = [] +# Iterate over nets +for net in nets: + # Get the name of the net + net_name = net.getName() + # Initialize a list to store output pins + output_pins = [] + # Get all ITerms associated with the net + net_ITerms = net.getITerms() + # Iterate over ITerms + for net_ITerm in net_ITerms: + # Check if the ITerm represents an input signal + if (net_ITerm.isInputSignal()): + # Get the name of the pin + pin_name = design.getITermName(net_ITerm) + # Append the pin name to the list of output pins + output_pins.append(pin_name) + # Check if the number of output pins exceeds the fanout threshold + if len(output_pins) > gt_fanout: + # Append the net name and its fanout to the list + net_fanout.append([net_name, len(output_pins)]) +# Return the list of nets with fanout greater than the threshold +return net_fanout",Give me a list of nets with a fanout greater than 6 +"# Get the design block +block = ord.get_db_block() +# Get all nets +nets = block.getNets() +# Define the fanout threshold +gt_fanout = 6 +# Initialize a list to store nets with fanout greater than the threshold +net_fanout = [] +# Iterate over nets +for net in nets: + # Get the name of the net + net_name = net.getName() + # Initialize a list to store output pins + output_pins = [] + # Get all ITerms associated with the net + net_ITerms = net.getITerms() + # Iterate over ITerms + for net_ITerm in net_ITerms: + # Check if the ITerm represents an input signal + if (net_ITerm.isInputSignal()): + # Get the name of the pin + pin_name = design.getITermName(net_ITerm) + # Append the pin name to the list of output pins + output_pins.append(pin_name) + # Check if the number of output pins exceeds the fanout threshold + if len(output_pins) < gt_fanout: + # Append the net name and its fanout to the list + net_fanout.append([net_name, len(output_pins)]) +# Return the list of nets with fanout greater than the threshold +return net_fanout",Give me a list of nets with a fanout less than 6 +"# Get the design block +block = ord.get_db_block() +# Get all nets +nets = block.getNets() +# Define the fanout threshold +gt_fanout = 5 +# Initialize a list to store nets with fanout greater than the threshold +net_fanout = [] +# Iterate over nets +for net in nets: + # Get the name of the net + net_name = net.getName() + # Initialize a list to store output pins + output_pins = [] + # Get all ITerms associated with the net + net_ITerms = net.getITerms() + # Iterate over ITerms + for net_ITerm in net_ITerms: + # Check if the ITerm represents an input signal + if (net_ITerm.isInputSignal()): + # Get the name of the pin + pin_name = design.getITermName(net_ITerm) + # Append the pin name to the list of output pins + output_pins.append(pin_name) + # Check if the number of output pins exceeds the fanout threshold + if len(output_pins) > gt_fanout: + # Append the net name and its fanout to the list + net_fanout.append([net_name, len(output_pins)]) +# Return the list of nets with fanout greater than the threshold +return net_fanout",Give me a list of nets with a fanout greater than 5 +"# Get the design block +block = ord.get_db_block() +# Get all nets +nets = block.getNets() +# Define the fanout threshold +gt_fanout = 5 +# Initialize a list to store nets with fanout greater than the threshold +net_fanout = [] +# Iterate over nets +for net in nets: + # Get the name of the net + net_name = net.getName() + # Initialize a list to store output pins + output_pins = [] + # Get all ITerms associated with the net + net_ITerms = net.getITerms() + # Iterate over ITerms + for net_ITerm in net_ITerms: + # Check if the ITerm represents an input signal + if (net_ITerm.isInputSignal()): + # Get the name of the pin + pin_name = design.getITermName(net_ITerm) + # Append the pin name to the list of output pins + output_pins.append(pin_name) + # Check if the number of output pins exceeds the fanout threshold + if len(output_pins) < gt_fanout: + # Append the net name and its fanout to the list + net_fanout.append([net_name, len(output_pins)]) +# Return the list of nets with fanout greater than the threshold +return net_fanout",Give me a list of nets with a fanout less than 5 +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the def units to 1500 as mentioned in the prompt +block.setDefUnits(1500)",Set the def units to 1500 +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than or equal 5 ns as mentioned in the prompt + if pin_rise_arr >= 5e-9: + output.append(pin) +return output",Get all the pins which has a pin rising arrival time greater than or equal to 5 ns and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than or equal 132 ps as mentioned in the prompt + if pin_rise_arr >= 1.32e-10: + output.append(pin) +return output",Get all the pins which has a pin rising arrival time greater than or equal to 132 ps and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than or equal 132 picosecond as mentioned in the prompt + if pin_rise_arr >= 1.32e-10: + output.append(pin) +return output",Get all the pins which has a pin rising arrival time greater than or equal to 132 picosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than or equal 5 nanosecond as mentioned in the prompt + if pin_rise_arr >= 5e-9: + output.append(pin) +return output",Get all the pins which has a pin rising arrival time greater than or equal to 5 nanosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than or equal 18 nanosecond as mentioned in the prompt + if pin_rise_arr >= 1.8e-8: + output.append(pin) +return output",Get all the pins which has a pin rising arrival time greater than or equal to 18 nanosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than or equal 18 ns as mentioned in the prompt + if pin_rise_arr >= 1.8e-8: + output.append(pin) +return output",Get all the pins which has a pin rising arrival time greater than or equal to 18 ns and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than or equal 142 ns as mentioned in the prompt + if pin_rise_arr >= 1.42e-7: + output.append(pin) +return output",Get all the pins which has a pin rising arrival time greater than or equal to 142 ns and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than or equal 142 nanosecond as mentioned in the prompt + if pin_rise_arr >= 1.42e-7: + output.append(pin) +return output",Get all the pins which has a pin rising arrival time greater than or equal to 142 nanosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than or equal 321 ns as mentioned in the prompt + if pin_rise_arr >= 3.21e-7: + output.append(pin) +return output",Get all the pins which has a pin rising arrival time greater than or equal to 321 ns and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than or equal 321 nanosecond as mentioned in the prompt + if pin_rise_arr >= 3.21e-7: + output.append(pin) +return output",Get all the pins which has a pin rising arrival time greater than or equal to 321 nanosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than or equal 28 ns as mentioned in the prompt + if pin_rise_arr >= 2.8e-8: + output.append(pin) +return output",Get all the pins which has a pin rising arrival time greater than or equal to 28 ns and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than or equal 28 nanosecond as mentioned in the prompt + if pin_rise_arr >= 2.8e-8: + output.append(pin) +return output",Get all the pins which has a pin rising arrival time greater than or equal to 28 nanosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins connected to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rise arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rise arrival time is greater than or equal 6 nanoseconds as mentioned in the prompt + if pin_rise_arr >= 0.000000006: + output.append(pin) +return output",Get all the pins which has a pin rise arrival time greater than or equal to 6 nanoseconds in the block and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins connected to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rise arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rise arrival time is less than or equal 0.4 second as mentioned in the prompt + if pin_rise_arr <= 0.4: + # Append the pin to the output + output.append(pin) +return output",Get all the pins which has a pin rise arrival time less than or equal to 0.4 seconds in the block and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins connected to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the fall arrival time + pin_fall_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the fall arrival time is less than or equal to 0.1 seconds as mentioned in the prompt + if pin_fall_arr <= 0.1: + # Append the pin to the output + output.append(pin) +return output",Get all the pins which has a pin fall arrival time less than or equal to 0.1 second in the block and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 5 ns as mentioned in the prompt + if pin_rise_arr >= 5e-9: + output.append(pin) +return output",Get all the pins which has a pin falling arrival time greater than or equal to 5 ns and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 132 ps as mentioned in the prompt + if pin_rise_arr >= 1.32e-10: + output.append(pin) +return output",Get all the pins which has a pin falling arrival time greater than or equal to 132 ps and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 132 picosecond + if pin_rise_arr >= 1.32e-10: + output.append(pin) +return output",Get all the pins which has a pin falling arrival time greater than or equal to 132 picosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 5 nanosecond as mentioned in the prompt + if pin_rise_arr >= 5e-9: + output.append(pin) +return output",Get all the pins which has a pin falling arrival time greater than or equal to 5 nanosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 18 nanosecond as mentioned in the prompt + if pin_rise_arr >= 1.8e-8: + output.append(pin) +return output",Get all the pins which has a pin falling arrival time greater than or equal to 18 nanosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 18 ns as mentioned in the prompt + if pin_rise_arr >= 1.8e-8: + output.append(pin) +return output",Get all the pins which has a pin falling arrival time greater than or equal to 18 ns and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 142 ns as mentioned in the prompt + if pin_rise_arr >= 1.42e-7: + output.append(pin) +return output",Get all the pins which has a pin falling arrival time greater than or equal to 142 ns and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 142 nanosecond as mentioned in the prompt + if pin_rise_arr >= 1.42e-7: + output.append(pin) +return output",Get all the pins which has a pin falling arrival time greater than or equal to 142 nanosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins connected to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_fall_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is less than or equal to 0.1 seconds as mentioned in the prompt + if pin_fall_arr <= 0.1: + # Append the pin to the output + output.append(pin) +return output",Get all the pins which has a falling arrival time less than or equal to 0.1 second in the block and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 8 ns as mentioned in the prompt + if pin_rise_arr >= 8e-9: + output.append(pin) +return output",Get all the pins which has a falling arrival time greater than or equal to 8 ns and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 118 ps as mentioned in the prompt + if pin_rise_arr >= 1.18e-10: + output.append(pin) +return output",Get all the pins which has a falling arrival time greater than or equal to 118 ps and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 118 picosecond + if pin_rise_arr >= 1.18e-10: + output.append(pin) +return output",Get all the pins which has a falling arrival time greater than or equal to 118 picosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 9 nanosecond as mentioned in the prompt + if pin_rise_arr >= 9e-9: + output.append(pin) +return output",Get all the pins which has a falling arrival time greater than or equal to 9 nanosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 18 nanosecond as mentioned in the prompt + if pin_rise_arr >= 0.000000018: + output.append(pin) +return output",Get all the pins which has a falling arrival time greater than or equal to 18 nanosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 18 ns as mentioned in the prompt + if pin_rise_arr >= 0.000000018: + output.append(pin) +return output",Get all the pins which has a falling arrival time greater than or equal to 18 ns and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 142 ns as mentioned in the prompt + if pin_rise_arr >= 0.000000142: + output.append(pin) +return output",Get all the pins which has a falling arrival time greater than or equal to 142 ns and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins belong to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the falling arrival time is greater than or equal 142 nanosecond as mentioned in the prompt + if pin_rise_arr >= 0.000000142: + output.append(pin) +return output",Get all the pins which has a falling arrival time greater than or equal to 142 nanosecond and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""input2"" as mentioned in the prompt +inst = block.findInst(""input2"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the X Minimum of the bounding box of the instance +xmin = BBox.xMin() +# Get the Y Minimum of the bounding box of the instance +ymin = BBox.yMin() +# Get the X Maximum of the bounding box of the instance +xmax = BBox.xMax() +# Get the Y Maximum of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","Give me the bounding box of the instance ""input2"", and provide a list of coordinates, with (Xmin, Ymin) in one list, and (Xmax, Ymax) in the next list" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""input2"" as mentioned in the prompt +inst = block.findInst(""input2"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the x_min of the bounding box of the instance +xmin = BBox.xMin() +# Get the y_min of the bounding box of the instance +ymin = BBox.yMin() +# Get the x_max of the bounding box of the instance +xmax = BBox.xMax() +# Get the y_max of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","Retrieve the bounding box of the instance ""input2"", and provide a list of coordinates, with (x_min, y_min) in one list, and (x_max, y_max) in the next list" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""_cell1\_124_"" +inst = block.findInst(""_cell1\_124_"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the X Minimum of the bounding box of the instance +xmin = BBox.xMin() +# Get the Y Minimum of the bounding box of the instance +ymin = BBox.yMin() +# Get the X Maximum of the bounding box of the instance +xmax = BBox.xMax() +# Get the Y Maximum of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","Retrieve the bounding box of the instance ""_cell1\_124_"", and provide a list of coordinates, with (Xmin, Ymin) in one list, and (Xmax, Ymax) in the next list" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""_cell1\_124_"" +inst = block.findInst(""_cell1\_124_"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the x_min of the bounding box of the instance +xmin = BBox.xMin() +# Get the y_min of the bounding box of the instance +ymin = BBox.yMin() +# Get the x_max of the bounding box of the instance +xmax = BBox.xMax() +# Get the y_max of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","Retrieve the bounding box of the instance ""_cell1\_124_"", and provide a list of coordinates, with (x_min, y_min) in one list, and (x_max, y_max) in the next list" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""_buff132_"" +inst = block.findInst(""_buff132_"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the X Minimum of the bounding box of the instance +xmin = BBox.xMin() +# Get the Y Minimum of the bounding box of the instance +ymin = BBox.yMin() +# Get the X Maximum of the bounding box of the instance +xmax = BBox.xMax() +# Get the Y Maximum of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","Give me the bounding box of the instance ""_buff132_"", and provide a list of coordinates, with (Xmin, Ymin) in one list, and (Xmax, Ymax) in the next list" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""_buff132_"" +inst = block.findInst(""_buff132_"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the x_min of the bounding box of the instance +xmin = BBox.xMin() +# Get the y_min of the bounding box of the instance +ymin = BBox.yMin() +# Get the x_max of the bounding box of the instance +xmax = BBox.xMax() +# Get the y_max of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","Retrieve the bounding box of the instance ""_buff132_"", and provide a list of coordinates, with (x_min, y_min) in one list, and (x_max, y_max) in the next list" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""_buff132_"" +inst = block.findInst(""_buff132_"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the Min_x of the bounding box of the instance +xmin = BBox.xMin() +# Get the Min_y of the bounding box of the instance +ymin = BBox.yMin() +# Get the Max_x of the bounding box of the instance +xmax = BBox.xMax() +# Get the Max_y of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","Retrieve the bounding box of the instance ""_buff132_"", and provide a list of coordinates, with (Min_x, Min_y) in one list, and (Max_x, Max_y) in the next list" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""_buff132_"" +inst = block.findInst(""_buff132_"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the min_x of the bounding box of the instance +xmin = BBox.xMin() +# Get the min_y of the bounding box of the instance +ymin = BBox.yMin() +# Get the max_x of the bounding box of the instance +xmax = BBox.xMax() +# Get the max_y of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","Retrieve the bounding box of the instance ""_buff132_"", and provide a list of coordinates, with (min_x, min_y) in one list, and (max_x, max_y) in the next list" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""temp_inst"" +inst = block.findInst(""temp_inst"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the Min_x of the bounding box of the instance +xmin = BBox.xMin() +# Get the Min_y of the bounding box of the instance +ymin = BBox.yMin() +# Get the Max_x of the bounding box of the instance +xmax = BBox.xMax() +# Get the Max_y of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","Retrieve the bounding box of the instance ""temp_inst"", and provide a list of coordinates, with (Min_x, Min_y) in one list, and (Max_x, Max_y) in the next list" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""temp_inst"" +inst = block.findInst(""temp_inst"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the min_x of the bounding box of the instance +xmin = BBox.xMin() +# Get the min_y of the bounding box of the instance +ymin = BBox.yMin() +# Get the max_x of the bounding box of the instance +xmax = BBox.xMax() +# Get the max_y of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","Give me the bounding box of the instance ""temp_inst"", and provide a list of coordinates, with (min_x, min_y) in one list, and (max_x, max_y) in the next list" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""inst01"" +inst = block.findInst(""inst01"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the Min_x of the bounding box of the instance +xmin = BBox.xMin() +# Get the Min_y of the bounding box of the instance +ymin = BBox.yMin() +# Get the Max_x of the bounding box of the instance +xmax = BBox.xMax() +# Get the Max_y of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","How can I get the bounding box of the instance ""inst01"", and provide a list of coordinates, with (Min_x, Min_y) in one list, and (Max_x, Max_y) in the next list?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""temp_inst"" +inst = block.findInst(""temp_inst"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the min_x of the bounding box of the instance +xmin = BBox.xMin() +# Get the min_y of the bounding box of the instance +ymin = BBox.yMin() +# Get the max_x of the bounding box of the instance +xmax = BBox.xMax() +# Get the max_y of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","How can I get the bounding box of the instance ""temp_inst"", and provide a list of coordinates, with (min_x, min_y) in one list, and (max_x, max_y) in the next list?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""_cell1\_124_"" +inst = block.findInst(""_cell1\_124_"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the X Minimum of the bounding box of the instance +xmin = BBox.xMin() +# Get the Y Minimum of the bounding box of the instance +ymin = BBox.yMin() +# Get the X Maximum of the bounding box of the instance +xmax = BBox.xMax() +# Get the Y Maximum of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","How can I get the bounding box of the instance ""_cell1\_124_"", and provide a list of coordinates, with (Xmin, Ymin) in one list, and (Xmax, Ymax) in the next list?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name ""_cell1\_124_"" +inst = block.findInst(""_cell1\_124_"") +# Get the Bounding box of the instance +BBox = inst.getBBox() +# Get the x minimum of the bounding box of the instance +xmin = BBox.xMin() +# Get the y minimum of the bounding box of the instance +ymin = BBox.yMin() +# Get the x maximum of the bounding box of the instance +xmax = BBox.xMax() +# Get the y maximum of the bounding box of the instance +ymax = BBox.yMax() +return [[xmin,ymin],[xmax,ymax]]","How can I get the bounding box of the instance ""_cell1\_124_"", and provide a list of coordinates, with (xmin, ymin) in one list, and (xmax, ymax) in the next list?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the DEF units of this technology to 1200 as mentioned in the prompt +block.setDefUnits(1200)",Establish the units per micron as 1200. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the DEF units of this technology to 1200 as mentioned in the prompt +block.setDefUnits(1200)",Set the units per micron to 1200. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the DEF units of this technology to 1200 as mentioned in the prompt +block.setDefUnits(1200)",Set the DEF units of this technology to 1200. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the DEF units of this technology to 1200 as mentioned in the prompt +block.setDefUnits(1200)",How can I set the DEF units of this technology to 1200? +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the DEF units of this technology to 1600 as mentioned in the prompt +block.setDefUnits(1600)",Establish the units per micron as 1600. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the DEF units of this technology to 1600 as mentioned in the prompt +block.setDefUnits(1600)",Set the units per micron to 1600. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the DEF units of this technology to 1600 as mentioned in the prompt +block.setDefUnits(1600)",Set the DEF units of this technology to 1600. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the DEF units of this technology to 1600 as mentioned in the prompt +block.setDefUnits(1600)",How can I set the DEF units of this technology to 1600? +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the DEF units of this technology to 1500 as mentioned in the prompt +block.setDefUnits(1500)",Establish the units per micron as 1500. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the DEF units of this technology to 1500 as mentioned in the prompt +block.setDefUnits(1500)",Set the units per micron to 1500. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the DEF units of this technology to 1500 as mentioned in the prompt +block.setDefUnits(1500)",Set the DEF units of this technology to 1500. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the DEF units of this technology to 1500 as mentioned in the prompt +block.setDefUnits(1500)",How can I set the DEF units of this technology to 1500? +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input2' as mentioned in the prompt +inst = block.findInst(""input2"") +inst.setUserFlag1()","Assign the value of true for user-defined flag 1 for the instance named ""input2""." +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find an instance with name 'input3' as mentioned in the prompt +inst = block.findInst('input3') +# Get all the pins connected to an instance +pins = inst.getITerms() +# Initialize a nets array +nets = [] +# Iterate through all the pins +for pin in pins: + # Get the net the pin + nets.append(pin.getNet()) +# Initialize the count with 0 +count = 0 +# Iterate through all the nets +for net in nets: + # Check if the wire is replaced with a new wire + if net.isWireAltered(): + # Increase the count + count+=1 +return count",Provide the count of modified nets connected to the instance 'input3'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find an instance with name '_cell1\_124_' as mentioned in the prompt +inst = block.findInst('_cell1\_124_') +# Get all the pins connected to an instance +pins = inst.getITerms() +# Initialize a nets array +nets = [] +# Iterate through all the pins +for pin in pins: + # Get the net the pin + nets.append(pin.getNet()) +# Initialize the count with 0 +count = 0 +# Iterate through all the nets +for net in nets: + # Check if the wire is replaced with a new wire + if net.isWireAltered(): + # Increase the count + count+=1 +return count",Provide the count of modified nets connected to the instance '_cell1\_124_'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find an instance with name '_buff132_' +inst = block.findInst('_buff132_') +# Get all the pins connected to an instance +pins = inst.getITerms() +# Initialize a nets array +nets = [] +# Iterate through all the pins +for pin in pins: + # Get the net the pin + nets.append(pin.getNet()) +# Initialize the count with 0 +count = 0 +# Iterate through all the nets +for net in nets: + # Check if the wire is replaced with a new wire + if net.isWireAltered(): + # Increase the count + count+=1 +return count",Provide the count of modified nets connected to the instance '_buff132_'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find an instance with name 'input2' +inst = block.findInst('input2') +# Get all the pins connected to an instance +pins = inst.getITerms() +# Initialize a nets array +nets = [] +# Iterate through all the pins +for pin in pins: + # Get the net the pin + nets.append(pin.getNet()) +# Initialize the count with 0 +count = 0 +# Iterate through all the nets +for net in nets: + # Check if the wire is replaced with a new wire + if net.isWireAltered(): + # Increase the count + count+=1 +return count",Provide the count of modified nets connected to the instance 'input2'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find an instance with name 'input4' as mentioned in the prompt +inst = block.findInst('input4') +# Get all the pins connected to an instance +pins = inst.getITerms() +nets = [] +# Iterate through all the pins +for pin in pins: + # Get the net the pin + nets.append(pin.getNet()) +# Iterate through all the nets +for net in nets: + # Check if the wire is altered + if net.isWireAltered(): + return True +return False","Examine all nets connected to the instance 'input4' to see if any have been modified. Return True if modified, and False otherwise." +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find an instance with name '_buff132_' as mentioned in the prompt +inst = block.findInst('_buff132_') +# Get all the pins connected to an instance +pins = inst.getITerms() +nets = [] +# Iterate through all the pins +for pin in pins: + # Get the net the pin + nets.append(pin.getNet()) +# Iterate through all the nets +for net in nets: + # Check if the wire is altered + if net.isWireAltered(): + return True +return False","Examine all nets connected to the instance '_buff132_' to see if any have been modified. Return True if modified, and False otherwise." +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find an instance with name '_buff132_' +inst = block.findInst('_buff132_') +# Get all the pins connected to an instance +pins = inst.getITerms() +nets = [] +# Iterate through all the pins +for pin in pins: + # Get the net the pin + nets.append(pin.getNet()) +# Iterate through all the nets +for net in nets: + # Check if the wire is altered + if net.isWireAltered(): + return True +return False","Help me write a piece of code that examine all nets connected to the instance '_buff132_' to see if any have been modified. Return True if modified, and False otherwise." +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find an instance with name '_cell1\_124_' +inst = block.findInst('_cell1\_124_') +# Get all the pins connected to an instance +pins = inst.getITerms() +nets = [] +# Iterate through all the pins +for pin in pins: + # Get the net the pin + nets.append(pin.getNet()) +# Iterate through all the nets +for net in nets: + # Check if the wire is altered + if net.isWireAltered(): + return True +return False","Examine all nets connected to the instance '_cell1\_124_' to see if any have been modified. Return True if modified, and False otherwise." +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find an instance with name '_cell1\_124_' as mentioned in the prompt +inst = block.findInst('_cell1\_124_') +# Get all the pins connected to an instance +pins = inst.getITerms() +nets = [] +# Iterate through all the pins +for pin in pins: + # Get the net the pin + nets.append(pin.getNet()) +# Iterate through all the nets +for net in nets: + # Check if the wire is altered + if net.isWireAltered(): + return True +return False","Help me write a piece of code that examine all nets connected to the instance '_cell1\_124_' to see if any have been modified. Return True if modified, and False otherwise." +"# Get the design block +block = ord.get_db_block() +# Find the instance ""input03"" +inst = block.findInst(""input03"") +# Set the instance as don't touch type +inst.setDoNotTouch(True)","Set the instance ""input03"" as don't touch type" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""input03"" +inst = block.findInst(""input03"") +# Set the instance as don't touch type +inst.setDoNotTouch(True)","How can I set the instance ""input03"" as don't touch?" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""_cell1\_124_"" +inst = block.findInst(""_cell1\_124_"") +# Set the instance as don't touch type +inst.setDoNotTouch(True)","Set the instance ""_cell1\_124_"" as don't touch type" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""_cell1\_124_"" +inst = block.findInst(""_cell1\_124_"") +# Set the instance as don't touch type +inst.setDoNotTouch(True)","How can I set the instance ""_cell1\_124_"" as don't touch?" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""input03"" +inst = block.findInst(""input03"") +# Reset the instance's don't touch flag +inst.setDoNotTouch(False)","Reset the instance ""input03""'s don't touch flag" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""input03"" +inst = block.findInst(""input03"") +# Reset the instance's don't touch flag +inst.setDoNotTouch(False)","How can I reset the instance ""input03""'s don't touch flag?" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""_cell1\_124_"" +inst = block.findInst(""_cell1\_124_"") +# Reset the instance's don't touch flag +inst.setDoNotTouch(False)","Reset the instance ""_cell1\_124_""'s don't touch flag" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""_cell1\_124_"" +inst = block.findInst(""_cell1\_124_"") +# Reset the instance's don't touch flag +inst.setDoNotTouch(False)","How can I reset the instance ""_cell1\_124_""'s don't touch flag?" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""input03"" +inst = block.findInst(""input03"") +# Reset the instance's don't touch flag +inst.setDoNotTouch(False)","Reset the instance ""input03""'s don't touch setting" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""input03"" +inst = block.findInst(""input03"") +# Reset the instance's don't touch flag +inst.setDoNotTouch(False)","How can I reset the instance ""input03""'s don't touch setting?" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""_cell1\_124_"" +inst = block.findInst(""_cell1\_124_"") +# Reset the instance's don't touch flag +inst.setDoNotTouch(False)","Reset the instance ""_cell1\_124_""'s don't touch setting" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""_cell1\_124_"" +inst = block.findInst(""_cell1\_124_"") +# Reset the instance's don't touch flag +inst.setDoNotTouch(False)","How can I reset the instance ""_cell1\_124_""'s don't touch setting?" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""input03"" +inst = block.findInst(""input03"") +# Reset the instance's don't touch flag +inst.setDoNotTouch(False)","Reset the don't touch setting of instance ""input03""" +"# Get the design block +block = ord.get_db_block() +# Find the instance ""input03"" +inst = block.findInst(""input03"") +# Reset the instance's don't touch flag +inst.setDoNotTouch(False)","How can I reset the don't touch setting of instance ""input03""?" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Return the number of layers in this technology. +return tech.getLayerCount()",Retrieve the count of layers in this technology. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Return the number of layers in this technology. +return tech.getLayerCount()",How can I get the count of layers in this technology? +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Return the number of layers in this technology. +return tech.getLayerCount()",Write a piece of code help me get the amount of layers in this technology +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Return the count of types of vias supported by this technology. +return tech.getViaCount()",Retrieve the count of types of vias supported by this technology. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Return the count of types of vias supported by this technology. +return tech.getViaCount()",How can I get the count of types of vias supported by this technology? +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Return the count of types of vias supported by this technology. +return tech.getViaCount()",Write a piece of code to get the count of types of vias supported by this technology. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Find the 'metal1' layer +layer = tech.findLayer('metal1') +# Return the layer above the layer +return layer.getUpperLayer()",Retrieve the layer above the layer named 'metal1'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Find the 'M3' layer +layer = tech.findLayer('M3') +# Return the layer above the layer +return layer.getUpperLayer()",Give me the technology layer above the layer named 'M3'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Find the 'metal1' layer +layer = tech.findLayer('metal1') +# Return the layer above the layer +return layer.getUpperLayer()",Help me get the layer above the layer named 'metal1'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Find the 'metal2' layer +layer = tech.findLayer('metal2') +# Return the layer above the layer +return layer.getUpperLayer()",How can I get the layer above the layer named 'metal2'? +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Find the 'Via3' layer +layer = tech.findLayer('Via3') +# Return the layer above the layer +return layer.getUpperLayer()",Give me the technology layer above the layer named 'Via3'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Find the 'via3' layer +layer = tech.findLayer('via3') +# Return the layer above the layer +return layer.getUpperLayer()",Give me the technology layer above the layer named 'via3'. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology info +tech = block.getTech() +# Find the 'M4' layer +layer = tech.findLayer('M4') +# Return the layer above the layer +return layer.getUpperLayer()",Help me get the layer above the layer named 'M4'. +"# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Name of the instance to check the placement status +inst_name = 'FILLER_0_3_49' + +# Iterate through all instances +for inst in insts: + # Check if the instance name matches the target instance + if inst.getName() == inst_name: + # Return the placement status of the instance + return inst.isPlaced()",Verify if the instance 'FILLER_0_3_49' is placed or not +"# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Name of the instance to check the placement status +inst_name = 'input3' + +# Iterate through all instances +for inst in insts: + # Check if the instance name matches the target instance + if inst.getName() == inst_name: + # Return the placement status of the instance + return inst.isPlaced()",Verify if the instance 'input3' is placed or not +"# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Name of the instance to check the placement status +inst_name = 'input3' + +# Iterate through all instances +for inst in insts: + # Check if the instance name matches the target instance + if inst.getName() == inst_name: + # Return the placement status of the instance + return inst.isPlaced()",How can I know if the instance 'input3' is placed or not? +"# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Name of the instance to check the placement status +inst_name = 'input3' + +# Iterate through all instances +for inst in insts: + # Check if the instance name matches the target instance + if inst.getName() == inst_name: + # Return the placement status of the instance + return inst.isPlaced()",Help me write a piece of script to know if the instance 'input3' is placed or not +"# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Name of the instance to check the placement status +inst_name = 'cell_12\132' + +# Iterate through all instances +for inst in insts: + # Check if the instance name matches the target instance + if inst.getName() == inst_name: + # Return the placement status of the instance + return inst.isPlaced()",Help me write a piece of script to know if the instance 'cell_12\132' is placed or not +"# Get the design block +block = design.getBlock() + +# Find the instance with name 'PHY_21' +inst = block.findInst('PHY_21') + +# Get the MTerms +mterms = inst.getMaster().getMTerms() + +# Return the MTerms +return mterms +"," +# Retrieve the MTerms of the master cell of the instance 'PHY_21'" +"# Get the design block +block = design.getBlock() + +# Retrieve all instances +insts = block.getInsts() + +# Initialize an empty list to store instances with INV_X1 cell +inst_list = [] + +# Iterate over each instance in the design +for inst in insts: + # Get the master of the current instance + master = inst.getMaster() + # Check if the master's name matches ""INV_X1"" + if master.getName() == ""INV_X1"": + # Append the current instance to the list + inst_list.append(inst) + +# Return the list of instances with INV_X1 cell +return inst_list",get the instances with INV_X1 cell +"# Get length and width of the bounding box of the instance '_590_' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('_590_') + +# Get the length and width of the bounding box of the instance +length = inst.getBBox().getLength() +width = inst.getBBox().getWidth() + +# Return the length and width +return (length, width)",Help me get the length and width of the bounding box of the instance '_590_' +"# Get length and width of the bounding box of the instance '_590_' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('_590_') + +# Get the length and width of the bounding box of the instance +length = inst.getBBox().getLength() +width = inst.getBBox().getWidth() + +# Return the length and width +return (length, width)",How can I get the length and width of the bounding box of the instance '_590_'? +"# Get length and width of the bounding box of the instance 'input118' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input118') + +# Get the length and width of the bounding box of the instance +length = inst.getBBox().getLength() +width = inst.getBBox().getWidth() + +# Return the length and width +return (length, width)",Help me get the length and width of the bounding box of the instance 'input118' +"# Get length and width of the bounding box of the instance 'input118' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('input118') + +# Get the length and width of the bounding box of the instance +length = inst.getBBox().getLength() +width = inst.getBBox().getWidth() + +# Return the length and width +return (length, width)",How can I get the length and width of the bounding box of the instance 'input118'? +"# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store offset of 'MUX2_X1' +offset_dict = {} + +# Iterate through instances +for inst in insts: + # Check if the master cell name contains 'MUX2_X1' + if inst.getMaster().getName() == ""MUX2_X1"": + # Get the offset + transform = inst.getTransform() + offset_dict[inst.getName()] = transform.getOffset() + +# Return dictionary +return offset_dict",get the offset of the instances whose library cell is 'MUX2_X1' +"# Get the IoType of the MTerms of the instance '_575_' + +# Get the design block +block = design.getBlock() + +# Find the instance with name '_575_' +inst = block.findInst('_575_') + +# Get the MTerms of the master cell +mterms = inst.getMaster().getMTerms() + +# Initialize a dictionary to store IoTypes +iotype_dict = {} + +# Iterate through all MTerms +for term in mterms: + # Store the IoType of each term in the dictionary + iotype_dict[term.getName()] = term.getIoType() + +# Return the dictionary containing IoTypes +return iotype_dict",get the IoType of the mterms of the instance '_575_' +"# Get the IoType of the MTerms of the instance 'split22' + +# Get the design block +block = design.getBlock() + +# Find the instance with name 'split22' +inst = block.findInst('split22') + +# Get the MTerms of the master cell +mterms = inst.getMaster().getMTerms() + +# Initialize a dictionary to store IoTypes +iotype_dict = {} + +# Iterate through all MTerms +for term in mterms: + # Store the IoType of each term in the dictionary + iotype_dict[term.getName()] = term.getIoType() + +# Return the dictionary containing IoTypes +return iotype_dict",get the IoType of the mterms of the instance 'split22' +"# Get the IoType of the MTerms of the instance 'split22' + +# Get the design block +block = design.getBlock() + +# Find the instance with name 'split22' +inst = block.findInst('split22') + +# Get the MTerms of the master cell +mterms = inst.getMaster().getMTerms() + +# Initialize a dictionary to store IoTypes +iotype_dict = {} + +# Iterate through all MTerms +for term in mterms: + # Store the IoType of each term in the dictionary + iotype_dict[term.getName()] = term.getIoType() + +# Return the dictionary containing IoTypes +return iotype_dict",How can I get the IoType of the mterms of the instance 'split22'? +"# Check if the instance '_373_' has any pin set as clocked + +# Get the design block +block = design.getBlock() + +# Find the instance '_373_' +inst = block.findInst('_373_') + +# Get all pins of the instance +pins = inst.getITerms() + +# List to store pins are set as clocked +clocked_ports = [] + +# Check if any pin is set as clocked +for pin in pins: + if pin.isClocked(): + clocked_ports.append(pin) + +# Return clocked ports +return clocked_ports",Check if the instance '_373_' has any pin set as clocked +"# Check if the instance '_373_' has any pin set as clocked + +# Get the design block +block = design.getBlock() + +# Find the instance '_373_' +inst = block.findInst('_373_') + +# Get all pins of the instance +pins = inst.getITerms() + +# List to store pins are set as clocked +clocked_ports = [] + +# Check if any pin is set as clocked +for pin in pins: + if pin.isClocked(): + clocked_ports.append(pin) + +# Return clocked ports +return clocked_ports",How can I know if the instance '_373_' has any pin set as clocked? +"# Check if the instance 'input112' has any pin set as clocked + +# Get the design block +block = design.getBlock() + +# Find the instance 'input112' +inst = block.findInst('input112') + +# Get all pins of the instance +pins = inst.getITerms() + +# List to store pins are set as clocked +clocked_ports = [] + +# Check if any pin is set as clocked +for pin in pins: + if pin.isClocked(): + clocked_ports.append(pin) + +# Return clocked ports +return clocked_ports",How can I know if the instance 'input112' has any pin set as clocked? +"# Get the design block +block = ord.get_db_block() +# Initialize a list to store clock nets +clock_nets = [] +# Get all nets +nets = block.getNets() +# Iterate over nets +for net in nets: + # Check if the net is a CLOCK net + if net.getSigType() == 'CLOCK': + # Check if the net is a CLOCK net + clock_nets.append(net) +# Check if CLOCK nets exist +if len(clock_nets) > 0: + return True +else: + return False",How can I know if the design has any clock nets? +"# Get the design block +block = ord.get_db_block() +# Initialize a list to store clock nets +clock_nets = [] +# Get all nets +nets = block.getNets() +# Iterate over nets +for net in nets: + # Check if the net is a CLOCK net + if net.getSigType() == 'CLOCK': + # Check if the net is a CLOCK net + clock_nets.append(net) +# Check if CLOCK nets exist +if len(clock_nets) > 0: + return True +else: + return False",Writre a piece of code to see if the design has any clock nets +"# Get the design block +block = ord.get_db_block() +# Initialize a list to store clock nets +clock_nets = [] +# Get all nets +nets = block.getNets() +# Iterate over nets +for net in nets: + # Check if the net is a CLOCK net + if net.getSigType() == 'CLOCK': + # Check if the net is a CLOCK net + clock_nets.append(net) +# Check if CLOCK nets exist +if len(clock_nets) > 0: + return True +else: + return False",Give me the code to see if the design has any clock nets using OpenROAD Python API +"# Get the IoType of the MTerms of the instance 'split22' + +# Get the design block +block = design.getBlock() + +# Find the instance with name 'split22' +inst = block.findInst('split22') + +# Get the MTerms of the master cell +mterms = inst.getMaster().getMTerms() + +# Initialize a dictionary to store IoTypes +iotype_dict = {} + +# Iterate through all MTerms +for term in mterms: + # Store the IoType of each term in the dictionary + iotype_dict[term.getName()] = term.getIoType() + +# Return the dictionary containing IoTypes +return iotype_dict",get the IoType of the mterms of the instance 'split22' using OpenROAD Python API +"# Get the IoType of the MTerms of the instance 'split22' + +# Get the design block +block = design.getBlock() + +# Find the instance with name 'split22' +inst = block.findInst('split22') + +# Get the MTerms of the master cell +mterms = inst.getMaster().getMTerms() + +# Initialize a dictionary to store IoTypes +iotype_dict = {} + +# Iterate through all MTerms +for term in mterms: + # Store the IoType of each term in the dictionary + iotype_dict[term.getName()] = term.getIoType() + +# Return the dictionary containing IoTypes +return iotype_dict",How can I get the IoType of the mterms of the instance 'split22' using OpenROAD Python API? +"# Get the design block +block = ord.get_db_block() +# Get all instances +insts = block.getInsts() +# Create a list to store pin names +pin_name_list = [] +# Loop through all instances +for inst in insts: + # Get the pins of this instance + inst_ITerms = inst.getITerms() + # Loop through all pins + for ITerm in inst_ITerms: + # Append pin names to the list + pin_name_list.append(design.getITermName(ITerm)) +return pin_name_list",How can I put the name of every pin into a list? +"# Get the design block +block = ord.get_db_block() +# Get all instances +insts = block.getInsts() +# Create a list to store pin names +pin_name_list = [] +# Loop through all instances +for inst in insts: + # Get the pins of this instance + inst_ITerms = inst.getITerms() + # Loop through all pins + for ITerm in inst_ITerms: + # Append pin names to the list + pin_name_list.append(design.getITermName(ITerm)) +return pin_name_list",Show me how to put every pin's name into a list +"# Get the design block +block = ord.get_db_block() +# Get all instances +insts = block.getInsts() +# Create a list to store the name of the instance and its bottom-left corner and top-right corner's location +inst_name_location_list = [] +# Loop through all instances +for inst in insts: + # Get the properties + cell_name = inst.getName() + BBox = inst.getBBox() + inst_x0 = BBox.xMin() + inst_y0 = BBox.yMin() + inst_x1 = BBox.xMax() + inst_y1 = BBox.yMax() + inst_name_location_list.append([cell_name, inst_x0, inst_y0, inst_x1, inst_y1]) +return inst_name_location_list",Get the bounding box of all instances +"# Get the design block +block = ord.get_db_block() +# Get all instances +insts = block.getInsts() +# Create a list to store the name of the instance and its bottom-left corner and top-right corner's location +inst_name_location_list = [] +# Loop through all instances +for inst in insts: + # Get the properties + cell_name = inst.getName() + BBox = inst.getBBox() + inst_x0 = BBox.xMin() + inst_y0 = BBox.yMin() + inst_x1 = BBox.xMax() + inst_y1 = BBox.yMax() + inst_name_location_list.append([cell_name, inst_x0, inst_y0, inst_x1, inst_y1]) +return inst_name_location_list","How to get a list of lists, with each inner list containing the name, the bottom-left corner, and the top-right corner locations of each instance?" +"# Get the design block +block = ord.get_db_block() +# Get all instances +insts = block.getInsts() +# Create a list to store the name of the instance and its bottom-left corner and top-right corner's location +inst_name_location_list = [] +# Loop through all instances +for inst in insts: + # Get the properties + cell_name = inst.getName() + BBox = inst.getBBox() + inst_x0 = BBox.xMin() + inst_y0 = BBox.yMin() + inst_x1 = BBox.xMax() + inst_y1 = BBox.yMax() + inst_name_location_list.append([cell_name, inst_x0, inst_y0, inst_x1, inst_y1]) +return inst_name_location_list","Show me how I can get a list of lists, with each inner list containing the name, the bottom-left corner, and the top-right corner locations of each instance." +"# Get the design block +block = ord.get_db_block() +# Get every instance +insts = block.getInsts() +# Create an empty list to store all cell_name-library_cell_name pair +inst_name_libcell_list = [] +# Loop through all instances +for inst in insts: + # Get the name of the cell + cell_name = inst.getName() + # Get the master of this instance + master_cell = inst.getMaster() + # Get the master name (library cell name) of this instance + master_name = master_cell.getName() + # Append them into a list + inst_name_libcell_list.append([cell_name, master_name]) +return inst_name_libcell_list",Get the liberty cell type for all instance +"# Get the design block +block = ord.get_db_block() +# Get every instance +insts = block.getInsts() +# Create an empty list to store all cell_name-library_cell_name pair +inst_name_libcell_list = [] +# Loop through all instances +for inst in insts: + # Get the name of the cell + cell_name = inst.getName() + # Get the master of this instance + master_cell = inst.getMaster() + # Get the master name (library cell name) of this instance + master_name = master_cell.getName() + # Append them into a list + inst_name_libcell_list.append([cell_name, master_name]) +return inst_name_libcell_list",Show me how I can get the liberty cell type for all instance in a list +"# Get the design block +block = ord.get_db_block() +# Get every instance +insts = block.getInsts() +# Create a list to store the result +inst_name_macro_list = [] +# Loop through all instances +for inst in insts: + # Get the name of the cell + cell_name = inst.getName() + # Get the master of this cell + master_cell = inst.getMaster() + # Check is the cell is a macro + is_macro = 1 if master_cell.isBlock() else 0 + # Append the result + inst_name_macro_list.append([cell_name, is_macro]) +return inst_name_macro_list",check if an instance is a macro in the design +"# Get the design block +block = ord.get_db_block() +# Get every instance +insts = block.getInsts() +# Create an empty list to store all cell_name-library_cell_name pair +inst_name_libcell_list = [] +# Loop through all instances +for inst in insts: + # Get the name of the cell + cell_name = inst.getName() + # Get the master of this instance + master_cell = inst.getMaster() + # Get the master name (library cell name) of this instance + master_name = master_cell.getName() + # Append them into a list + inst_name_libcell_list.append([cell_name, master_name]) +return inst_name_libcell_list",How can I get the liberty cell type for all instance in a list? +"# Get the design block +block = ord.get_db_block() +# Get every instance +insts = block.getInsts() +# Create a list to store the result +inst_name_macro_list = [] +# Loop through all instances +for inst in insts: + # Get the name of the cell + cell_name = inst.getName() + # Get the master of this cell + master_cell = inst.getMaster() + # Check is the cell is a macro + is_macro = 1 if master_cell.isBlock() else 0 + # Append the result + inst_name_macro_list.append([cell_name, is_macro]) +return inst_name_macro_list",How can I identify if a cell is a macro? +"# Get the design block +block = ord.get_db_block() +# Get every instance +insts = block.getInsts() +# Create a list to store the result +inst_name_macro_list = [] +# Loop through all instances +for inst in insts: + # Get the name of the cell + cell_name = inst.getName() + # Get the master of this cell + master_cell = inst.getMaster() + # Check is the cell is a macro + is_macro = 1 if master_cell.isBlock() else 0 + # Append the result + inst_name_macro_list.append([cell_name, is_macro]) +return inst_name_macro_list","Write a script to separate standard cells and macros in the design, show the result in a list." +"# Get the design block +block = ord.get_db_block() +# Get every instance +insts = block.getInsts() +# Create a list to store the result +pin_name_location_list = [] +# Loop through all instances +for inst in insts: + # Get all pins of this cell + inst_ITerms = inst.getITerms() + # Loop through all pins + for ITerm in inst_ITerms: + # Get the pin's name defines in the lef file through MTerm + MTerm_name = inst_ITerm.getMTerm().getName() + # Get the name of the cell this pin belongs to. + inst_name = inst_ITerm.getInst().getName() + # Concat the two strings + pin_name = ""{}/{}"".format(inst_name, MTerm_name) + # Get the location of the pin in the layout + pin_loc = ITerm.getAvgXY() + if pin_loc[0]: + pin_name_location_list.append([pin_name, pin_loc[0], pin_loc[1]]) + else: + pin_name_location_list.append([pin_name, -1, -1]) +return pin_name_location_list",Get the location of all pins +"# Get the DB +db = ord.get_db() +# Get all libraries read into the DB +libs = db.getLibs() +# Create a list to store every library cell's name +libcell_name_list = [] +# Loop through all libraries +for lib in libs: + # Get all library cells in this library + lib_masters = lib.getMasters() + # Loop through all library cells + for master in lib_masters: + # Get the name and append it to the list + libcell_name = master.getName() + libcell_name_list.append(libcell_name) +return libcell_name_list",Get the name of every liberty cell diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/DB/query.xlsx b/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/DB/query.xlsx new file mode 100644 index 0000000..d14799c Binary files /dev/null and b/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/DB/query.xlsx differ diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/Flow/flow.csv b/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/Flow/flow.csv new file mode 100644 index 0000000..9b4e64a --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/Flow/flow.csv @@ -0,0 +1,95221 @@ +code,prompt +"# Get the defined top layer of the IO pin placer + +# Get the IO Placer object of the design +iop = design.getIOPlacer() + +# Return the top layer +return iop.getTopLayer()",Get the defined top layer of the IO pin placer +"# Get the corner avoidance, number of slots and HPWL report of the IO pin placer + +# Get the IO Placer object of the design +iop = design.getIOPlacer() + +# Get the parameters of the IO Placer +parameters = iop.getParameters() + +# Construct the output string with corner avoidance, HPWL report, and number of slots +output_string = ""Corner Avoidance: {}\nHPWL Report: {}\nNumber of slots: {}"".format( + parameters.getCornerAvoidance(), + parameters.getReportHPWL(), + parameters.getNumSlots() +) + +# Return the output string +return output_string","Get the corner avoidance, number of slots and HPWL report of the IO pin placer" +"# Get the vertical and horizontal length of the setting of the IO pin placer + +# Get the IO Placer object of the design +iop = design.getIOPlacer() + +# Get the parameters of the IO Placer +parameters = iop.getParameters() + +# Return the vertical and horizontal length +return (parameters.getVerticalLength(), parameters.getHorizontalLength())",Get the vertical and horizontal length of the setting of the IO pin placer +"# Get the minimum distance setting of the IO pin placer and set it to 100 if it is 0 + +# Get the IO Placer object of the design +iop = design.getIOPlacer() + +# Get the parameters of the IO Placer +parameters = iop.getParameters() + +# Set the minimum distance to 100 if it's 0 +min_dist = parameters.getMinDistance() +if min_dist == 0: + parameters.setMinDistance(100) + +# Set min distance in tracks +parameters.setMinDistanceInTracks(True) + +# Return the minimum distance +return min_dist",Get the minimum distance setting of the IO pin placer and set it to 100 if it is 0 +"# Change the setting of horizontal and vertical length of thr IO pin placer to 100 + +# Get the IO Placer object of the design +iop = design.getIOPlacer() + +# Get the parameters of the IO Placer +parameters = iop.getParameters() + +# Set vertical and horizontal length to 100 +parameters.setVerticalLength(100) +parameters.setHorizontalLength(100)",Change the setting of horizontal and vertical length of thr IO pin placer to 100 +"# Adjust the setting of vertical length of the IO pin placer to 100 + +# Get the IO Placer object of the design +iop = design.getIOPlacer() + +# Get the parameters of the IO Placer +parameters = iop.getParameters() + +# Set vertical length to 100 +parameters.setVerticalLength(100)",Adjust the setting of vertical length of the IO pin placer to 100 +"# Check if the annealing debug mode is on for the IO pin placer and print the configs of the IO pin placer + +# Get the IO Placer object of the design +io_placer = design.getIOPlacer() + +# Print the configurations of the IO placer +io_placer.printConfig() + +# Return whether the annealing debug is on +return io_placer.isAnnealingDebugOn()",Check if the annealing debug mode is on for the IO pin placer and print the configs of the IO pin placer +"# Get the number of DRVs, cloud size and set the could size to 500 from the detailed router + +# Get the Triton Route object of the design +triton_route = design.getTritonRoute() + +# Get the number of DRVs +num_drvs = triton_route.getNumDRVs() + +# Set the cloud size to 500 +cloud_size = triton_route.setCloudSize(500) + +# Return the number of DRVs and cloud size +return (num_drvs, cloud_size)","Get the number of DRVs, cloud size and set the could size to 500 from the detailed router" +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 um,15 um, and the top-right corner as 55 um,35 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the standard cells and the macros. Place each macro at least 5 um away from each other, and set a halo region around each macro as 5 um. Set the number of iteration of the global router as 30. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. During detailed placement, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the standard cells and the macros. Place each macro at least 5 um away from each other, and set a halo region around each macro as 5 um. Set the number of iteration of the global router as 30. During detailed placement, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 30 um,15 um, and the top-right corner as 55 um,35 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 um,15 um, and the top-right corner as 55 um,35 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the standard cells and the macros. Place each macro at least 5 um away from each other, and set a halo region around each macro as 5 um. Set the number of iteration of the global router as 10. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the standard cells and the macros. Place each macro at least 5 um away from each other, and set a halo region around each macro as 5 um. Set the number of iteration of the global router as 10. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 30 um,15 um, and the top-right corner as 55 um,35 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 30 um,15 um, and the top-right corner as 55 um,35 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 um,15 um, and the top-right corner as 55 um,35 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the standard cells and the macros. Place each macro at least 5 um away from each other, and set a halo region around each macro as 5 um. Set the number of iteration of the global router as 20. During detailed placement, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +libFiles = libDir.glob(""*.lib"") +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +design = Design(tech)",How can I read .lib files into OpenROAD? +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Set file path +lefDir = Path(""lef_path"") +lefFiles = lefDir.glob('*.lef') +# Modify the technology file postfix for other naming convention +techLefFiles = lefDir.glob(""*.tech.lef"") +# Read library files +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech)",How can I read .lef files into OpenROAD? +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have .lef files read into OpenROAD DB +design = Design(tech) + +designDir = Path(""design_path"") +design_file_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" +verilogFile = designDir/str(design_file_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name)",Show me the way to read the Verilog file into OpenROAD +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have .lef files read into OpenROAD DB +design = Design(tech) + +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"")","If the clock prot is called clk_i, how can I set the design clock period to 50 nanoseconds?" +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 10 um +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks()","Show me the piece of code to perform floorplanning using a utilization rate of 50% and an aspect ratio of 0.66, and set the spacing between the core and the die to 10 microns" +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(118) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M6 and M7 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M6"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode)",How can I place I/O pins of the design block on M6 and M7 layers? +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset()",How can I perform global placement? +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Global Placement +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement +# In OpenROAD, global placement should be performed before macro placement +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl()",Place the macros onto the design block +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False)",Perform detailed placement in OpenROAD +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Clock Tree Synthesis +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False)",Show me how I can perform CTS in OpenROAD +"from openroad import Tech, Design +from pathlib import Path +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Add Filler Cells +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix)",Add filler cells on the design block +"from openroad import Tech, Design +from pathlib import Path +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power distribution network + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes()",Show me how I can construct power distribution network in OpenROAD +"from openroad import Tech, Design +from pathlib import Path +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes()",Show me how I can build power distribution network if my design has macros +"from openroad import Tech, Design +from pathlib import Path +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1""))",How can I perform IR drop analysis on the M1 layer where the pins are located? +"from openroad import Tech, Design +from pathlib import Path +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +design.evalTclString(""report_power"")","Report the switching power, internal power and leakage power of the design" +"from openroad import Tech, Design +from pathlib import Path +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Global Routing +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True)",Perform global routing in OpenROAD +"from openroad import Tech, Design +from pathlib import Path +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Detailed Routing +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main()",Perform detailed routing in OpenROAD +"from openroad import Design, Tech +import openroad as ord + +tech = Tech() +# Read the files into Openroad +design = Design(tech) + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +db = ord.get_db() +libs = db.getLibs() +site_name = """" +for lib in libs: + sites = lib.getSites() + if len(sites) == 0: + continue + else: + site_name = sites[0].getName() + break +site = floorplan.findSite(site_name) +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks()",How can I automatically search for the name of the site and use that for floorplanning? +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Clock Tree Synthesis +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False)",Show me how I can perform clock tree synthesis in OpenROAD +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal2 grid, the metal4 grid, and the metal8 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal2 grid, metal4 grid, and metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal8, set the width and spacing to 5 and 5 microns, and for the power rings on metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After placement, do CTS and use bufferx1 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After PDN construction, get the IR drop analysis result on Metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 microns,15 microns, and the top-right corner as 55 microns,35 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 microns,15 microns, and the top-right corner as 55 microns,35 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on Metal5 and Metal6. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. During detailed placement, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.45, and set the spacing between die and core as 10 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal4 grid, and the Metal7 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal4 grid, and Metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal7 and Metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.45, and set the spacing between die and core as 12 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.50, and set the spacing between die and core as 14 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.45, and set the spacing between die and core as 14 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.50, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. During detailed placement, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.40, and set the spacing between die and core as 12 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.50, and set the spacing between die and core as 10 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal4 grid, and the Metal7 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal4 grid, and Metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal7, set the width and spacing to 5 and 5 microns, and for the power rings on Metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 10 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7, set the width and spacing to 4 and 4 microns, and for the power rings on Metal8, also set the width and spacing to 4 and 4 microns. If there are macros, build power grids for macros on Metal5 and Metal6 and set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 10 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal4 grid, and the Metal7 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal4 grid, and Metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal7, set the width and spacing to 5 and 5 microns, and for the power rings on Metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.45, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 2 and 2 microns, and for the power rings on metal8, set the width and spacing to 2 and 2 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.45, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7, set the width and spacing to 5 and 5 microns, and for the power rings on metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.50, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. During detailed placement, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7, set the width and spacing to 5 and 5 microns, and for the power rings on metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 12 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 20. During detailed placement, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8 and Metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on Metal5 and Metal6. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on Metal5 and Metal6. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on Metal5 and Metal6. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 20. During detailed placement, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.40, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7 and metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7 and metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.50, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.45, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7 and metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.50, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 10. During detailed placement, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.40, and set the spacing between die and core as 12 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.60, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 2 and 2 microns, and for the power rings on metal8, set the width and spacing to 2 and 2 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.45, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 4 and 4 microns, and for the power rings on metal8, also set the width and spacing to 4 and 4 microns. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.50, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 4 and 4 microns, and for the power rings on metal8, set the width and spacing to 4 and 4 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.40, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 4 and 4 microns, and for the power rings on metal8, set the width and spacing to 4 and 4 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.45, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 2 and 2 microns, and for the power rings on metal8, set the width and spacing to 2 and 2 micronsas well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.40, and set the spacing between die and core as 12 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 20. During detailed placement, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 4 and 4 microns, and for the power rings on metal8, set the width and spacing to 4 and 4 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal2 grid, the metal4 grid, and the metal8 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal2 grid, metal4 grid, and metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal8, set the width and spacing to 5 and 5 microns, and for the power rings on metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal2 grid, the metal4 grid, and the metal8 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal2 grid, metal4 grid, and metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal8, set the width and spacing to 5 and 5 microns, and for the power rings on metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. During detailed placement, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal2 grid, the metal4 grid, and the metal8 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal2 grid, metal4 grid, and metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal8 and metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on Metal5 and Metal6. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After placement, do CTS and use bufferx1 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on Metal5 and Metal6. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After PDN construction, get the IR drop analysis result on Metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,40. And set the bottom-left corner of the core as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 microns,15 microns, and the top-right corner as 55 microns,35 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 70,70. And set the bottom-left corner of the core as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After placement, do CTS and use bufferx1 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After PDN construction, get the IR drop analysis result on Metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7, set the width and spacing to 5 and 5 microns, and for the power rings on metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7, set the width and spacing to 2 and 2 microns, and for the power rings on Metal8, also set the width and spacing to 2 and 2 microns. If there are macros, build power grids for macros on Metal5 and Metal6 and set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 4 and 4 microns, and for the power rings on metal8, set the width and spacing to 4 and 4 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 4 and 4 microns, and for the power rings on metal8, set the width and spacing to 4 and 4 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7, set the width and spacing to 4 and 4 microns, and for the power rings on Metal8, set the width and spacing to 4 and 4 micronsas well. If there are macros, build power grids for macros on Metal5 and Metal6 and set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 70,70. And set the bottom-left corner of the core as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. During detailed placement, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 2 and 2 microns, and for the power rings on metal8, set the width and spacing to 2 and 2 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,40. And set the bottom-left corner of the core as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 microns,15 microns, and the top-right corner as 55 microns,35 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal2 grid, the metal4 grid, and the metal8 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal2 grid, metal4 grid, and metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal8, set the width and spacing to 5 and 5 microns, and for the power rings on metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 20. During detailed placement, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on Metal5 and Metal6. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on Metal5 and Metal6. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8 and Metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 10. During detailed placement, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,40. And set the bottom-left corner of the core as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7 and metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,40. And set the bottom-left corner of the core as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 30. During detailed placement, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7 and metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,40. And set the bottom-left corner of the core as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 2 and 2 microns, and for the power rings on metal8, set the width and spacing to 2 and 2 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 70,70. And set the bottom-left corner of the core as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 4 and 4 microns, and for the power rings on metal8, also set the width and spacing to 4 and 4 microns. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 4 and 4 microns, and for the power rings on metal8, set the width and spacing to 4 and 4 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7, set the width and spacing to 5 and 5 microns, and for the power rings on metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal4 grid, and the Metal7 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal4 grid, and Metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal7, set the width and spacing to 5 and 5 microns, and for the power rings on Metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 30. During detailed placement, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7, set the width and spacing to 5 and 5 microns, and for the power rings on metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 30 microns,15 microns, and the top-right corner as 55 microns,35 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. During detailed placement, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal2 grid, the metal4 grid, and the metal8 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal2 grid, metal4 grid, and metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal8 and metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8 and Metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8 and Metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8 and Metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. During detailed placement, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.45, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.40, and set the spacing between die and core as 10 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.50, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7 and metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.50, and set the spacing between die and core as 10 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.50, and set the spacing between die and core as 12 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. During detailed placement, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 12 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.40, and set the spacing between die and core as 14 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7, set the width and spacing to 4 and 4 microns, and for the power rings on Metal8, set the width and spacing to 4 and 4 microns as well. If there are macros, build power grids for macros on Metal5 and Metal6 and set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.45, and set the spacing between die and core as 14 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7, set the width and spacing to 4 and 4 microns, and for the power rings on Metal8, also set the width and spacing to 4 and 4 microns. If there are macros, build power grids for macros on Metal5 and Metal6 and set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.40, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 2 and 2 microns, and for the power rings on metal8, set the width and spacing to 2 and 2 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.60, and set the spacing between die and core as 12 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 microns,15 microns, and the top-right corner as 55 microns,35 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7, set the width and spacing to 5 and 5 microns, and for the power rings on metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.40, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 2 and 2 microns, and for the power rings on metal8, set the width and spacing to 2 and 2 micronsas well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.45, and set the spacing between die and core as 10 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After placement, do CTS and use bufferx1 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7, set the width and spacing to 4 and 4 microns, and for the power rings on Metal8, set the width and spacing to 4 and 4 microns as well. If there are macros, build power grids for macros on Metal5 and Metal6 and set the pitch of the via between two grids to 2 microns. After PDN construction, get the IR drop analysis result on Metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.40, and set the spacing between die and core as 14 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 10. During detailed placement, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8 and Metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on Metal5 and Metal6. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 14 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8 and Metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 12 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal2 grid, the metal4 grid, and the metal8 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal2 grid, metal4 grid, and metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal8 and metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 5 microns. After that, place the pins on metal8 and metal9. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 20. During detailed placement, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(13) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 10 microns. After that, place the pins on Metal8 and Metal9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.40, and set the spacing between die and core as 14 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal4 grid, and the Metal7 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal4 grid, and Metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal7 and Metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 12 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.60, and set the spacing between die and core as 14 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.60, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7 and metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.50, and set the spacing between die and core as 14 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.50, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 30. During detailed placement, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7 and metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 10 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 12 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 4 and 4 microns, and for the power rings on metal8, set the width and spacing to 4 and 4 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.60, and set the spacing between die and core as 12 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 2 and 2 microns, and for the power rings on metal8, also set the width and spacing to 2 and 2 microns. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.60, and set the spacing between die and core as 14 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal4 grid, and the Metal7 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal4 grid, and Metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal7, set the width and spacing to 5 and 5 microns, and for the power rings on Metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.35, and set the spacing between die and core as 14 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7, set the width and spacing to 2 and 2 microns, and for the power rings on Metal8, set the width and spacing to 2 and 2 microns as well. If there are macros, build power grids for macros on Metal5 and Metal6 and set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.60, and set the spacing between die and core as 5 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7, set the width and spacing to 5 and 5 microns, and for the power rings on metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.60, and set the spacing between die and core as 12 microns. After that, place the IO pins on metal7 and metal8. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 20. During detailed placement, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 4 and 4 microns, and for the power rings on metal8, set the width and spacing to 4 and 4 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplanning and set the floorplan utilization as 0.45, and set the spacing between die and core as 10 microns. After that, place the IO pins on Metal7 and Metal8. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After placement, do CTS and use bufferx1 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8, set the width and spacing to 5 and 5 microns, and for the power rings on Metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After PDN construction, get the IR drop analysis result on Metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 microns,15 microns, and the top-right corner as 55 microns,35 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal2 grid, the metal4 grid, and the metal8 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal2 grid, metal4 grid, and metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal8 and metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal2 grid, the metal4 grid, and the metal8 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal2 grid, metal4 grid, and metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal8 and metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 30 microns,15 microns, and the top-right corner as 55 microns,35 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After placement, do CTS and use bufferx1 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal2 grid, the Metal4 grid, and the Metal8 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal2 grid, Metal4 grid, and Metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal8 and Metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After PDN construction, get the IR drop analysis result on Metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,40. And set the bottom-left corner of the core as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 microns,15 microns, and the top-right corner as 55 microns,35 microns. Meanwhile ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,40. And set the bottom-left corner of the core as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 microns,15 microns, and the top-right corner as 55 microns,35 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7 and metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After placement, do CTS and use bufferx1 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After PDN construction, get the IR drop analysis result on Metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal4 grid, and the Metal7 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal4 grid, and Metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal7, set the width and spacing to 5 and 5 microns, and for the power rings on Metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 microns,12 microns, and the top-right corner as 43 microns,42 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal4 grid, and the Metal7 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal4 grid, and Metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal7, set the width and spacing to 5 and 5 microns, and for the power rings on Metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 2 and 2 microns, and for the power rings on metal8, set the width and spacing to 2 and 2 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,40. And set the bottom-left corner of the core as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 microns,15 microns, and the top-right corner as 55 microns,35 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7, set the width and spacing to 5 and 5 microns, and for the power rings on metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 microns,5 microns, and the top-right corner as 20 microns,25 microns. Meanwhile make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7, set the width and spacing to 5 and 5 microns, and for the power rings on metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 70,70. And set the bottom-left corner of the core as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 microns,32 microns, and the top-right corner as 55 microns,60 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After placement, do CTS and use bufferx1 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7, set the width and spacing to 2 and 2 microns, and for the power rings on Metal8, set the width and spacing to 2 and 2 microns as well. If there are macros, build power grids for macros on Metal5 and Metal6 and set the pitch of the via between two grids to 2 microns. After PDN construction, get the IR drop analysis result on Metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# nMacro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 microns,10 microns, and the top-right corner as 30 microns,40 microns. And place each macro at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal2 grid, the metal4 grid, and the metal8 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal2 grid, metal4 grid, and metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal8, set the width and spacing to 5 and 5 microns, and for the power rings on metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 30. During detailed placement, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal2 grid, the metal4 grid, and the metal8 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal2 grid, metal4 grid, and metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal8, set the width and spacing to 5 and 5 microns, and for the power rings on metal9, set the width and spacing to 5 and 5 microns as well. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 2 and set the spacing to 2 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal2 grid, the metal4 grid, and the metal8 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal2 grid, metal4 grid, and metal8 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal8 and metal9, set the width to 5 and set the spacing to 5 microns. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times thethe pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""Metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""Metal9"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform CTS with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal8 and Metal9, and have power grids on Metal1 , Metal2, and Metal4 for standard cells and macros. For the power rings on Metal8 and Metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on Metal5 and Metal6. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal8 and metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m2 = design.getTech().getDB().getTech().findLayer(""metal2"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +m9 = design.getTech().getDB().getTech().findLayer(""metal9"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m8, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m9, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m2, width = m2.getMinWidth(), + spacing = m2.getSpacing(), pitch = m2.getPitch(), offset = m2.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m8, width = m8.getMinWidth(), + spacing = m8.getSpacing(), pitch = m8.getPitch(), offset = m8.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m2, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m2, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m8, layer1 = m9, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 20. During detailed placement, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal8 and metal9, and have power grids on metal1 , metal2, and metal4 for standard cells and macros. For the power rings on metal8 and metal9, set the width to 4 and set the spacing to 4 microns. If there are macros, build power grids for macros on metal5 and metal6. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal8 and Metal9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,40. And set the bottom-left corner of the core as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal4 grid, and the Metal7 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal4 grid, and Metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal7 and Metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. Set the width of the Metal1 grid, the Metal4 grid, and the Metal7 grid using the minimum value from the technology file. Then set the spacing of the Metal1 grid, Metal4 grid, and Metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on Metal7 and Metal8, set the width to 5 and set the spacing to 5. If there are macros, build power rings and grids for macros on Metal5 and Metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on Metal5 and Metal6, set the width to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7 and Metal8, set the width to 4 and set the spacing to 4 microns. If there are macros, build power rings and grids for macros on Metal5 and Metal6 and set the width for the power ring on Metal5 and Metal6 to 2 microns and set the spacing to 2 microns. And if there are parallel grids, set the pitch of the via between two grids to 2 microns. In the routing stage, route the design from Metal1 to Metal6. In the end, perform IR drop analysis on Metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7 and metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7 and metal8, set the width to 2 and set the spacing to 2 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 and set the width for the power ring on metal5 and metal6 to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the standard cells and the macros. Place each macro at least 5 microns away from each other, and set a halo region around each macro as 5 microns. Set the number of iteration of the global router as 30. During detailed placement, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7 and metal8, set the width to 5 and set the spacing to 5 microns. If there are macros, build power rings and grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. However, for the power ring on metal5 and metal6, set the width to 1.5 microns and set the spacing to 1.5 microns. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. After PDN construction, get the IR drop analysis result on metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,40. And set the bottom-left corner of the core as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Macro_core_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Macro_core_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""Metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""Metal6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""Metal1"" +params.topRoutingLayer = ""Metal6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 70,70. And set the bottom-left corner of the core as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 microns, and the y-axis as0. After the placement stage, perform clock tree synthesis with using bufferx1 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7, set the width and spacing to 4 and 4 microns, and for the power rings on Metal8, set the width and spacing to 4 and 4 microns as well. If there are macros, build power grids for macros on Metal5 and Metal6 and set the pitch of the via between two grids to 2 microns. After constructing power grids, perform IR drop analysis on Metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from Metal1 to Metal6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +# Report Power +ndesign.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 2 and 2 microns, and for the power rings on metal8, also set the width and spacing to 2 and 2 microns. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. After constructing power grids, perform IR drop analysis on metal1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from metal1 to metal7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""metal1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 microns, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 2 and 2 microns, and for the power rings on metal8, set the width and spacing to 2 and 2 microns as well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. In the end, perform IR drop analysis on metal1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Instance_pdn_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Instance_pdn_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 60,50. And set the bottom-left corner of the core as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. Set the width of the metal1 grid, the metal4 grid, and the metal7 grid using the minimum value from the technology file. Then set the spacing of the metal1 grid, metal4 grid, and metal7 grid using the minimum value from the technology file as well, but set the pitch of those grids using two times the minimum value from the technology file. Set the offset using the default value. For the power rings on metal7, set the width and spacing to 5 and 5 microns, and for the power rings on metal8, set the width and spacing to 5 and 5 microns as well. If there are macros, build power grids for macros on metal5 and metal6 with using minimum values for width and spacing from the technology file for power grids, and use two times the pitch value from the technology file for macro's power grids. And if there are parallel grids, set the pitch of the via between two grids to 0 microns. In the routing stage, route the design from metal1 to metal7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLCELL_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""Core_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") +grid = pdngen.findGrid(""Core_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 45,45. And set the bottom-left corner of the core as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on metal7 and metal8, and have power grids on metal1 and metal4 for standard cells and macros. For the power rings on metal7, set the width and spacing to 2 and 2 microns, and for the power rings on metal8, set the width and spacing to 2 and 2 micronsas well. If there are macros, build power grids for macros on metal5 and metal6 and set the pitch of the via between two grids to 0 microns. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on Metal7 and Metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""Metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""Metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer Metal4 (usually Metal4) + layer = design.getTech().getDB().getTech().findLayer(""Metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""bufferx1"") +cts.setRootBuffer(""bufferx1"") +cts.setSinkBuffer(""bufferx1"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""FILLER_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +halo = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""_core_"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""Metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""Metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""Metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""Metal8"") +grid = pdngen.findGrid(""_core_"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on Metal1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = m1.getMinWidth(), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = m4.getMinWidth(), + spacing = m4.getSpacing(), pitch = m4.getPitch(), offset = m4.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = m7.getMinWidth(), + spacing = m7.getSpacing(), pitch = m7.getPitch(), offset = m7.getOffset(), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""Metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""Metal6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = f""Core_macro_grid_{i}"", + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(f""Core_macro_grid_{i}"") + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = m5.getMinWidth(), + spacing = m5.getSpacing(), pitch = m5.getPitch(), offset = m5.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = m6.getMinWidth(), + spacing = m6.getSpacing(), pitch = m6.getPitch(), offset = m6.getOffset(), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""Metal2"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as1. After placement, do CTS and use bufferx1 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on Metal7 and Metal8, and have power grids on Metal1 and Metal4 for standard cells and macros. For the power rings on Metal7, set the width and spacing to 2 and 2 microns, and for the power rings on Metal8, set the width and spacing to 2 and 2 microns as well. If there are macros, build power grids for macros on Metal5 and Metal6 and set the pitch of the via between two grids to 2 microns. After PDN construction, get the IR drop analysis result on Metal1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on metal7 and metal8 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer metal4 (usually metal4) + layer = design.getTech().getDB().getTech().findLayer(""metal4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 nanoseconds. Then perform floorplan and set the bottom-left corner of the die as 0,0 and the top-right corner as 40,60. And set the bottom-left corner of the core as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 microns to each other, and set a halo region around each macro as 5 microns. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 microns, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +libFiles = libDir.glob(""*.lib"") +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +design = Design(tech)",Show me how I can read .lib files into OpenROAD +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +libFiles = libDir.glob(""*.lib"") +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +design = Design(tech)",Write a piece of code to read .lib files into OpenROAD +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Set file path +lefDir = Path(""lef_path"") +lefFiles = lefDir.glob('*.lef') +# Modify the technology file postfix for other naming convention +techLefFiles = lefDir.glob(""*.tech.lef"") +# Read library files +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech)",Show me how I can read .lef files into OpenROAD +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Set file path +lefDir = Path(""lef_path"") +lefFiles = lefDir.glob('*.lef') +# Modify the technology file postfix for other naming convention +techLefFiles = lefDir.glob(""*.tech.lef"") +# Read library files +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech)",Write a piece of code to read .lef files into OpenROAD +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have .lef files read into OpenROAD DB +design = Design(tech) + +designDir = Path(""design_path"") +design_file_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" +verilogFile = designDir/str(design_file_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name)",Show me how I can read the Verilog file into OpenROAD +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have .lef files read into OpenROAD DB +design = Design(tech) + +designDir = Path(""design_path"") +design_file_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" +verilogFile = designDir/str(design_file_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name)",How can I read the Verilog file into OpenROAD? +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have .lef files read into OpenROAD DB +design = Design(tech) + +designDir = Path(""design_path"") +design_file_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" +verilogFile = designDir/str(design_file_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name)",Write a piece of code to read the Verilog file into OpenROAD? +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have .lef files read into OpenROAD DB +design = Design(tech) + +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"")","If the clock prot is called clk_i, how can I set the design clock period to 50 nanoseconds?" +"from openroad import Design, Tech +import openroad as ord + +tech = Tech() +# Read the files into Openroad +design = Design(tech) + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +db = ord.get_db() +libs = db.getLibs() +site_name = """" +for lib in libs: + sites = lib.getSites() + if len(sites) == 0: + continue + else: + site_name = sites[0].getName() + break +site = floorplan.findSite(site_name) +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks()",Show me the code that automatically searches for the name of the site and uses that for floorplanning. +"from openroad import Design, Tech +import openroad as ord + +tech = Tech() +# Read the files into Openroad +design = Design(tech) + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +db = ord.get_db() +libs = db.getLibs() +site_name = """" +for lib in libs: + sites = lib.getSites() + if len(sites) == 0: + continue + else: + site_name = sites[0].getName() + break +site = floorplan.findSite(site_name) +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks()","If I don't know the name of the site defined in the library, how can I perform floorplanning then?" +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, \ No newline at end of file diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/Flow/flow.xlsx b/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/Flow/flow.xlsx new file mode 100644 index 0000000..4549a5d Binary files /dev/null and b/flow-Agent/EDA-Corpus-main/Augmented_Data/Prompt-Script/Flow/flow.xlsx differ diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/Flow/Flow.csv b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/Flow/Flow.csv new file mode 100644 index 0000000..77871e3 --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/Flow/Flow.csv @@ -0,0 +1,224 @@ +Prompts,Answers +Brief me on OpenROAD Flow?,"OpenROAD-flow-scripts (ORFS) is a fully autonomous, RTL-GDSII flow for rapid architecture and design space exploration, early prediction of QoR, and detailed physical design implementation. However, ORFS also enables manual intervention for finer user control of individual flow stages through Tcl commands and Python APIs." +What is OpenROAD Flow and its benefits?,"OpenROAD-flow-scripts (ORFS) is a fully autonomous, RTL-GDSII flow for rapid architecture and design space exploration, early prediction of QoR, and detailed physical design implementation. However, ORFS also enables manual intervention for finer user control of individual flow stages through Tcl commands and Python APIs." +Brief me on OpenROAD Flow?,"OpenROAD-flow-scripts offer a comprehensive, autonomous RTL-GDSII flow for rapid design exploration and physical design, allowing for manual intervention at stages through Tcl commands and Python APIs for greater control." +"I'm trying to port ORFS to a TSMC process. During the detailed route step, I get a lot of DRT-0073 errors. Utilization is set to 20% at the beginning of the P&R flow and it is a pretty simple design. Give me some tips about what to look into? +I have tried to run the pin_access command directly but the -verbose parameter does not seem to work as I don't get any more information","You can try the developer debugs to get a sense of what is going on. Put detailed_route_debug -pa -pa_markers -pin _3504_:A1 before you call detailed_route and run it in the GUI. It will stop at the pin and show you how it is trying to access it and any associated drc markers. You click the continue button to see the various steps. Hopefully, that gives you an idea as to what is going on. The other option is a support contract with precisioninno.com where we can help under NDA. +" +I'm encountering DRT-0073 errors during detailed routing in ORFS; any advice?,"You can try the developer debugs to get a sense of what is going on. Put detailed_route_debug -pa -pa_markers -pin _3504_:A1 before you call detailed_route and run it in the GUI. It will stop at the pin and show you how it is trying to access it and any associated drc markers. You click the continue button to see the various steps. Hopefully, that gives you an idea as to what is going on. The other option is a support contract with precisioninno.com where we can help under NDA. +" +"I'm trying to port ORFS to a TSMC process. During the detailed route step, I get a lot of DRT-0073 errors. Utilization is set to 20% at the beginning of the P&R flow and it is a pretty simple design. Give me some tips about what to look into? +I have tried to run the pin_access command directly but the -verbose parameter does not seem to work as I don't get any more information","Developer debug options in OpenROAD can give insights into detailed routing processes, offering visual debug aids in the GUI and the option for NDA-supported assistance from precisioninno.com." +What does the following argument do in the build command of ORFS: -o or —local?,"The argument, o or —local, builds locally instead of building a Docker image." +How does the -o or —local argument function in the build command of ORFS?,"The argument, o or —local, builds locally instead of building a Docker image." +What does the following argument do in the build command of ORFS: -o or —local?,The -o or --local argument opts for a local build over Docker. +What operation does the -l or --latest argument perform in the build command of ORFS?,The -l or --latest argument specifies to use of the head of branch –or_branch or ‘master’ by default for tools/OpenROAD. +What is accomplished by the -l or --latest argument in the build command of ORFS?,The -l or --latest argument specifies to use of the head of branch –or_branch or ‘master’ by default for tools/OpenROAD. +What operation does the -l or --latest argument perform in the build command of ORFS?,"The -l or --latest argument chooses the latest branch head for tools/OpenROAD, defaulting to master." +How is this argument utilized in the build command of ORFS: --or_branch BRANCH_NAME?,The -or_branch BRANCH_NAME argument stipulates the use of the head of branch BRANCH for tools/OpenROAD. +How is the --or_branch BRANCH_NAME argument used in the build command of ORFS?,The -or_branch BRANCH_NAME argument stipulates the use of the head of branch BRANCH for tools/OpenROAD. +How is this argument utilized in the build command of ORFS: --or_branch BRANCH_NAME?,The -or_branch BRANCH_NAME argument selects the branch head of BRANCH for tools/OpenROAD. +What role does this argument play in the build command of ORFS: --or_repo REPO_URL?, This argument enumerates to use of a fork at REPO-URL (https/ssh) for tools/OpenROAD. +What does the --or_repo REPO_URL argument specify in the build command of ORFS?, This argument enumerates to use of a fork at REPO-URL (https/ssh) for tools/OpenROAD. +What role does this argument play in the build command of ORFS: --or_repo REPO_URL?,Specifies using a tools/OpenROAD fork at a given REPO-URL. +What does the following argument do in the build command of ORFS: --no_init?,The --no_init argument prescribes skipping initializing submodules. +What does the --no_init argument accomplish in the build command of ORFS?,The --no_init argument prescribes skipping initializing submodules. +What does the following argument do in the build command of ORFS: --no_init?,The --no_init option omits submodule initialization. +How does the following argument function in the build command of ORFS: -t N or --threads N?,The -t N or --threads N argument stipulates the use of N cpus when compiling software. +What does the -t N or --threads N argument control in the build command of ORFS?,The -t N or --threads N argument stipulates the use of N cpus when compiling software. +How does the following argument function in the build command of ORFS: -t N or --threads N?,The -t N or --threads N argument utilizes N CPUs for software compilation. +What is the purpose of the following argument in the build command of ORFS: -n or --nice?,"The -n or --nice flag in the build script instructs the build script to set all jobs to the maximim Unix ""niceness"". Niceness determines how much the operating system prefers to schedule process. The purpose of setting this flag is to ensure that a system is not overwhelmed by using all available processing primarily of the build jobs. The build will use all CPUs by default unless --threads is also given, then N threads are used instead." +What is the purpose of the -n or --nice argument in the build command of ORFS?,"The -n or --nice flag in the build script instructs the build script to set all jobs to the maximim Unix ""niceness"". Niceness determines how much the operating system prefers to schedule process. The purpose of setting this flag is to ensure that a system is not overwhelmed by using all available processing primarily of the build jobs. The build will use all CPUs by default unless --threads is also given, then N threads are used instead." +What is the purpose of the following argument in the build command of ORFS: -n or --nice?,"The build script's -n or --nice flag sets all jobs to the maximum Unix ""niceness"" level. This determines the priority with which the operating system schedules processes. The aim is to prevent system overload by allocating all processing power primarily to the build jobs. Without specifying otherwise, the build utilizes all CPUs, but specifying --threads allows for the use of a fixed number of threads." +What does the following argument do in the build command of ORFS: —yosys-args-overwrite?,This argument states to not use default flags set by this scrip during Yosys compilation. +What does the --yosys-args-overwrite argument modify in the build command of ORFS?,This argument states to not use default flags set by this scrip during Yosys compilation. +What does the following argument do in the build command of ORFS: —yosys-args-overwrite?,This parameter instructs the script to ignore the default flags during Yosys compilation. +What is the purpose of the following argument in the build command of ORFS: —yosys-args STRING?,The '—yosys-args STRING' argument adds additional compilation flags for Yosys compilation. +How does the --yosys-args STRING argument customize the build process in ORFS?,The '—yosys-args STRING' argument adds additional compilation flags for Yosys compilation. +What is the purpose of the following argument in the build command of ORFS: —yosys-args STRING?,The '--yosys-args STRING' option allows for the inclusion of extra flags in Yosys compilations. +What function does the following argument serve in the build command of ORFS: —openroad-args-overwrite?,The '—openroad-args-overwrite' argument specifies to not use default flags set by this script during OpenROAD app compilation. +What modification does the --openroad-args-overwrite argument make in the build command of ORFS?,The '—openroad-args-overwrite' argument specifies to not use default flags set by this script during OpenROAD app compilation. +What function does the following argument serve in the build command of ORFS: —openroad-args-overwrite?,The '--openroad-args-overwrite' option commands the script not to apply its default flags during OpenROAD app compilations. +What does the following argument do in the build command of ORFS: —openroad-args STRING?,The '—openroad-args STRING' argument adds aditional compilation flags for OpenROAD app compilation. +How does the --openroad-args STRING argument alter the build process in ORFS?,The '—openroad-args STRING' argument adds aditional compilation flags for OpenROAD app compilation. +What does the following argument do in the build command of ORFS: —openroad-args STRING?,The '--openroad-args STRING' option introduces additional flags for compiling the OpenROAD app. +What is the purpose of the following argument in the build command of ORFS: —lsoracle-enable?,This argument initiates compiling LSOracle since it is disabled by default as it is not currently used on the flow. +What is the function of the --lsoracle-enable argument in the build command of ORFS?,This argument initiates compiling LSOracle since it is disabled by default as it is not currently used on the flow. +What is the purpose of the following argument in the build command of ORFS: —lsoracle-enable?,"Activates the compilation of LSOracle, which is off by default as it's not part of the current workflow." +What does the following argument do in the build command of ORFS: —lsoracle-args-overwrite?,The '—lsoracle-args-overwrite' argument stipulates not to use default flags set by this script during LSOracle compilation. +What does the --lsoracle-args-overwrite argument change in the build command of ORFS?,The '—lsoracle-args-overwrite' argument stipulates not to use default flags set by this script during LSOracle compilation. +What does the following argument do in the build command of ORFS: —lsoracle-args-overwrite?,The '--lsoracle-args-overwrite' command directs the script to bypass default flags for LSOracle compilations. +What does the following argument achieve in the build command of ORFS: —lsoracle-args STRING?,This argument adds aditional compilation flags for LSOracle compilation. +How does the --lsoracle-args STRING argument customize the ORFS build process?,This argument adds aditional compilation flags for LSOracle compilation. +What does the following argument achieve in the build command of ORFS: —lsoracle-args STRING?,This command introduces extra compilation flags for LSOracle. +What function does the following argument serve in the build command of ORFS: —install-path PATH?,The '—install-path PATH' delineates the path to install tools. Default is ${INSTALL_PATH}. +What does the --install-path PATH argument specify in the build command of ORFS?,The '—install-path PATH' delineates the path to install tools. Default is ${INSTALL_PATH}. +What function does the following argument serve in the build command of ORFS: —install-path PATH?,"The '--install-path PATH' option specifies the installation directory for tools, with ${INSTALL_PATH} as the default." +What does the following argument do in the build command of ORFS: —clean?,The '—clean' argument calls the git clean command interactively before compiling. It is useful to remove old build files. +What is achieved by the --clean argument in the build command of ORFS?,The '—clean' argument calls the git clean command interactively before compiling. It is useful to remove old build files. +What does the following argument do in the build command of ORFS: —clean?,"The '--clean' argument triggers an interactive git clean command before compiling, helping remove outdated build files." +What does the following argument do in the build command of ORFS: —clean-force?,This '—clean-force' argument will call git clean before compiling but WARNING: this option will not ask for confirmation. It is useful to remove old build files. +How does the --clean-force argument function in the build command of ORFS?,This '—clean-force' argument will call git clean before compiling but WARNING: this option will not ask for confirmation. It is useful to remove old build files. +What does the following argument do in the build command of ORFS: —clean-force?,"The '--clean-force' command enforces a git clean operation before compilation without seeking user confirmation, aiding in the deletion of old build files." +What function does the following argument serve in the build command of ORFS: -c or --copy-platforms?,This argument is only applicable to docker builds. It is used to copy platforms inside the docker image. +What does the -c or --copy-platforms argument do in the build command of ORFS?,This argument is only applicable to docker builds. It is used to copy platforms inside the docker image. +What function does the following argument serve in the build command of ORFS: -c or --copy-platforms?,"This command is tailored for docker builds, enabling the copying of platforms into the docker image." +What does the following argument do in the build command of ORFS: —docker-args-overwrite?,The ' —docker-args-overwrite' argument is only applicable for docker builds. They specify to not use default flags set by this script for Docker builds. +What modification does the --docker-args-overwrite argument make in the build command of ORFS?,The ' —docker-args-overwrite' argument is only applicable for docker builds. They specify to not use default flags set by this script for Docker builds. +What does the following argument do in the build command of ORFS: —docker-args-overwrite?,"The '--docker-args-overwrite' command is designated for docker builds, instructing not to use the script's default Docker build flags." +What does the following argument do in the build command of ORFS: —docker-args STRING?,This argument is only applicable to docker builds. It is used to add additional compilation flags for the Docker build. +How does the --docker-args STRING argument customize the ORFS build process?,This argument is only applicable to docker builds. It is used to add additional compilation flags for the Docker build. +What does the following argument do in the build command of ORFS: —docker-args STRING?,"This command, specific to docker builds, allows adding extra compilation flags for Docker builds." +"What does the following Synthesis variable, SYNTH_HIERARCHICAL do?","The variable SYNTH_HIERARCHICAL enables synthesis hierarchically, otherwise considered flat synthesis." +What does the SYNTH_HIERARCHICAL variable in Synthesis control?,"The variable SYNTH_HIERARCHICAL enables synthesis hierarchically, otherwise considered flat synthesis." +"What does the following Synthesis variable, SYNTH_HIERARCHICAL do?",SYNTH_HIERARCHICAL toggles between hierarchical and flat synthesis. +"What does the following Synthesis variable, LATCH_MAP_FILE do?",LATCH_MAP_FILE variable specifies the list of latches treated as a black box by Yosys. +What is the purpose of the LATCH_MAP_FILE variable in Synthesis?,LATCH_MAP_FILE variable specifies the list of latches treated as a black box by Yosys. +"What does the following Synthesis variable, LATCH_MAP_FILE do?",LATCH_MAP_FILE lists latches considered as black boxes by Yosys. +"What does the following Synthesis variable, CLKGATE_MAP_FILE do?",This variable specifies a list of cells for the gating clock treated as a black box by Yosys. +How does the CLKGATE_MAP_FILE variable in Synthesis function?,This variable specifies a list of cells for the gating clock treated as a black box by Yosys. +"What does the following Synthesis variable, CLKGATE_MAP_FILE do?",Specifies cells to treat as black boxes for clock gating in Yosys. +"Can you explain the usage of this Synthesis variable, ADDER_MAP_FILE?",List of adders treated as a black box by Yosys. +What does the ADDER_MAP_FILE variable in Synthesis specify?,List of adders treated as a black box by Yosys. +"Can you explain the usage of this Synthesis variable, ADDER_MAP_FILE?",Lists adders treated as black boxes by Yosys. +"What does the following Synthesis variable, TIEHI_CELL_AND_PORT do?","The variable, TIEHI_CELL_AND_PORT is used to tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist." +What does the TIEHI_CELL_AND_PORT variable in Synthesis define?,"The variable, TIEHI_CELL_AND_PORT is used to tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist." +"What does the following Synthesis variable, TIEHI_CELL_AND_PORT do?",TIEHI_CELL_AND_PORT identifies high tie cells used in Yosys synthesis to replace logical 1 in the Netlist. +"What does the following Synthesis variable, TIELO_CELL_AND_PORT do?",This variable is used to tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist. +What does the TIELO_CELL_AND_PORT variable in Synthesis indicate?,This variable is used to tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist. +"What does the following Synthesis variable, TIELO_CELL_AND_PORT do?",Defines low tie cells used in Yosys synthesis to replace logical 0 in the Netlist. +"What does the following Synthesis variable, MIN_BUF_CELL_AND_PORTS do?",The MIN_BUF_CELL_AND_PORTS variable is used to insert a buffer cell to pass through wires. Used in synthesis. +How does the MIN_BUF_CELL_AND_PORTS variable in Synthesis operate?,The MIN_BUF_CELL_AND_PORTS variable is used to insert a buffer cell to pass through wires. Used in synthesis. +"What does the following Synthesis variable, MIN_BUF_CELL_AND_PORTS do?","MIN_BUF_CELL_AND_PORTS inserts a buffer cell for wire pass-through, used in synthesis." +"What does the following Synthesis variable, ABC_CLOCK_PERIOD_IN_PS do?","The variable, ABC_CLOCK_PERIOD_IN_PS is used to specify the clock period to be used by STA during synthesis. Default value read from constraint.sdc." +What does the ABC_CLOCK_PERIOD_IN_PS variable in Synthesis determine?,"The variable, ABC_CLOCK_PERIOD_IN_PS is used to specify the clock period to be used by STA during synthesis. Default value read from constraint.sdc." +"What does the following Synthesis variable, ABC_CLOCK_PERIOD_IN_PS do?","ABC_CLOCK_PERIOD_IN_PS sets the clock period for STA during synthesis, with a default from constraint.sdc." +"What does the following Synthesis variable, ABC_DRIVER_CELL do?",Default driver cell used during ABC synthesis. +What does the ABC_DRIVER_CELL variable in Synthesis specify?,Default driver cell used during ABC synthesis. +"What does the following Synthesis variable, ABC_DRIVER_CELL do?",Specifies the default driver cell for ABC synthesis. +"What does the following Synthesis variable, ABC_LOAD_IN_FF do?","During synthesis, the set_load value specified by this, ABC_LOAD_IN_FF variable is used." +What does the ABC_LOAD_IN_FF variable in Synthesis imply?,"During synthesis, the set_load value specified by this, ABC_LOAD_IN_FF variable is used." +"What does the following Synthesis variable, ABC_LOAD_IN_FF do?",ABC_LOAD_IN_FF sets the load value during synthesis. +"What does the following Synthesis variable, MAX_UNGROUP_SIZE do?","For hierarchical synthesis, this variable ungroups modules of the size given by this variable." +What does the MAX_UNGROUP_SIZE variable in Synthesis control?,"For hierarchical synthesis, this variable ungroups modules of the size given by this variable." +"What does the following Synthesis variable, MAX_UNGROUP_SIZE do?","For hierarchical synthesis, ungroups modules based on specified size." +"Tell me about the Floorplan variable, FLOORPLAN_DEF?",FLOORPLAN_DEF is used to specify the use of the DEF file to initialize floorplan. +Can you explain the FLOORPLAN_DEF variable in Floorplan?,FLOORPLAN_DEF is used to specify the use of the DEF file to initialize floorplan. +"Tell me about the Floorplan variable, FLOORPLAN_DEF?",FLOORPLAN_DEF uses a DEF file to initialize the floorplan. +"Elaborate on the Floorplan variable, PLACE_SITE?",Placement site for core cells defined in the technology LEF file. +What is the role of the PLACE_SITE variable in Floorplan?,Placement site for core cells defined in the technology LEF file. +"Elaborate on the Floorplan variable, PLACE_SITE?",Defines the placement site for core cells in the technology LEF file. +"Describe the use this Floorplan variable, TAPCELL_TCL?",TAPCELL_TCL specifies the path to the Endcap and Welltie cells file. +How does the TAPCELL_TCL variable in Floorplan function?,TAPCELL_TCL specifies the path to the Endcap and Welltie cells file. +"Describe the use this Floorplan variable, TAPCELL_TCL?",TAPCELL_TCL points to the Endcap and Welltie cells file. +"What is the function of the Floorplan variable, RTLMP_FLOW?","This variable, RTLMP_FLOW enables the Hierarchical RTLMP flow. By default it is disabled." +What does the RTLMP_FLOW variable in Floorplan control?,"This variable, RTLMP_FLOW enables the Hierarchical RTLMP flow. By default it is disabled." +"What is the function of the Floorplan variable, RTLMP_FLOW?","RTLMP_FLOW toggles the Hierarchical RTLMP flow, defaulting to off." +"Tell me about the Floorplan variable, MACRO_HALO?","MACRO_HALO specifies to keep out a distance from macro, in X and Y, to standard cell row." +Can you describe the MACRO_HALO variable in Floorplan?,"MACRO_HALO specifies to keep out a distance from macro, in X and Y, to standard cell row." +"Tell me about the Floorplan variable, MACRO_HALO?",MACRO_HALO sets the keep-out distance around macros in X and Y to standard cell rows. +"Tell me about the Floorplan variable, MACRO_PLACEMENT?",MACRO_PLACEMENT specifies the path of a file on how to place certain macros manually using read_macro_placement. +What does the MACRO_PLACEMENT variable in Floorplan specify?,MACRO_PLACEMENT specifies the path of a file on how to place certain macros manually using read_macro_placement. +"Tell me about the Floorplan variable, MACRO_PLACEMENT?",MACRO_PLACEMENT defines manual macro placement through a specified file. +"Elaborate on the Floorplan variable, MACRO_PLACEMENT_TCL?",This variable specifies the path of a TCL file on how to place certain macros manually. +How does the MACRO_PLACEMENT_TCL variable in Floorplan operate?,This variable specifies the path of a TCL file on how to place certain macros manually. +"Elaborate on the Floorplan variable, MACRO_PLACEMENT_TCL?",Specifies a TCL file for manual macro placement. +"Describe the Floorplan variable, MACRO_PLACE_HALO?",Horizontal /vertical halo around macros (microns). Used by automatic macro placement. +What does the MACRO_PLACE_HALO variable in Floorplan indicate?,Horizontal /vertical halo around macros (microns). Used by automatic macro placement. +"Describe the Floorplan variable, MACRO_PLACE_HALO?","Sets the halo around macros for automatic placement, in microns." +"Tell me about the Floorplan variable, MACRO_PLACE_CHANNEL?",Horizontal/vertical channel width between macros (microns). Used by automatic macro placement when RTLMP_FLOW is disabled. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro. +What does the MACRO_PLACE_CHANNEL variable in Floorplan define?,Horizontal/vertical channel width between macros (microns). Used by automatic macro placement when RTLMP_FLOW is disabled. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro. +"Tell me about the Floorplan variable, MACRO_PLACE_CHANNEL?","Determines the channel width between macros for automatic placement, in microns." +"Give me details on the Floorplan variable, MACRO_BLOCKAGE_HALO?",Blockage width overridden from default calculation. +Can you detail the MACRO_BLOCKAGE_HALO variable in Floorplan?,Blockage width overridden from default calculation. +"Give me details on the Floorplan variable, MACRO_BLOCKAGE_HALO?",Overrides the default blockage width calculation. +"Inform me about the Floorplan variable, PDN_TCL?","This variable specifies the file path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps." +What is the purpose of the PDN_TCL variable in Floorplan?,"This variable specifies the file path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps." +"Inform me about the Floorplan variable, PDN_TCL?",Specifies the file path for power grid policies used by pdn. +"Tell me about the Floorplan variable, MAKE_TRACKS.",MAKE_TRACKS variable outlines the Tcl file that defines adding routing tracks to a floorplan. +How does the MAKE_TRACKS variable in Floorplan function?,MAKE_TRACKS variable outlines the Tcl file that defines adding routing tracks to a floorplan. +"Tell me about the Floorplan variable, MAKE_TRACKS.",MAKE_TRACKS outlines a Tcl file for adding routing tracks to a floorplan. +"What is the function of the Floorplan variable, IO_PLACER_H?",The metal layer on which to place the I/O pins horizontally (top and bottom of the die). +What does the IO_PLACER_H variable in Floorplan specify?,The metal layer on which to place the I/O pins horizontally (top and bottom of the die). +"What is the function of the Floorplan variable, IO_PLACER_H?",Specifies the metal layer for horizontal I/O pin placement. +"Inform me about the Floorplan variable, IO_PLACER_V?",The metal layer on which to place the I/O pins vertically (sides of the die). +How does the IO_PLACER_V variable in Floorplan operate?,The metal layer on which to place the I/O pins vertically (sides of the die). +"Inform me about the Floorplan variable, IO_PLACER_V?",Specifies the metal layer for vertical I/O pin placement. +"Tell me about the Floorplan variable, GUI_NO_TIMING?",Skip loading timing for a faster GUI load. +What does the GUI_NO_TIMING variable in Floorplan control?,Skip loading timing for a faster GUI load. +"Tell me about the Floorplan variable, GUI_NO_TIMING?",Skips loading timing for faster GUI loading. +"Give me a description for the following ‘Placement’ tool variable, HAS_IO_CONSTRAINTS?",Skip the initial non-IO based global placement if IO constraints are present. +Can you describe the HAS_IO_CONSTRAINTS variable in the Placement tool?,Skip the initial non-IO based global placement if IO constraints are present. +"Give me a description for the following ‘Placement’ tool variable, HAS_IO_CONSTRAINTS?",Skips initial non-IO based global placement if IO constraints exist. +"Tell me about the ‘Placement’ tool variable, CELL_PAD_IN_SITES_GLOBAL_PLACEMENT?",Cell padding on both sides in site widths to ease routability during global placement. +What does the CELL_PAD_IN_SITES_GLOBAL_PLACEMENT variable in Placement do?,Cell padding on both sides in site widths to ease routability during global placement. +"Tell me about the ‘Placement’ tool variable, CELL_PAD_IN_SITES_GLOBAL_PLACEMENT?",Defines cell padding in site widths for global placement routability. +"What does this ‘Placement’ tool variable, CELL_PAD_IN_SITES_DETAIL_PLACEMENT do?",Cell padding on both sides in site widths to ease routability in detail placement. +How does the CELL_PAD_IN_SITES_DETAIL_PLACEMENT variable in Placement function?,Cell padding on both sides in site widths to ease routability in detail placement. +"What does this ‘Placement’ tool variable, CELL_PAD_IN_SITES_DETAIL_PLACEMENT do?",Defines cell padding in site widths for detail placement routability. +"Give me a description for the following ‘Placement’ tool variable, PLACE_DENSITY?",The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread. +What does the PLACE_DENSITY variable in Placement control?,The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread. +"Give me a description for the following ‘Placement’ tool variable, PLACE_DENSITY?",Sets the desired placement density of cells on the core area. +"What does this ‘Placement’ tool variable, PLACE_DENSITY_LB_ADDON do?",Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists. +How does the PLACE_DENSITY_LB_ADDON variable in Placement operate?,Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists. +"What does this ‘Placement’ tool variable, PLACE_DENSITY_LB_ADDON do?",Adjusts the lower boundary of PLACE_DENSITY with an addon if present. +"State the function of this OpenROAD ‘Placement’ tool variable, REPAIR_PDN_VIA_LAYER?",Remove power grid vias which generate DRC violations after detailed routing. +What does the REPAIR_PDN_VIA_LAYER variable in Placement specify?,Remove power grid vias which generate DRC violations after detailed routing. +"State the function of this OpenROAD ‘Placement’ tool variable, REPAIR_PDN_VIA_LAYER?",Removes power grid vias causing DRC violations after detailed routing. +"Give me a description for the following OpenROAD ‘Placement’ tool variable, GLOBAL_PLACEMENT_ARGS?",Use additional tuning parameters during global placement other than default args defined in gloabl_place.tcl. +Can you explain the GLOBAL_PLACEMENT_ARGS variable in Placement?,Use additional tuning parameters during global placement other than default args defined in gloabl_place.tcl. +"Give me a description for the following OpenROAD ‘Placement’ tool variable, GLOBAL_PLACEMENT_ARGS?",Uses additional parameters for global placement beyond default args. +"What does this OpenROAD ‘Placement’ tool variable, ENABLE_DPO do?",Enable detail placement with improve_placement feature. +What does the ENABLE_DPO variable in Placement do?,Enable detail placement with improve_placement feature. +"What does this OpenROAD ‘Placement’ tool variable, ENABLE_DPO do?",Enables detailed placement improvement. +"Give me a description for the following OpenROAD ‘Placement’ tool variable, DPO_MAX_DISPLACEMENT?",Specifies how far an instance can be moved when optimizing. +How does the DPO_MAX_DISPLACEMENT variable in Placement function?,Specifies how far an instance can be moved when optimizing. +"Give me a description for the following OpenROAD ‘Placement’ tool variable, DPO_MAX_DISPLACEMENT?",Limits instance movement distance during optimization. +"Give me a description for the following OpenROAD ‘Placement’ tool variable, GPL_TIMING_DRIVEN?","In OpenROAD Flow Scripts (ORFS), the GPL_TIMING_DRIVEN variable specifies whether the global placer (gpl) should use timing driven-placement. Timing-driven placement will cause gpl to ocassionally run static timing analysis (sta) during placement in order to determine the timing on each net. gpl will then reweight the nets based on how timing-critical they are. This process improves the timing of the netlist by decreasing the distance between timing-critical cells, but it also causes an increase in gpl runtime due to running timing analysis." +What does the GPL_TIMING_DRIVEN variable in Placement control?,"In OpenROAD Flow Scripts (ORFS), the GPL_TIMING_DRIVEN variable specifies whether the global placer (gpl) should use timing driven-placement. Timing-driven placement will cause gpl to ocassionally run static timing analysis (sta) during placement in order to determine the timing on each net. gpl will then reweight the nets based on how timing-critical they are. This process improves the timing of the netlist by decreasing the distance between timing-critical cells, but it also causes an increase in gpl runtime due to running timing analysis." +"Give me a description for the following OpenROAD ‘Placement’ tool variable, GPL_TIMING_DRIVEN?","GPL_TIMING_DRIVEN toggles timing-driven global placement, affecting gpl runtime and netlist timing." +"Give me a description for the following OpenROAD ‘Placement’ tool variable, GPL_ROUTABILITY_DRIVEN?","In OpenROAD Flow Scripts (ORFS), the GPL_ROUTABILITY_DRIVEN variable specifies whether the global placer (gpl) should use routability driven-placement. Routability-driven placement will cause gpl to ocassionally run global routing (grt) during placement in order to determine routing congestion hotspots. gpl will then reweight the nets based on how congestion data. This process improves the routability of the netlist by spacing out cells in routing congested areas, but it also causes an increase in gpl runtime due to running global routing." +How does the GPL_ROUTABILITY_DRIVEN variable in Placement operate?,"In OpenROAD Flow Scripts (ORFS), the GPL_ROUTABILITY_DRIVEN variable specifies whether the global placer (gpl) should use routability driven-placement. Routability-driven placement will cause gpl to ocassionally run global routing (grt) during placement in order to determine routing congestion hotspots. gpl will then reweight the nets based on how congestion data. This process improves the routability of the netlist by spacing out cells in routing congested areas, but it also causes an increase in gpl runtime due to running global routing." +"Give me a description for the following OpenROAD ‘Placement’ tool variable, GPL_ROUTABILITY_DRIVEN?","GPL_ROUTABILITY_DRIVEN toggles routability-driven global placement, influencing gpl runtime and netlist routability." +"Give me a description for the following OpenROAD ‘Placement’ tool variable, CAP_MARGIN?",Specifies a capacitance margin when fixing max capacitance violations. This option allow you to overfix. +What does the CAP_MARGIN variable in Placement specify?,Specifies a capacitance margin when fixing max capacitance violations. This option allow you to overfix. +"Give me a description for the following OpenROAD ‘Placement’ tool variable, CAP_MARGIN?",Sets a capacitance margin for overfixing max capacitance violations. +"Give me a description for the following OpenROAD ‘Placement’ tool variable, SLEW_MARGIN?",Specifies a slew margin when fixing max slew violations. This option allow you to overfix. +How does the SLEW_MARGIN variable in Placement function?,Specifies a slew margin when fixing max slew violations. This option allow you to overfix. +"Give me a description for the following OpenROAD ‘Placement’ tool variable, SLEW_MARGIN?",Sets a slew margin for overfixing max slew violations. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, CTS_ARGS?",Override clock_tree_synthesis arguments +What does the CTS_ARGS variable in Clock Tree Synthesis control?,Override clock_tree_synthesis arguments +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, CTS_ARGS?",Overrides arguments for clock tree synthesis. +What does CTS_BUF_CELL do in ORFS?,The CTS_BUF_CELL variable sets the root buffer cell used in the clock tree during clock tree synthesis (CTS) +What is the purpose of the CTS_BUF_CELL variable in ORFS?,The CTS_BUF_CELL variable sets the root buffer cell used in the clock tree during clock tree synthesis (CTS) +What does CTS_BUF_CELL do in ORFS?,CTS_BUF_CELL selects the root buffer cell for clock tree synthesis. +What is the use of the ORFS variable FILL_CELLS?,The FILL_CELLS variable holds a list of cell names to use as filler cells. Wildcard patterns (*) are supported. Fill cells are used to fill empty cell sites which aids in satisfying design rules and density rules. +How does the FILL_CELLS variable in ORFS function?,The FILL_CELLS variable holds a list of cell names to use as filler cells. Wildcard patterns (*) are supported. Fill cells are used to fill empty cell sites which aids in satisfying design rules and density rules. +What is the use of the ORFS variable FILL_CELLS?,"FILL_CELLS lists cell names for filler cells, supporting wildcards." +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, HOLD_SLACK_MARGIN?",Specifies a time margin for the slack when fixing hold violations. This option allow you to overfix. +What does the HOLD_SLACK_MARGIN variable in Clock Tree Synthesis specify?,Specifies a time margin for the slack when fixing hold violations. This option allow you to overfix. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, HOLD_SLACK_MARGIN?",Specifies a time margin for fixing hold violations. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SETUP_SLACK_MARGIN?",Specifies a time margin for the slack when fixing setup violations. +How does the SETUP_SLACK_MARGIN variable in Clock Tree Synthesis operate?,Specifies a time margin for the slack when fixing setup violations. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SETUP_SLACK_MARGIN?",Specifies a time margin for setup violation fixes. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SKIP_GATE_CLONING?",Do not use gate cloning transform to fix timing violations (default: use gate cloning) +What does the SKIP_GATE_CLONING variable in Clock Tree Synthesis control?,Do not use gate cloning transform to fix timing violations (default: use gate cloning) +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SKIP_GATE_CLONING?",Disables gate cloning for timing violation fixes. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SKIP_PIN_SWAP?",Do not use pin swapping as a transform to fix timing violations (default: use pin swapping) +What does the SKIP_PIN_SWAP variable in Clock Tree Synthesis indicate?,Do not use pin swapping as a transform to fix timing violations (default: use pin swapping) +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SKIP_PIN_SWAP?",Disables pin swapping for timing violation fixes. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, TNS_END_PERCENT?","In OpenROAD Flow Scripts, the TNS_END_PERCENT variable specifies what percent of violating timing paths will be fixed during timing optimization. TNS_END_PERCENT must be a floating point value between 0-100. However, even if TNS_END_PERCENT is 0, the worst path will always be fixed. The purpose of this flag is to allow the user some control over how much runtime and logic area is spent on timing optimization, with a higher value leading to more runtime/area and a lower value leading to less runtime/area." +How does the TNS_END_PERCENT variable in Clock Tree Synthesis function?,"In OpenROAD Flow Scripts, the TNS_END_PERCENT variable specifies what percent of violating timing paths will be fixed during timing optimization. TNS_END_PERCENT must be a floating point value between 0-100. However, even if TNS_END_PERCENT is 0, the worst path will always be fixed. The purpose of this flag is to allow the user some control over how much runtime and logic area is spent on timing optimization, with a higher value leading to more runtime/area and a lower value leading to less runtime/area." +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, TNS_END_PERCENT?",TNS_END_PERCENT defines the percent of timing path fixes during optimization. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, EQUIVALENCE_CHECK?","In OpenROAD Flow Scripts, the EQUIVALENCE_CHECK variable toggles whether a logical equivalence check is run after timing optimization to ensure logical correctness of the circuit. If EQUIVALENCE_CHECK is 1, the check is performed. If EQUIVALENCE_CHECK is any other value or unset, the check is not run. The default value is unset." +What does the EQUIVALENCE_CHECK variable in Clock Tree Synthesis specify?,"In OpenROAD Flow Scripts, the EQUIVALENCE_CHECK variable toggles whether a logical equivalence check is run after timing optimization to ensure logical correctness of the circuit. If EQUIVALENCE_CHECK is 1, the check is performed. If EQUIVALENCE_CHECK is any other value or unset, the check is not run. The default value is unset." +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, EQUIVALENCE_CHECK?",EQUIVALENCE_CHECK toggles logical equivalence checks post-optimization. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, REMOVE_CELLS_FOR_EQY?","In OpenROAD Flow Scripts, the REMOVE_CELLS_FOR_EQY variable sets the list of cells to remove from the verilog netlist file produced specifically for netlist equivalence checking. Netlist equivalence checking is performed with the Yosys EQY tool. Wildcard patterns (*) are supported. This variable is passed directly to write_verilog -remove_cells <>." +How does the REMOVE_CELLS_FOR_EQY variable in Clock Tree Synthesis operate?,"In OpenROAD Flow Scripts, the REMOVE_CELLS_FOR_EQY variable sets the list of cells to remove from the verilog netlist file produced specifically for netlist equivalence checking. Netlist equivalence checking is performed with the Yosys EQY tool. Wildcard patterns (*) are supported. This variable is passed directly to write_verilog -remove_cells <>." +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, REMOVE_CELLS_FOR_EQY?",REMOVE_CELLS_FOR_EQY lists cells to exclude from equivalence checking netlist files. +What is the difference between Yosys and OpenROAD?,Yosys is a logic synthesis tool which is responsible for transforming register transfer-level (RTL) code into a gate-level netlist. OpenROAD is a place and route (P&R) tool which is responsible for implementing a gale-level netlist into a chip layout. Yosys is developed by the YosysHQ organization whereas OpenROAD is developed by The OpenROAD Project. OpenROAD Flow Scripts (ORFS) makes use of both of these tools (as well as KLayout) to form a full RTL-to-GDS flow. +Can you contrast Yosys with OpenROAD in terms of functionality?,Yosys is a logic synthesis tool which is responsible for transforming register transfer-level (RTL) code into a gate-level netlist. OpenROAD is a place and route (P&R) tool which is responsible for implementing a gale-level netlist into a chip layout. Yosys is developed by the YosysHQ organization whereas OpenROAD is developed by The OpenROAD Project. OpenROAD Flow Scripts (ORFS) makes use of both of these tools (as well as KLayout) to form a full RTL-to-GDS flow. +What is the difference between Yosys and OpenROAD?,"Yosys transforms RTL code into a gate-level netlist, while OpenROAD handles P&R from netlist to chip layout." +Is there a simple way to open the GUI in ORFS?,"OpenROAD Flow Scripts (ORFS) includes Makefile targets to open the GUI after each step. You can use the command make gui_*, where * is the name of the flow step (e.g. make_floorplan)." +Is there a straightforward method to launch the GUI in ORFS?,"OpenROAD Flow Scripts (ORFS) includes Makefile targets to open the GUI after each step. You can use the command make gui_*, where * is the name of the flow step (e.g. make_floorplan)." +Is there a simple way to open the GUI in ORFS?,OpenROAD Flow Scripts include Makefile targets for GUI access after flow steps. \ No newline at end of file diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/Flow/Flow.xlsx b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/Flow/Flow.xlsx new file mode 100644 index 0000000..3cfbe75 Binary files /dev/null and b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/Flow/Flow.xlsx differ diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/General/General.csv b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/General/General.csv new file mode 100644 index 0000000..34124e7 --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/General/General.csv @@ -0,0 +1,216 @@ +Prompts,Answers +What is PDNGEN?,"The PDNGEN module (pdn) in OpenROAD aims to simplify the process of adding a power grid into a floorplan. A user can specify a small set of power grid policies to be applied to the design, such as the layers to use, stripe width, and spacing, and then pdn will generate the actual metal straps. Power grid policies can be defined over both the standard cell area and areas occupied by macros." +What is the essence of PDNGEN?,"The PDNGEN module (pdn) in OpenROAD aims to simplify the process of adding a power grid into a floorplan. A user can specify a small set of power grid policies to be applied to the design, such as the layers to use, stripe width, and spacing, and then pdn will generate the actual metal straps. Power grid policies can be defined over both the standard cell area and areas occupied by macros." +What is PDNGEN?,"OpenROAD's Power Distribution Network Generator (PDNGEN) module, abbreviated as pdn, streamlines the integration of a power grid into a design's floorplan. Users can establish a few power grid guidelines, such as selecting layers, setting stripe width, and spacing, after which pdn automatically constructs the metal straps. These guidelines can be applied across both the standard cell region and macro-occupied areas." +What is the structure of OpenDB?,The structure of OpenDB is based on the text file formats LEF (library) and DEF (design) formats version 5.6. OpenDB supports a binary file format to save and load the design much faster than using LEF and DEF. OpenDB is written in C++ 98 with standard library-style iterators. The classes are designed to be fast enough to base an application on without having to copy them into application-specific structures. +Can you describe the architecture of OpenDB?,The structure of OpenDB is based on the text file formats LEF (library) and DEF (design) formats version 5.6. OpenDB supports a binary file format to save and load the design much faster than using LEF and DEF. OpenDB is written in C++ 98 with standard library-style iterators. The classes are designed to be fast enough to base an application on without having to copy them into application-specific structures. +What is the structure of OpenDB?,"OpenDB's architecture mirrors the LEF (Library Exchange Format) and DEF (Design Exchange Format) text file standards version 5.6, supporting a binary file format for quicker design saving and loading than possible with LEF and DEF. Written in C++ 98, OpenDB employs standard library-style iterators and classes designed for rapid operation, obviating the need for copying into specific application structures." +How is FastRoute better than previous routing frameworks?,"FastRoute innovates over prior routing frameworks because it integrates several novel techniques: fast congestion-driven via-aware Steiner tree construction, 3-bend routing, virtual capacity adjustment, multi-source multi-sink maze routing, and spiral layer assignment. These techniques not only address the routing congestion measured at the edges of global routing grids but also minimize the total wirelength and via usage, which is critical for subsequent detailed routing, yield, and manufacturability. Experimental results show that FastRoute is highly effective and efficient in solving ISPD07 and ISPD08 global routing benchmark suites. The results outperform recently published academic global routers in both routability and runtime. In particular, for ISPD07 and ISPD08 global routing benchmarks, FastRoute generates 12 congestion-free solutions out of 16 benchmarks with a speed significantly faster than other routers." +In what ways is FastRoute superior to its predecessors in routing frameworks?,"FastRoute innovates over prior routing frameworks because it integrates several novel techniques: fast congestion-driven via-aware Steiner tree construction, 3-bend routing, virtual capacity adjustment, multi-source multi-sink maze routing, and spiral layer assignment. These techniques not only address the routing congestion measured at the edges of global routing grids but also minimize the total wirelength and via usage, which is critical for subsequent detailed routing, yield, and manufacturability. Experimental results show that FastRoute is highly effective and efficient in solving ISPD07 and ISPD08 global routing benchmark suites. The results outperform recently published academic global routers in both routability and runtime. In particular, for ISPD07 and ISPD08 global routing benchmarks, FastRoute generates 12 congestion-free solutions out of 16 benchmarks with a speed significantly faster than other routers." +How is FastRoute better than previous routing frameworks?,"FastRoute distinguishes itself from previous routing frameworks by integrating innovative approaches such as fast congestion-driven via-aware Steiner tree construction, 3-bend routing, virtual capacity adjustment, multi-source multi-sink maze routing, and spiral layer assignment. These methods tackle routing congestion at global routing grid edges and aim to minimize overall wirelength and via count, vital for detailed routing, yield, and manufacturability. According to tests, FastRoute excels in efficiency and effectiveness across ISPD07 and ISPD08 global routing benchmarks, outperforming contemporary academic routers in routability and speed, delivering congestion-free outcomes for 12 out of 16 benchmarks." +What does RTLMP do?,"A macro placer (MP) is an algorithm which specifically focuses on placing macros in the core area. RTL­MP is a novel macro placer that utilizes RTL information and tries to “mimic” the interaction between the frontend RTL designer and the back­ end physical design engineer to produce human­-quality floorplans. By exploiting the logical hierarchy and processing logical modules based on connection signatures, RTL­MP can capture the dataflow inherent in the RTL and use the dataflow information to guide macro placement." +What tasks does RTLMP accomplish?,"A macro placer (MP) is an algorithm which specifically focuses on placing macros in the core area. RTL­MP is a novel macro placer that utilizes RTL information and tries to “mimic” the interaction between the frontend RTL designer and the back­ end physical design engineer to produce human­-quality floorplans. By exploiting the logical hierarchy and processing logical modules based on connection signatures, RTL­MP can capture the dataflow inherent in the RTL and use the dataflow information to guide macro placement." +What does RTLMP do?,"A macro placer (MP) specifically targets macro placement within the core area. The novel RTL­MP leverages RTL data to emulate the collaborative process between frontend RTL designers and backend physical design engineers, producing floorplans of comparable quality to human-generated ones. By analyzing logical hierarchies and connections, RTL­MP captures the RTL's inherent data flow to inform its macro placement strategy." +What was the need to develop Hier-RTLMP?,"Recently, with the increasing complexity of IP blocks, and in particular with auto-generated RTL for machine learning (ML) accelerators, the number of macros in a single RTL block can easily run into several hundred. This makes the task of generating an automatic floorplan (.def) with IO pin and macro placements for front-end physical synthesis even more critical and challenging. The so-called peripheral approach of forcing macros to the periphery of the layout is no longer viable when the ratio of the sum of the macro perimeters to the floorplan perimeter is large since this increases the required stacking depth of macros. Thus, a novel multilevel physical planning approach that exploits the hierarchy and dataflow inherent in the design RTL, and describes its realization in a new hierarchical macro placer, Hier-RTLMP was developed. " +What prompted the creation of Hier-RTLMP?,"Recently, with the increasing complexity of IP blocks, and in particular with auto-generated RTL for machine learning (ML) accelerators, the number of macros in a single RTL block can easily run into several hundred. This makes the task of generating an automatic floorplan (.def) with IO pin and macro placements for front-end physical synthesis even more critical and challenging. The so-called peripheral approach of forcing macros to the periphery of the layout is no longer viable when the ratio of the sum of the macro perimeters to the floorplan perimeter is large since this increases the required stacking depth of macros. Thus, a novel multilevel physical planning approach that exploits the hierarchy and dataflow inherent in the design RTL, and describes its realization in a new hierarchical macro placer, Hier-RTLMP was developed. " +What was the need to develop Hier-RTLMP?,"The increasing complexity of IP blocks, especially auto-generated RTL for machine learning (ML) accelerators, has led to designs with hundreds of macros. This escalates the difficulty of automatically generating a floorplan (.def) that includes IO pin and macro placements for front-end physical synthesis. The traditional peripheral placement strategy becomes impractical when the macro perimeter sum greatly exceeds the floorplan's perimeter, necessitating a novel multilevel physical planning approach. This approach, realized in the Hier-RTLMP, leverages design RTL's inherent hierarchy and data flow for effective macro placement." +How is Hier-RTLMP different from RTL-MP?,"Hier-RTLMP consists of an auto-clustering engine that transforms the logical hierarchy into a physical hierarchy. Unlike RTL-MP where the physical hierarchy is a single level, Hier-RTLMP’s autoclustering engine creates a multilevel physical hierarchy of physical clusters. This enables the handling of large RTLs with hundreds of macros and allows for the placement of macros within the core area." +In what aspects does Hier-RTLMP diverge from RTL-MP?,"Hier-RTLMP consists of an auto-clustering engine that transforms the logical hierarchy into a physical hierarchy. Unlike RTL-MP where the physical hierarchy is a single level, Hier-RTLMP’s autoclustering engine creates a multilevel physical hierarchy of physical clusters. This enables the handling of large RTLs with hundreds of macros and allows for the placement of macros within the core area." +How is Hier-RTLMP different from RTL-MP?,"Hier-RTLMP introduces an auto-clustering engine that converts logical hierarchies into a multilevel physical structure. Unlike the single-level physical hierarchy in RTL-MP, Hier-RTLMP's engine facilitates managing extensive RTL designs with numerous macros, allowing for their strategic placement within the core area." +How does FastRoute work?,"The first part of the FastRoute framework is topology generation. Because FastRoute tries to avoid rip-up and reroute to reduce both wirelength and runtime, the initial tree topology has significant impacts. With the congestion-driven and via-aware topology, the next stage of FastRoute is actual routing. We find that there exists significant potential to improve traditional routing techniques in terms of via control and congestion reduction. The most commonly used routing techniques in global routing include L/Z/U pattern routing, monotonic routing, and maze routing. In addition to new topology and routing techniques, Fast Route integrates several performance enhancement techniques to further improve routing quality and reduce run time." +Can you explain the operating principle of FastRoute?,"The first part of the FastRoute framework is topology generation. Because FastRoute tries to avoid rip-up and reroute to reduce both wirelength and runtime, the initial tree topology has significant impacts. With the congestion-driven and via-aware topology, the next stage of FastRoute is actual routing. We find that there exists significant potential to improve traditional routing techniques in terms of via control and congestion reduction. The most commonly used routing techniques in global routing include L/Z/U pattern routing, monotonic routing, and maze routing. In addition to new topology and routing techniques, Fast Route integrates several performance enhancement techniques to further improve routing quality and reduce run time." +How does FastRoute work?,"FastRoute's framework begins with topology generation, aiming to minimize rip-up and reroute actions to reduce wirelength and runtime. The initial tree topology, based on congestion-driven and via-aware principles, sets the stage for the routing phase, which shows significant improvement opportunities over traditional methods in terms of via management and congestion alleviation. Besides innovative topology and routing strategies, FastRoute incorporates various performance-boosting techniques to enhance routing quality and efficiency." +Why is RSMT used more?,"Traditionally, global routing just uses tree structures like RMST or RSMT while RSMT is becoming more popular due to its minimal wirelength to connect a multi-pin net." +Why is RSMT favored over other methods?,"Traditionally, global routing just uses tree structures like RMST or RSMT while RSMT is becoming more popular due to its minimal wirelength to connect a multi-pin net." +Why is RSMT used more?,"Global routing traditionally utilizes tree structures such as RMST or RSMT, with RSMT growing in preference due to its efficiency in connecting multi-pin nets with minimal wirelength." +"Tab completion does work in console mode but not in GUI mode, why?","The OpenROAD GUI is made from custom Qt code and does not apply to the console. OpenROAD relies on the tclreadline package, which doesn't work well with imported namespaces." +Why does tab completion function in console mode but fail in GUI mode?,"The OpenROAD GUI is made from custom Qt code and does not apply to the console. OpenROAD relies on the tclreadline package, which doesn't work well with imported namespaces." +"Tab completion does work in console mode but not in GUI mode, why?","The OpenROAD GUI is built using custom Qt programming and is not applicable to command-line operations. It utilizes the tclreadline package, which faces compatibility issues with imported namespaces." +What is OpenDB?,"OpenDB is a design database to support tools for physical chip design. It was originally developed by Athena Design Systems. Nefelus, Inc. acquired the rights to the code and open-sourced it with BSD-3 license in 2019 to support the DARPA OpenROAD project. The structure of OpenDB is based on the text file formats LEF (library) and DEF (design) formats version 5.6. OpenDB supports a binary file format to save and load the design much faster than using LEF and DEF. OpenDB is written in C++ 98 with standard library style iterators. The classes are designed to be fast enough to base an application on without having to copy them into application-specific structures." +What is the role of OpenDB?,"OpenDB is a design database to support tools for physical chip design. It was originally developed by Athena Design Systems. Nefelus, Inc. acquired the rights to the code and open-sourced it with BSD-3 license in 2019 to support the DARPA OpenROAD project. The structure of OpenDB is based on the text file formats LEF (library) and DEF (design) formats version 5.6. OpenDB supports a binary file format to save and load the design much faster than using LEF and DEF. OpenDB is written in C++ 98 with standard library style iterators. The classes are designed to be fast enough to base an application on without having to copy them into application-specific structures." +What is OpenDB?,"OpenDB, originally developed by Athena Design Systems and later open-sourced by Nefelus, Inc. under a BSD-3 license for the DARPA OpenROAD project in 2019, serves as a database for physical chip design, utilizing LEF and DEF formats version 5.6 and supporting a binary format for efficient design loading and saving." +What is Automatic Code Generator used for?,The automatic code generator in OpenROAD is used to generate code for OpenDB objects and Iterators. It uses JSON input and automatically generates corresponding C++ files +What is the purpose behind the Automatic Code Generator?,The automatic code generator in OpenROAD is used to generate code for OpenDB objects and Iterators. It uses JSON input and automatically generates corresponding C++ files +What is Automatic Code Generator used for?,"OpenROAD's automatic code generator produces C++ files for OpenDB objects and iterators from JSON input, streamlining code generation." +What commands are used to read and write design data in OpenROAD?,"OpenROAD is run using Tcl scripts. The following commands are used to read and write design data. +read_lef [-tech] [-library] filename +read_def filename +write_def [-version 5.8|5.7|5.6|5.5|5.4|5.3] filename +read_verilog filename +write_verilog filename +read_db filename +write_db filename +write_abstract_lef filename" +"What support does OpenROAD have for Abstract LEF? +",OpenROAD contains an abstract LEF writer that can take your current design and emit an abstract LEF representing the external pins of your design and metal obstructions. Use the write_abstract_lef command to generate the abstract LEF. +How does OpenROAD support Abstract LEF?,OpenROAD contains an abstract LEF writer that can take your current design and emit an abstract LEF representing the external pins of your design and metal obstructions. Use the write_abstract_lef command to generate the abstract LEF. +"What support does OpenROAD have for Abstract LEF? +","The abstract LEF writer in OpenROAD allows for the creation of an abstract LEF from your design, detailing external pins and metal obstructions, using the write_abstract_lef command." +How does OpenROAD compute the die area when using the core_utilization argument in the initialize_floorplan?,"To compute the die area for the initialize_floorplan command, OpenROAD first calculates the core area by dividing the total logic area of the instances coming from synthesis and by the specified core_utilization. OpenROAD then shapes that core area based on the aspect_ratio parameter. Finally, OpenROAD expands the core area by adding a core margin on each edge of the core area. Altogether, this forms the die area." +How does OpenROAD determine die area with the core_utilization argument during floorplan initialization?,"To compute the die area for the initialize_floorplan command, OpenROAD first calculates the core area by dividing the total logic area of the instances coming from synthesis and by the specified core_utilization. OpenROAD then shapes that core area based on the aspect_ratio parameter. Finally, OpenROAD expands the core area by adding a core margin on each edge of the core area. Altogether, this forms the die area." +How does OpenROAD compute the die area when using the core_utilization argument in the initialize_floorplan?,"To calculate die area, OpenROAD first determines the core area by dividing the total logic area by the core utilization, shapes this area using the aspect ratio, and then expands it by adding core margins, resulting in the die area." +I would like to know if there is any way to write the log output from OpenROAD into a file (using a report_ type command)?,"To capture output from OpenROAD, you can use standard Unix file operations and redirections. OpenROAD outputs all messages directly to the stdout I/O stream." +Is there a method to direct OpenROAD's log output to a file?,"To capture output from OpenROAD, you can use standard Unix file operations and redirections. OpenROAD outputs all messages directly to the stdout I/O stream." +I would like to know if there is any way to write the log output from OpenROAD into a file (using a report_ type command)?,"Capturing OpenROAD output can be done using standard Unix redirections, as it sends all messages directly to the stdout stream." +What is the minimum number of metal layers OpenROAD can route in?,"OpenROAD has the theoretical ability to route as few as two layers, but it has rarely been tried by the developers due to the lack of a specialized channel router. It is expected that OpenROAD will hit some issues and have to iterate. If you try this and run into issues, please kindly file an issue on GitHub. However, if the PDK is proprietary, it will be more difficult for the OpenROAD team to diagnose and debug." +What is the minimum metal layer count that OpenROAD can handle for routing?,"OpenROAD has the theoretical ability to route as few as two layers, but it has rarely been tried by the developers due to the lack of a specialized channel router. It is expected that OpenROAD will hit some issues and have to iterate. If you try this and run into issues, please kindly file an issue on GitHub. However, if the PDK is proprietary, it will be more difficult for the OpenROAD team to diagnose and debug." +What is the minimum number of metal layers OpenROAD can route in?,"OpenROAD theoretically can route with as few as two layers, but this is rarely tested and may encounter issues, for which feedback on GitHub is appreciated, especially for proprietary PDKs." +"Can OpenROAD work with multi-VT cells (HVT, LVT, SVT) and swap between them in a single run?","OpenROAD supports using multi-VT cell libraries, and it can swap between VT cells during optimization." +Can OpenROAD manage cells with different threshold voltages within a single run?,"OpenROAD supports using multi-VT cell libraries, and it can swap between VT cells during optimization." +"Can OpenROAD work with multi-VT cells (HVT, LVT, SVT) and swap between them in a single run?","OpenROAD allows the use of multi-VT cell libraries, enabling swapping between VT cells during optimization phases." +Can OpenROAD work with Multi-Mode-Multi-Corner Files (mmmc) ?,"OpenROAD supports multi-corner Static Timing Analysis (STA), but it doesn't currently support multi-mode STA. ""MMMC"" files from proprietary tools are stored in proprietary formats, which OpenROAD cannot support. The OpenSTA manual will contain more information about how to run multi-corner analysis." +Is OpenROAD compatible with Multi-Mode-Multi-Corner Files?,"OpenROAD supports multi-corner Static Timing Analysis (STA), but it doesn't currently support multi-mode STA. ""MMMC"" files from proprietary tools are stored in proprietary formats, which OpenROAD cannot support. The OpenSTA manual will contain more information about how to run multi-corner analysis." +Can OpenROAD work with Multi-Mode-Multi-Corner Files (mmmc) ?,"While OpenROAD supports multi-corner Static Timing Analysis, it does not yet accommodate multi-mode STA due to proprietary format constraints of ""MMMC"" files." +What does Antenna Rule Checker do?,"This tool checks antenna violations and generates a report to indicate violated nets. See LEF/DEF 5.8 Language Reference, Appendix C, ""Calculating and Fixing Process Antenna Violations"" (p.389) for a description of antenna violations." +How does the Antenna Rule Checker contribute to design integrity?,"This tool checks antenna violations and generates a report to indicate violated nets. See LEF/DEF 5.8 Language Reference, Appendix C, ""Calculating and Fixing Process Antenna Violations"" (p.389) for a description of antenna violations." +What does Antenna Rule Checker do?,"The tool checks for antenna violations and reports nets that violate these rules, with guidance found in the LEF/DEF 5.8 Language Reference." +What is Clock Tree Synthesis in OpenROAD?,"Clock tree synthesis (CTS) is the step of distributing a clock to all endpoints (such as flip-flops) while trying to minimize power and skew (the different in clock arrival times between two registers). The clock tree synthesis module in OpenROAD (cts) is based on TritonCTS 2.0, and can be run using the clock_tree_synthesis command. TritonCTS 2.0 features on-the-fly characterization, and therefore does not need to pre-generate characterization data. The on-the-fly characterization feature can be optionally controlled by parameters specified by the configure_cts_characterization command. You can use the set_wire_rc command to set the clock routing layer used when calculating parasitics in this step." +What entails Clock Tree Synthesis in OpenROAD?,"Clock tree synthesis (CTS) is the step of distributing a clock to all endpoints (such as flip-flops) while trying to minimize power and skew (the different in clock arrival times between two registers). The clock tree synthesis module in OpenROAD (cts) is based on TritonCTS 2.0, and can be run using the clock_tree_synthesis command. TritonCTS 2.0 features on-the-fly characterization, and therefore does not need to pre-generate characterization data. The on-the-fly characterization feature can be optionally controlled by parameters specified by the configure_cts_characterization command. You can use the set_wire_rc command to set the clock routing layer used when calculating parasitics in this step." +What is Clock Tree Synthesis in OpenROAD?,"Clock tree synthesis in OpenROAD, facilitated by TritonCTS 2.0, distributes clock signals to endpoints while minimizing power and skew, offering on-the-fly characterization to avoid pre-generated data needs." +Tell me about Detailed Placement in OpenROAD?,"The detailed placement module in OpenROAD (dpl) is based on OpenDP or Open-Source Detailed Placement Engine. Its key features are +fence region and fragmented ROWs." +What does Detailed Placement involve in OpenROAD?,"The detailed placement module in OpenROAD (dpl) is based on OpenDP or Open-Source Detailed Placement Engine. Its key features are +fence region and fragmented ROWs." +Tell me about Detailed Placement in OpenROAD?,"The detailed placement module, based on OpenDP, focuses on fence regions and fragmented rows for placement optimization." +Describe the Restructure module in OpenROAD?,The restructure module in OpenROAD (rmp) is based on an interface to ABC for local resynthesis. The package allows logic restructuring that targets area or timing. It extracts a cloud of logic using the OpenSTA timing engine and passes it to ABC through the blif interface. Multiple recipes for area or timing are run to obtain multiple structures from ABC; the most desirable among these is used to improve the netlist. The ABC output is read back by a blif reader which is integrated into OpenDB. Blif writer and reader also support constants from and to OpenDB. Reading back of constants requires insertion of tie cells which should be provided by the user as per the interface described below. +Can you outline the Restructure module's role in OpenROAD?,The restructure module in OpenROAD (rmp) is based on an interface to ABC for local resynthesis. The package allows logic restructuring that targets area or timing. It extracts a cloud of logic using the OpenSTA timing engine and passes it to ABC through the blif interface. Multiple recipes for area or timing are run to obtain multiple structures from ABC; the most desirable among these is used to improve the netlist. The ABC output is read back by a blif reader which is integrated into OpenDB. Blif writer and reader also support constants from and to OpenDB. Reading back of constants requires insertion of tie cells which should be provided by the user as per the interface described below. +Describe the Restructure module in OpenROAD?,"The restructure module interfaces with ABC for logic resynthesis aimed at area or timing improvement, utilizing OpenSTA for logic extraction and integrating ABC's output through OpenDB's blif reader and writer." +Describe Parallax Static Timing Analyzer or OpenSTA?,"OpenSTA is a gate-level static timing verifier. As a stand-alone executable, it can be used to verify the timing of a design using standard file formats. OpenSTA uses a TCL command interpreter to read the design, specify timing constraints, and print timing reports." +What capabilities does the Parallax Static Timing Analyzer offer?,"OpenSTA is a gate-level static timing verifier. As a stand-alone executable, it can be used to verify the timing of a design using standard file formats. OpenSTA uses a TCL command interpreter to read the design, specify timing constraints, and print timing reports." +Describe Parallax Static Timing Analyzer or OpenSTA?,"OpenSTA performs gate-level static timing analysis, using TCL for design reading, timing constraints specification, and timing report generation." +What is DFT?,This tool is an implementation of Design For Testing. New nets and logic are added to allow IC designs to be tested for errors in manufacturing. Physical imperfections can cause hard failures and variability can cause timing errors. +Can you elaborate on DFT?,This tool is an implementation of Design For Testing. New nets and logic are added to allow IC designs to be tested for errors in manufacturing. Physical imperfections can cause hard failures and variability can cause timing errors. +What is DFT?,"This tool implements Design For Testing (DFT) by introducing new nets and logic, facilitating the testing of IC designs for manufacturing errors. It addresses physical defects and variability, which can lead to hard failures and timing errors, respectively." +What is Read UPF Utility?,"This module contains functionality to read, and modify information from Unified Power Format (UPF) files." +What functionality does the Read UPF Utility offer?,"This module contains functionality to read, and modify information from Unified Power Format (UPF) files." +What is Read UPF Utility?,This module offers tools to access and alter information within Unified Power Format (UPF) files. +Explain Chip-level Connections in OpenROAD?,"The chip-level connections module in OpenROAD (pad) is based on the open-source tool ICeWall. In this utility, either place an IO ring around the boundary of the chip and connect with either wirebond pads or a bump array." +How are chip-level connections managed in OpenROAD?,"The chip-level connections module in OpenROAD (pad) is based on the open-source tool ICeWall. In this utility, either place an IO ring around the boundary of the chip and connect with either wirebond pads or a bump array." +Explain Chip-level Connections in OpenROAD?,"OpenROAD's chip-level connections module (pad) utilizes the open-source ICeWall tool to place an IO ring around the chip's boundary, connecting through wirebond pads or a bump array." +Brief me on the parasitics extraction module?,"The parasitics extraction module in OpenROAD (rcx) is based on the open-source OpenRCX, a Parasitic Extraction (PEX, or RCX) tool that works on OpenDB design APIs. It extracts routed designs based on the LEF/DEF layout model. +OpenRCX extracts both Resistance and Capacitance for wires, based on coupling distance to the nearest wire and the track density context over and/or under the wire of interest, as well as cell abstracts. The capacitance and resistance measurements are based on equations of coupling distance interpolated on exact measurements from a calibration file, called the Extraction Rules file. The Extraction Rules file (RC technology file) is generated once for every process node and corner, using a provided utility for DEF wire pattern generation and regression modeling. +OpenRCX stores resistance, coupling capacitance, and ground (i.e., grounded) capacitance on OpenDB objects with direct pointers to the associated wire and via db objects. Optionally, OpenRCX can generate a .spef file." +Can you brief me on the parasitics extraction module?,"The parasitics extraction module in OpenROAD (rcx) is based on the open-source OpenRCX, a Parasitic Extraction (PEX, or RCX) tool that works on OpenDB design APIs. It extracts routed designs based on the LEF/DEF layout model. +OpenRCX extracts both Resistance and Capacitance for wires, based on coupling distance to the nearest wire and the track density context over and/or under the wire of interest, as well as cell abstracts. The capacitance and resistance measurements are based on equations of coupling distance interpolated on exact measurements from a calibration file, called the Extraction Rules file. The Extraction Rules file (RC technology file) is generated once for every process node and corner, using a provided utility for DEF wire pattern generation and regression modeling. +OpenRCX stores resistance, coupling capacitance, and ground (i.e., grounded) capacitance on OpenDB objects with direct pointers to the associated wire and via db objects. Optionally, OpenRCX can generate a .spef file." +Brief me on the parasitics extraction module?,"The parasitics extraction module in OpenROAD, based on OpenRCX, performs parasitic extraction on routed designs using the LEF/DEF model. It calculates wire resistance and capacitance by considering coupling distance and track density, utilizing a calibration file for accurate measurements. OpenRCX can also produce a .spef file for further analysis." +What is global routing?,"The global routing module in OpenROAD (grt) is based on FastRoute, an open-source global router originally derived from Iowa State University's FastRoute4.1 algorithm. Global routing is responsible for creating routing guides for each net to simplify the job of the detailed router. The purpose of global routing is mainly to avoid overcongestion when creating the guides." +Can you explain global routing and its importance?,"The global routing module in OpenROAD (grt) is based on FastRoute, an open-source global router originally derived from Iowa State University's FastRoute4.1 algorithm. Global routing is responsible for creating routing guides for each net to simplify the job of the detailed router. The purpose of global routing is mainly to avoid overcongestion when creating the guides." +What is global routing?,"OpenROAD's global routing module, built on the FastRoute algorithm, creates routing guides for each net to manage congestion during detailed routing, aiming to prevent overcongestion." +Which environment is required for setting up OpenROAD flow scripts?,You can use the bash shell to run commands and scripts. +What setup is necessary for OpenROAD flow scripts?,You can use the bash shell to run commands and scripts. +Which environment is required for setting up OpenROAD flow scripts?,The bash shell facilitates command and script execution. +What are the ways of installing OpenROAD flow scripts/ ORFS?,"These are the ways of installing OpenROAD flow scripts/ ORFS: Docker, Pre-built Binaries, Windows Subsystem for Linux (WSL), and Local Installation." +What installation methods exist for OpenROAD flow scripts/ORFS?,"These are the ways of installing OpenROAD flow scripts/ ORFS: Docker, Pre-built Binaries, Windows Subsystem for Linux (WSL), and Local Installation." +What are the ways of installing OpenROAD flow scripts/ ORFS?,"OpenROAD flow scripts can be installed via Docker, Pre-built Binaries, WSL, or Local Installation." +What is the basic build command for OpenROAD flow scripts/ ORFS?,The basic basic build command in ORFS is ./build_openroad.sh --help. +What is the fundamental build command for OpenROAD flow scripts/ORFS?,The basic basic build command in ORFS is ./build_openroad.sh --help. +What is the basic build command for OpenROAD flow scripts/ ORFS?,The fundamental ORFS build command is ./build_openroad.sh --help. +What is OpenROAD?,"The OpenROAD (""Foundations and Realization of Open, Accessible Design"") Project was launched in June 2018 within the DARPA IDEA program. OpenROAD aims to bring down the barriers of cost, expertise, and unpredictability that currently block designers' access to hardware implementation in advanced technologies. The project team is developing a fully autonomous, open-source toolchain for digital SoC layout generation, focusing on the RTL-to-GDSII phase of system-on-chip design. Thus, OpenROAD holistically attacks the multiple facets of today's design cost crisis: engineering resources, design tool licenses, project schedule, and risk." +Can you provide an overview of OpenROAD and its functionalities?,"The OpenROAD (""Foundations and Realization of Open, Accessible Design"") Project was launched in June 2018 within the DARPA IDEA program. OpenROAD aims to bring down the barriers of cost, expertise, and unpredictability that currently block designers' access to hardware implementation in advanced technologies. The project team is developing a fully autonomous, open-source toolchain for digital SoC layout generation, focusing on the RTL-to-GDSII phase of system-on-chip design. Thus, OpenROAD holistically attacks the multiple facets of today's design cost crisis: engineering resources, design tool licenses, project schedule, and risk." +What is OpenROAD?,"Launched in June 2018 under DARPA's IDEA program, the OpenROAD (""Foundations and Realization of Open, Accessible Design"") Project aims to democratize access to hardware implementation in cutting-edge technologies by developing a fully autonomous, open-source toolchain for digital SoC layout from RTL-to-GDSII. This initiative addresses the design cost crisis from various angles, including engineering resources, tool licenses, project timelines, and risk." +What is AutoTuner?,"AutoTuner is a ""no-human-in-loop"" parameter tuning framework for commercial and academic RTL-to-GDS flows. AutoTuner provides a generic interface where users can define parameter configuration as JSON objects. This enables AutoTuner to easily support various tools and flows. AutoTuner also utilizes METRICS2.1 to capture PPA of individual search trials. With the abundant features of METRICS2.1, users can explore various reward functions that steer the flow autotuning to different PPA goals." +What is AutoTuner and its purpose in OpenROAD?,"AutoTuner is a ""no-human-in-loop"" parameter tuning framework for commercial and academic RTL-to-GDS flows. AutoTuner provides a generic interface where users can define parameter configuration as JSON objects. This enables AutoTuner to easily support various tools and flows. AutoTuner also utilizes METRICS2.1 to capture PPA of individual search trials. With the abundant features of METRICS2.1, users can explore various reward functions that steer the flow autotuning to different PPA goals." +What is AutoTuner?,"AutoTuner, a ""no-human-in-loop"" framework, facilitates parameter tuning across commercial and academic RTL-to-GDS flows. It employs a generic interface for parameter configurations via JSON objects and leverages METRICS2.1 to evaluate PPA across trials, supporting the exploration of diverse PPA-optimizing reward functions." +WHat are the current supported search algorithms by AutoTuner?,"AutoTuner contains top-level Python script for ORFS, each of which implements a different search algorithm. Current supported search algorithms are as follows: +Random/Grid Search, Population Based Training (PBT), Tree Parzen Estimator (HyperOpt), Bayesian + Multi-Armed Bandit (AxSearch), Tree Parzen Estimator + Covariance Matrix Adaptation Evolution Strategy (Optuna), Evolutionary Algorithm (Nevergrad)" +Which search algorithms are currently supported by AutoTuner?,"AutoTuner contains top-level Python script for ORFS, each of which implements a different search algorithm. Current supported search algorithms are as follows: +Random/Grid Search, Population Based Training (PBT), Tree Parzen Estimator (HyperOpt), Bayesian + Multi-Armed Bandit (AxSearch), Tree Parzen Estimator + Covariance Matrix Adaptation Evolution Strategy (Optuna), Evolutionary Algorithm (Nevergrad)" +WHat are the current supported search algorithms by AutoTuner?,"AutoTuner incorporates a top-level Python script for ORFS, offering various search algorithms like Random/Grid Search, Population Based Training (PBT), Tree Parzen Estimator (HyperOpt), Bayesian + Multi-Armed Bandit (AxSearch), Tree Parzen Estimator + Covariance Matrix Adaptation Evolution Strategy (Optuna), and Evolutionary Algorithm (Nevergrad)." +How to set the direction of tuning in AutoTuner?,"User-defined coefficient values (coeff_perform, coeff_power, coeff_area) of three objectives to set the direction of tuning are written in the script. Each coefficient is expressed as a global variable at the get_ppa function in PPAImprov class in the script (coeff_perform, coeff_power, coeff_area). Efforts to optimize each of the objectives are proportional to the specified coefficients." +How can the tuning direction be set in AutoTuner?,"User-defined coefficient values (coeff_perform, coeff_power, coeff_area) of three objectives to set the direction of tuning are written in the script. Each coefficient is expressed as a global variable at the get_ppa function in PPAImprov class in the script (coeff_perform, coeff_power, coeff_area). Efforts to optimize each of the objectives are proportional to the specified coefficients." +How to set the direction of tuning in AutoTuner?,"In AutoTuner, user-defined coefficient values (coeff_perform, coeff_power, coeff_area) direct the tuning efforts towards optimizing performance, power, and area. These coefficients are globally declared in the PPAImprov class's get_ppa function." +What environment is required for AutoTuner?,"To set up AutoTuner, make sure you have a virtual environment set up with Python 3.9.X. There are plenty of ways to do this, we recommend using Miniconda, which is a free minimal installer for the package manager conda." +What environment is necessary for operating AutoTuner?,"To set up AutoTuner, make sure you have a virtual environment set up with Python 3.9.X. There are plenty of ways to do this, we recommend using Miniconda, which is a free minimal installer for the package manager conda." +What environment is required for AutoTuner?,"To initiate AutoTuner, ensure the setup of a virtual environment using Python 3.9.X, with Miniconda recommended for managing the environment." +Which parameters/variables can be used for tune or sweep?,Any variable that can be set from the command line can be used for tune or sweep. +What parameters or variables can be tuned or swept in AutoTuner?,Any variable that can be set from the command line can be used for tune or sweep. +Which parameters/variables can be used for tune or sweep?,Variables settable via command line can be employed for tuning or sweeping parameters. +How to add verilog designs to ORFS repository for a full RTL-GDS flow execution?,The following design example is based on the design spm that implements a Single-port memory using gf180 platform. This procedure applies to any design for a given platform you choose. Start from the base directory OpenROAD-flow-scripts/flow. Step 1: Create the Verilog source files directory based on the top module name. Step 2: Create config.mk to define design configuration. Step 3: Define key design parameters in config.mk. Step 4: Define SDC constraints. Step 5: Add the design name to Makefile to run the flow with the make command. +How can Verilog designs be added to the ORFS repository for complete RTL-GDSII flow execution?,The following design example is based on the design spm that implements a Single-port memory using gf180 platform. This procedure applies to any design for a given platform you choose. Start from the base directory OpenROAD-flow-scripts/flow. Step 1: Create the Verilog source files directory based on the top module name. Step 2: Create config.mk to define design configuration. Step 3: Define key design parameters in config.mk. Step 4: Define SDC constraints. Step 5: Add the design name to Makefile to run the flow with the make command. +How to add verilog designs to ORFS repository for a full RTL-GDS flow execution?,"Describing a design example for a Single-port memory using the gf180 platform, this process is adaptable to any design. It includes creating a Verilog source directory, configuring design settings in config.mk, defining key parameters, setting SDC constraints, and incorporating the design into the Makefile for execution." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export PLATFORM?","While designing spm that implements a Single-port memory using gf180 platform, the export PLATFORM value can be gf180." +"For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export PLATFORM?","While designing spm that implements a Single-port memory using gf180 platform, the export PLATFORM value can be gf180." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export PLATFORM?","For a Single-port memory design on the gf180 platform, the export PLATFORM variable should be set to gf180." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export DESIGN_NAME?","While designing spm that implements a Single-port memory using gf180 platform, the value of the parameter, export DESIGN_NAME can be spm." +"For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export DESIGN_NAME?","While designing spm that implements a Single-port memory using gf180 platform, the value of the parameter, export DESIGN_NAME can be spm." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export DESIGN_NAME?","When designing a Single-port memory on the gf180 platform, the export DESIGN_NAME should be assigned to spm." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export VERILOG_FILES?","For the value of export VERILOG_FILES parameter while designing spm that implements a Single-port memory using gf180 platform, it can be $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))" +"For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export VERILOG_FILES?","For the value of export VERILOG_FILES parameter while designing spm that implements a Single-port memory using gf180 platform, it can be $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))" +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export VERILOG_FILES?",The export VERILOG_FILES parameter should be set to include all Verilog files under the design nickname directory for a Single-port memory design on the gf180 platform. +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export SDC_FILE?","The parameter, export SDC_FILE can have the value ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc while designing spm that implements a Single-port memory using gf180 platform" +"For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export SDC_FILE?","The parameter, export SDC_FILE can have the value ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc while designing spm that implements a Single-port memory using gf180 platform" +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export SDC_FILE?","While designing a Single-port memory on the gf180 platform, the export SDC_FILE parameter should be set to the constraint file path." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export CORE_UTILIZATION?", The value of CORE_UTILIZATION may be subjective but one value for CORE_UTILIZATION while designing spm that implements a Single-port memory using gf180 platform40 +"For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export CORE_UTILIZATION?", The value of CORE_UTILIZATION may be subjective but one value for CORE_UTILIZATION while designing spm that implements a Single-port memory using gf180 platform40 +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export CORE_UTILIZATION?","The CORE_UTILIZATION value, while subjective, could be set to 40 for a Single-port memory design on the gf180 platform." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export PLACE_DENSITY ","The value of the parameter, export PLACE_DENSITY while designing spm that implements a Single-port memory can be 0.6." +"For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export PLACE_DENSITY?","The value of the parameter, export PLACE_DENSITY while designing spm that implements a Single-port memory can be 0.6." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export PLACE_DENSITY ","For a Single-port memory design, the export PLACE_DENSITY should be set to 0.6." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export TNS_END_PERCENT?","The value of the parameter, export TNS_END_PERCENT while designing spm that implements a Single-port memory can be 100." +"For a Single-port memory design using the gf180 platform, what should be the value for the parameter, export TNS_END_PERCENT?","The value of the parameter, export TNS_END_PERCENT while designing spm that implements a Single-port memory can be 100." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export TNS_END_PERCENT?","In the case of a Single-port memory design, the export TNS_END_PERCENT should be 100." +What is the function of the Environment Variables for the OpenROAD Flow Scripts?,"Environment variables are used in the OpenROAD flow to define various platform, design, and tool-specific variables to allow finer control and user overrides at various flow stages. These are defined in the config.mk file located in the platform and design-specific directories." +How do Environment Variables influence the OpenROAD Flow Scripts?,"Environment variables are used in the OpenROAD flow to define various platform, design, and tool-specific variables to allow finer control and user overrides at various flow stages. These are defined in the config.mk file located in the platform and design-specific directories." +What is the function of the Environment Variables for the OpenROAD Flow Scripts?,"The OpenROAD flow utilizes environment variables defined in the config.mk file to specify various platform, design, and tool-specific settings, offering detailed control and customization at different stages." +"What does the general variables for all stages, SKIP_REPORT_METRICS do?","The SKIP_REPORT_METRICS general variable if set to 1, then metrics, report_metrics does nothing. This is useful to speed up builds." +What is the role of the SKIP_REPORT_METRICS variable in all stages?,"The SKIP_REPORT_METRICS general variable if set to 1, then metrics, report_metrics does nothing. This is useful to speed up builds." +"What does the general variables for all stages, SKIP_REPORT_METRICS do?","If the SKIP_REPORT_METRICS variable is set to 1, metrics and report_metrics are bypassed, which accelerates the build process." +"Can you explain the usage of the Library Setup variable, PROCESS?","The variable, PROCESS signifies a technology node or process in use." +Can you detail the PROCESS variable in Library Setup?,"The variable, PROCESS signifies a technology node or process in use." +"Can you explain the usage of the Library Setup variable, PROCESS?",The PROCESS variable indicates the technology node or process in use. +"What is the function of the Library Setup variable, CORNER?",This CORNER variable specifies the Library to select based on corner BC/TC/WC. +What is the purpose of the CORNER variable in Library Setup?,This CORNER variable specifies the Library to select based on corner BC/TC/WC. +"What is the function of the Library Setup variable, CORNER?",The CORNER variable determines the Library selection based on corner cases like BC/TC/WC. +"What is the description of Library Setup variable, TECH_LEF","This variable, TECH_LEF, stipulates a technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements." +What does the TECH_LEF variable in Library Setup describe?,"This variable, TECH_LEF, stipulates a technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements." +"What is the description of Library Setup variable, TECH_LEF","TECH_LEF defines a technology LEF file from the PDK containing details on metal layers, vias, and spacing requirements." +"What is the description of Library Setup variable, SC_LEF",SC_LEF is used to specify the path to the technology standard cell LEF file. +What does the SC_LEF variable in Library Setup denote?,SC_LEF is used to specify the path to the technology standard cell LEF file. +"What is the description of Library Setup variable, SC_LEF",SC_LEF specifies the path to the technology standard cell LEF file. +"What is the function of the Library Setup variable, GDS_FILES",GDS_FILES specifies the path to platform GDS files. +What is the role of the GDS_FILES variable in Library Setup?,GDS_FILES specifies the path to platform GDS files. +"What is the function of the Library Setup variable, GDS_FILES",GDS_FILES sets the path to platform GDS files. +"What is the description of Library Setup variable, LIB_FILES","LIB_FILES enumerates a Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing, and power definitions for each cell." +What does the LIB_FILES variable in Library Setup specify?,"LIB_FILES enumerates a Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing, and power definitions for each cell." +"What is the description of Library Setup variable, LIB_FILES","LIB_FILES lists a Liberty file for the standard cell library, including PVT characterization, and definitions of input/output characteristics, timing, and power for each cell." +"Can you explain the usage of the Library Setup variable, DONT_USE_CELLS?","In OpenROAD Flow Scripts, the DONT_USE_CELLS variable stores a list of cells to avoid when performing both synthesis and place & route. Basic wildcard patterns (*) are supported. You may want to mark a cell as dont_use for several reasons, including 1) some cells may have complicated pin access patterns which are more likely to cause design rule violations during detailed routing, 2) some cells may be more prone to manufacturing variation, and will cause difficulty to close timing constraints, 3) A designer may not want to use certain cells during the implementation flow." +How is the DONT_USE_CELLS variable used in Library Setup?,"In OpenROAD Flow Scripts, the DONT_USE_CELLS variable stores a list of cells to avoid when performing both synthesis and place & route. Basic wildcard patterns (*) are supported. You may want to mark a cell as dont_use for several reasons, including 1) some cells may have complicated pin access patterns which are more likely to cause design rule violations during detailed routing, 2) some cells may be more prone to manufacturing variation, and will cause difficulty to close timing constraints, 3) A designer may not want to use certain cells during the implementation flow." +"Can you explain the usage of the Library Setup variable, DONT_USE_CELLS?","In OpenROAD Flow Scripts, DONT_USE_CELLS stores cells to avoid during synthesis and place & route, supporting basic wildcard patterns (*), due to reasons like complex pin access, susceptibility to manufacturing variation, or simply preference." +What does restructuring do?,"Restructuring (the rst module) uses logic resynthesis to optimize combinational logic paths. Restructuring can be performed in either area or delay mode. Area mode will optimize the logic cell area of the paths, whereas delay mode will optimize for delay. An Area Mode Example: restructure -liberty_file ckt.lib -target area -tielo_pin ABC -tiehi_pin DEF. For Timing Mode Example: restructure -liberty_file ckt.lib -target delay -tielo_pin ABC -tiehi_pin DEF -slack_threshold 1 -depth_threshold 2." +How does restructuring contribute to design optimization?,"Restructuring (the rst module) uses logic resynthesis to optimize combinational logic paths. Restructuring can be performed in either area or delay mode. Area mode will optimize the logic cell area of the paths, whereas delay mode will optimize for delay. An Area Mode Example: restructure -liberty_file ckt.lib -target area -tielo_pin ABC -tiehi_pin DEF. For Timing Mode Example: restructure -liberty_file ckt.lib -target delay -tielo_pin ABC -tiehi_pin DEF -slack_threshold 1 -depth_threshold 2." +What does restructuring do?,Restructuring optimizes combinational logic paths in area or delay modes. +Is there a way of knowing which instances were modified by resize command ?,"The Resizer module (rsz) can modify the netlist by inserting or removing buffers, as well as increasing or decreasing the drive strength of cells. rsz does not save a log of which instances were modified, because it would create an excessively long log file. A recommended workaround solution would be to save a layout file (such as DEF or ODB) before performing resizing, and then compare it to a layout file after resizing." +Is it possible to identify instances modified by the resize command?,"The Resizer module (rsz) can modify the netlist by inserting or removing buffers, as well as increasing or decreasing the drive strength of cells. rsz does not save a log of which instances were modified, because it would create an excessively long log file. A recommended workaround solution would be to save a layout file (such as DEF or ODB) before performing resizing, and then compare it to a layout file after resizing." +Is there a way of knowing which instances were modified by resize command ?,Resizer modifies the netlist by adjusting buffer sizes and cell drive strengths without detailed modification logs. +How can I improve runtime?,"In OpenROAD, the runtime of the software is directly related to 1) the modeling accuracy and 2) the circuit optimization effort. Improving runtime is usually a tradeoff of one of these two categories. If you are comfortable with reducing optimization effort, such as when performing design space exploration, you could try the following techniques: 1) Relaxing timing constraints in the SDC file, 2) skipping unnesessary optimization routines, such as setup and hold time fixing, 3) Stopping the design flow early, such as after the placement step or clock tree synthesis (CTS) step." +How might I enhance the runtime efficiency of my design?,"In OpenROAD, the runtime of the software is directly related to 1) the modeling accuracy and 2) the circuit optimization effort. Improving runtime is usually a tradeoff of one of these two categories. If you are comfortable with reducing optimization effort, such as when performing design space exploration, you could try the following techniques: 1) Relaxing timing constraints in the SDC file, 2) skipping unnesessary optimization routines, such as setup and hold time fixing, 3) Stopping the design flow early, such as after the placement step or clock tree synthesis (CTS) step." +How can I improve runtime?,"OpenROAD runtime is influenced by modeling accuracy and optimization efforts, with trade-offs for runtime improvement." +Why does my design take so long?,"In OpenROAD, the runtime of the design can be affected by several factors: 1) the size of the netlist. Designs with a large number of instances (100k or more) can take significantly longer than small designs. 2) the physical area of the design. Designs with large die areas (~1 mm^2 or larger) can take longer because of having to store the die size in memory. 3) improper timing constraints. Designs with excessive timing constaints can cause optimization algorithms, particularly Resizer (rsz) to take excessively long. 4) host machine constraints. Large designs can require a large amount of RAM to run. If the required memory exceeds your machine's available memory, the runtime will be significantly increased. Additionally, OpenROAD scales well with core count, so using a CPU with a greater number of cores can improve runtime." +What factors contribute to prolonged design processing times?,"In OpenROAD, the runtime of the design can be affected by several factors: 1) the size of the netlist. Designs with a large number of instances (100k or more) can take significantly longer than small designs. 2) the physical area of the design. Designs with large die areas (~1 mm^2 or larger) can take longer because of having to store the die size in memory. 3) improper timing constraints. Designs with excessive timing constaints can cause optimization algorithms, particularly Resizer (rsz) to take excessively long. 4) host machine constraints. Large designs can require a large amount of RAM to run. If the required memory exceeds your machine's available memory, the runtime will be significantly increased. Additionally, OpenROAD scales well with core count, so using a CPU with a greater number of cores can improve runtime." +Why does my design take so long?,"Netlist size, design area, timing constraints, and machine capabilities affect OpenROAD's runtime." +What is DBU?,"In OpenROAD, database units (DBU) are an integer representation of distance on a chip. In the LEF/DEF format, each technology specifies a conversion factor in terms of DBU/micron. For example, if a technology used a conversion factor of 2000 DBU/micron, that would mean that each DBU represents 0.0005 micron or 0.5 nm. The purpose for using DBU is that it enables faster calculation and no loss of precision compared to floating point representations." +Can you explain the concept of DBU in OpenROAD?,"In OpenROAD, database units (DBU) are an integer representation of distance on a chip. In the LEF/DEF format, each technology specifies a conversion factor in terms of DBU/micron. For example, if a technology used a conversion factor of 2000 DBU/micron, that would mean that each DBU represents 0.0005 micron or 0.5 nm. The purpose for using DBU is that it enables faster calculation and no loss of precision compared to floating point representations." +What is DBU?,"Database units (DBU) represent distance on a chip, converting to microns for precision without floating point errors." +How do I convert from DBU?,"In OpenROAD, an integer DBU value can be converted to a floating point micron value by using the ord::dbu_to_microns function" +How is conversion from DBU performed?,"In OpenROAD, an integer DBU value can be converted to a floating point micron value by using the ord::dbu_to_microns function" +How do I convert from DBU?,DBU values convert to microns using ord::dbu_to_microns function. +How to access GUI,OpenROAD's GUI can be started in two ways. One is to use the -gui flag when invoking OpenROAD from the command line (e.g. openroad -gui). The other option is to use the gui::show function from inside the openroad command interpreter. +How can the GUI be accessed in OpenROAD?,OpenROAD's GUI can be started in two ways. One is to use the -gui flag when invoking OpenROAD from the command line (e.g. openroad -gui). The other option is to use the gui::show function from inside the openroad command interpreter. +How to access GUI,OpenROAD's GUI is accessible via command line flag or internal show function. +Which commands are essential for manipulating design data in OpenROAD?,"OpenROAD is run using Tcl scripts. The following commands are used to read and write design data. +read_lef [-tech] [-library] filename +read_def filename +write_def [-version 5.8|5.7|5.6|5.5|5.4|5.3] filename +read_verilog filename +write_verilog filename +read_db filename +write_db filename +write_abstract_lef filename" +"What do these Debug output mean? +[INFO MPL-0024] [Multilevel Autoclustering] Creating clustered netlist. +[INFO MPL-0039] [Coarse Shaping] Determining shape functions for clusters. +[INFO MPL-0028] [Hierarchical Macro Placement] Placing clusters and macros. +[INFO MPL-0037] Updated location of 95 macros +Delete buffers for RTLMP flow... +[INFO RSZ-0026] Removed 0 buffers.","Messages with the MPL prefix are from the macro placement (mpl) module. These messages are progress messages, informing the user which step of the HierRTLMP flow is being executed." \ No newline at end of file diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/General/General.xlsx b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/General/General.xlsx new file mode 100644 index 0000000..d7227cf Binary files /dev/null and b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/General/General.xlsx differ diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/README.md b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/README.md new file mode 100644 index 0000000..823a3cf --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/README.md @@ -0,0 +1,7 @@ +### This is the Question-Answer format Large Language Model EDA Dataset for OpenROAD + +This dataset has been divided into 3 categories: + +1. **OR General** +2. **OR Tools** +3. **OR Flow** diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/Tools/Tools.csv b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/Tools/Tools.csv new file mode 100644 index 0000000..9ce9e17 --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/Tools/Tools.csv @@ -0,0 +1,189 @@ +Prompts,Answers +What does the -switch_cell argument in PDN do while doing power switch insertion?,"During power switch insertion, the -switch_cell argument is used to specify the name of a coarse-grain power switch cell that is to be inserted wherever the standard cell rail connects to the rest of the power grid. The mesh layers are associated with the unswitched power net of the voltage domain, whereas the standard cell rail is associated with the switched power net of the voltage domain. The placement of a power switch cell connects the unswitched power mesh to the switched power rail through a power switch defined by the define_power_switch_cell command." +How does the -switch_cell argument function in PDNGEN during power switch integration?,"During power switch insertion, the -switch_cell argument is used to specify the name of a coarse-grain power switch cell that is to be inserted wherever the standard cell rail connects to the rest of the power grid. The mesh layers are associated with the unswitched power net of the voltage domain, whereas the standard cell rail is associated with the switched power net of the voltage domain. The placement of a power switch cell connects the unswitched power mesh to the switched power rail through a power switch defined by the define_power_switch_cell command." +What does the -switch_cell argument in PDN do while doing power switch insertion?,"For inserting power switches, the -switch_cell parameter is utilized to denote a coarse-grain power switch cell's name for insertion at points where the standard cell rail merges with the broader power grid. The mesh layers correspond with the voltage domain's unswitched power net, and the standard cell rail links to the switched power net. Inserting a power switch cell bridges the unswitched power mesh and the switched power rail, facilitated by the define_power_switch_cell command." +What does the par module do?,"The partitioning module (par) is based on TritonPart, an open-source constraints-driven partitioner. par can be used to partition a hypergraph or a gate-level netlist. TritonPart solves multi-way partitioning by 1) constraints-driven coarsening, 2) initial partitioning, 3) refinement, 4) cut-overlay clustering and partitioning (COCP), and 5) V-cycle refinement. The purpose of partitioning a netlist is to reduce the complexity of a circuit so that algorithms can operate on smaller chunks of the netlist at a time. Partitioning a netlist may slightly reduce the optimization opportunities compared to a non-partitioned approach, but it greatly benefits the runtime. Partitioning a netlist may be the only option to feasibly operate on very large circuits." +What functionality does the par module provide?,"The partitioning module (par) is based on TritonPart, an open-source constraints-driven partitioner. par can be used to partition a hypergraph or a gate-level netlist. TritonPart solves multi-way partitioning by 1) constraints-driven coarsening, 2) initial partitioning, 3) refinement, 4) cut-overlay clustering and partitioning (COCP), and 5) V-cycle refinement. The purpose of partitioning a netlist is to reduce the complexity of a circuit so that algorithms can operate on smaller chunks of the netlist at a time. Partitioning a netlist may slightly reduce the optimization opportunities compared to a non-partitioned approach, but it greatly benefits the runtime. Partitioning a netlist may be the only option to feasibly operate on very large circuits." +What does the par module do?,"The partitioning tool, par, leverages TritonPart, a freely available constraint-based partitioning software. It enables the partitioning of hypergraphs or gate-level netlists through a process involving constraint-led coarsening, initial partitioning, refinement, cut-overlay clustering and partitioning (COCP), and V-cycle refinement. The main goal is to simplify the circuit's complexity, allowing algorithms to manage smaller sections of the netlist efficiently. Though partitioning may slightly limit optimization chances, it significantly enhances runtime and is often the sole strategy for managing vast circuits." +Is TritonRoute the foundation of drt?,"The Detailed Routing (drt) module in OpenROAD is based on the open-source detailed router TritonRoute. TritonRoute consists of several main building blocks, including pin access analysis, track assignment, initial detailed routing, search and repair, and a DRC engine. The initial development of the router is inspired by the ISPD-2018 initial detailed routing contest. However, the current drt framework differs and is built from scratch, aiming for an industrial-oriented, scalable, and flexible flow." +Does TritonRoute serve as the underlying technology for drt?,"The Detailed Routing (drt) module in OpenROAD is based on the open-source detailed router TritonRoute. TritonRoute consists of several main building blocks, including pin access analysis, track assignment, initial detailed routing, search and repair, and a DRC engine. The initial development of the router is inspired by the ISPD-2018 initial detailed routing contest. However, the current drt framework differs and is built from scratch, aiming for an industrial-oriented, scalable, and flexible flow." +Is TritonRoute the foundation of drt?,"The Detailed Routing (drt) module of OpenROAD, founded on the open-source detailed router TritonRoute, incorporates key components like pin access analysis, track assignment, initial routing, search and repair, and a DRC (Design Rule Checking) engine. Initially inspired by the ISPD-2018 detailed routing challenge, the current drt architecture is entirely new, designed for industrial-grade scalability and flexibility." +"What do these Debug output mean? +[INFO MPL-0024] [Multilevel Autoclustering] Creating clustered netlist. +[INFO MPL-0039] [Coarse Shaping] Determining shape functions for clusters. +[INFO MPL-0028] [Hierarchical Macro Placement] Placing clusters and macros. +[INFO MPL-0037] Updated location of 95 macros +Delete buffers for RTLMP flow... +[INFO RSZ-0026] Removed 0 buffers.","Messages with the MPL prefix are from the macro placement (mpl) module. These messages are progress messages, informing the user which step of the HierRTLMP flow is being executed." +What are the units of the -pad_right and -pad_left arguments of the global_placement function,"In global_placement, -pad_right and -pad_left add padding which is measured in cell sites to effectively make the cell appear wider. pad_left adds a pad to the left side, pad_right adds it to the right side. Wider cells during global placement can help reduce placement congestion and make finding a valid placement easier." +What are the measurement units for the -pad_right and -pad_left arguments in the global_placement function?,"In global_placement, -pad_right and -pad_left add padding which is measured in cell sites to effectively make the cell appear wider. pad_left adds a pad to the left side, pad_right adds it to the right side. Wider cells during global placement can help reduce placement congestion and make finding a valid placement easier." +What are the units of the -pad_right and -pad_left arguments of the global_placement function,"In the global placement process, the options -pad_right and -pad_left introduce padding in terms of cell sites, effectively broadening the cell. This padding on either side aids in alleviating placement congestion and facilitates easier placement validation." +Does space padding influence the design utilization? I feel like it shouldn't.,"Cell padding only impacts the way the global placer (gpl) and detailed placer (dpl) sees the cells. Cell padding does not change the logic area of the cell from the user perspective. If you were to use the report_design_area command, you would see the unpadded design utilization reported." +"Does padding affect design utilization, in your opinion?","Cell padding only impacts the way the global placer (gpl) and detailed placer (dpl) sees the cells. Cell padding does not change the logic area of the cell from the user perspective. If you were to use the report_design_area command, you would see the unpadded design utilization reported." +Does space padding influence the design utilization? I feel like it shouldn't.,"Padding adjustments affect only how global and detailed placers view the cells, leaving the cell's logical area as perceived by the user unchanged. Utilizing the report_design_area command will display the design's utilization without the padding." +"Wouldn't manually adding pads in the global_placement function reduce the maximum design utilization possible for a design? Especially since OpenROAD wants to be automatic, GPL will stop everything if it sees a DU >100% even if it could achieve a reasonable DU with equivalent padding","Cell padding can reduce the maximum possible design utilization. If you don't want padding in your design, you can reduce the default padding or turn it off. However, padding is usually necessary to achieve a cleanly routed design, because cells which are too close together may make routing impossible. If you want to optimize for very high-density designs, I believe you can also set padding on a master-by-master basis so that only the most difficult cells are padded. This process may take some trial and error." +Could manually adding pads in the global_placement function affect the maximum design utilization?,"Cell padding can reduce the maximum possible design utilization. If you don't want padding in your design, you can reduce the default padding or turn it off. However, padding is usually necessary to achieve a cleanly routed design, because cells which are too close together may make routing impossible. If you want to optimize for very high-density designs, I believe you can also set padding on a master-by-master basis so that only the most difficult cells are padded. This process may take some trial and error." +"Wouldn't manually adding pads in the global_placement function reduce the maximum design utilization possible for a design? Especially since OpenROAD wants to be automatic, GPL will stop everything if it sees a DU >100% even if it could achieve a reasonable DU with equivalent padding","Implementing cell padding may limit the maximum design utilization achievable. Adjusting or disabling default padding is an option, though padding is often crucial for achieving a neatly routed design by preventing overly congested cell placements. For high-density design optimization, padding can be selectively applied to particularly challenging cells, requiring some experimentation." +Why did I encounter an issue with CORE_UTILIZATION when trying to aim for a DU of 70% on the ASAP7 PDK which should be possible and reasonable for any design?,"If you are using ORFS, the CORE_UTILIZATION variable only determines the core utilization after Yosys (synthesis) runs using the netlist data. The utilization can change dramatically as OpenROAD performs timing optimization, which will insert buffers, remove buffers, and resize cells. For example, if you set CORE_UTILIZATION to 70% utilization during the initialization step, you may end up with 90%+ utilization because of optimization to meet timing constraints. It is currently up to the designer to ensure that the CORE_UTILIZATION is set appropriately, which may require some trial and error." +Why did I face a CORE_UTILIZATION issue when targeting a DU of 70% with the ASAP7 PDK?,"If you are using ORFS, the CORE_UTILIZATION variable only determines the core utilization after Yosys (synthesis) runs using the netlist data. The utilization can change dramatically as OpenROAD performs timing optimization, which will insert buffers, remove buffers, and resize cells. For example, if you set CORE_UTILIZATION to 70% utilization during the initialization step, you may end up with 90%+ utilization because of optimization to meet timing constraints. It is currently up to the designer to ensure that the CORE_UTILIZATION is set appropriately, which may require some trial and error." +Why did I encounter an issue with CORE_UTILIZATION when trying to aim for a DU of 70% on the ASAP7 PDK which should be possible and reasonable for any design?,"With ORFS, the CORE_UTILIZATION variable reflects core utilization post-Yosys synthesis, based on netlist data. Subsequent timing optimization in OpenROAD, which includes buffer insertion, deletion, and cell resizing, can significantly alter utilization levels. Designers must judiciously set CORE_UTILIZATION, anticipating possible adjustments through trial and error." +"If I have a design for which the detailed placement fails for a few instances, if I relax my timing constraints will it result in a successful placement?","Relaxing timing constraints can usually reduce your design utilization because fewer buffers will need to be inserted. However, detailed placement can fail for several reasons, including 1) setting core utilization too high, 2) not having enough cell padding during global placement, 3) having too much cell padding during detailed placement, 4) having a poor macro placement which will block placement of some standard cells" +"If detailed placement fails for certain instances in my design, would loosening timing constraints help achieve placement?","Relaxing timing constraints can usually reduce your design utilization because fewer buffers will need to be inserted. However, detailed placement can fail for several reasons, including 1) setting core utilization too high, 2) not having enough cell padding during global placement, 3) having too much cell padding during detailed placement, 4) having a poor macro placement which will block placement of some standard cells" +"If I have a design for which the detailed placement fails for a few instances, if I relax my timing constraints will it result in a successful placement?","Easing timing constraints can lead to lower design utilization by reducing the need for buffer insertion. However, detailed placement might fail due to reasons like excessive core utilization, insufficient global placement padding, excessive detailed placement padding, or suboptimal macro placement impeding standard cell placement." +"The timing optimizations done by the synthesis tool are ""discarded"" as the buffers are removed?","Empiracally, the OpenROAD team has found that OpenROAD optimizes better when the buffers from Yosys are removed, because Yosys does not do physical synthesis." +Are the timing adjustments made by the synthesis tool lost when buffers are eliminated?,"Empiracally, the OpenROAD team has found that OpenROAD optimizes better when the buffers from Yosys are removed, because Yosys does not do physical synthesis." +"The timing optimizations done by the synthesis tool are ""discarded"" as the buffers are removed?","The OpenROAD team has empirically observed that removing Yosys-inserted buffers leads to better optimization outcomes, as Yosys lacks physical synthesis capabilities." +Is there no need to re-synthesize with different timing constraints with Yosys? Or does it also use different/bigger non-buffer cells that also need to be resized?,"Empirically, applying timing constraints to Yosys for synthesis does not have much impact on the output netlist. However, the results may not be identical if the timing constraints are changed." +"Is re-synthesizing with altered timing constraints unnecessary with Yosys, or does it also resize non-buffer cells?","Empirically, applying timing constraints to Yosys for synthesis does not have much impact on the output netlist. However, the results may not be identical if the timing constraints are changed." +Is there no need to re-synthesize with different timing constraints with Yosys? Or does it also use different/bigger non-buffer cells that also need to be resized?,"Applying timing constraints during Yosys synthesis shows limited influence on the netlist outcome, with possible variations if timing constraints are altered." +"What does this warning mean? +[WARNING ODB-0208] VIA: duplicate VIA (via5_6_120_288_1_2_58_322) ignored...","This warning likely occurs because of multiple block abstracts with the same via. To fix this problem, one should ensure that the block abstracts do not have duplicates via definitions." +"Upon attempting to read an invalid ODB file, OpenROAD doesn't attempt to validate it and instead crashes with a cryptic message of Error: read_db.tcl, 1 ios_base::clear: unspecified iostream_category error. Why is this happening?","I would advise against using low-level OBD APIs to interact with OpenROAD. User-facing APIs in OpenROAD have documentation and error checking to prevent improper usage, however low-level APIs may not have error checking for performance reasons. In this case, it appears the db you are creating does not have a logger and can't issue any messages." +Why does OpenROAD crash without attempting to validate an invalid ODB file?,"I would advise against using low-level OBD APIs to interact with OpenROAD. User-facing APIs in OpenROAD have documentation and error checking to prevent improper usage, however low-level APIs may not have error checking for performance reasons. In this case, it appears the db you are creating does not have a logger and can't issue any messages." +"Upon attempting to read an invalid ODB file, OpenROAD doesn't attempt to validate it and instead crashes with a cryptic message of Error: read_db.tcl, 1 ios_base::clear: unspecified iostream_category error. Why is this happening?","I recommend against using the low-level OBD APIs in OpenROAD since user-friendly APIs offer documentation and error checking to prevent misuse, unlike low-level APIs that might lack error checks for efficiency. In your situation, the database being created lacks a logger, preventing message issuance." +What is IR Drop Analysis?,"The IR Drop Analysis module in OpenROAD (psm) is based on PDNSim, an open-source static IR analyzer. PDNSim will perform a simulation based on the estimated current draw of each instance to estimate what is the voltage drop seen at each cell. That is, it shows the voltage drop between the voltage source(s) of the chip and each instance." +Can you explain IR Drop Analysis and its purposes?,"The IR Drop Analysis module in OpenROAD (psm) is based on PDNSim, an open-source static IR analyzer. PDNSim will perform a simulation based on the estimated current draw of each instance to estimate what is the voltage drop seen at each cell. That is, it shows the voltage drop between the voltage source(s) of the chip and each instance." +What is IR Drop Analysis?,"The IR Drop Analysis module in OpenROAD, based on PDNSim, performs simulations to estimate the voltage drop across each cell by analyzing the current draw of each instance, illustrating the drop from the chip's voltage source(s) to each instance." +What are the features of IR Drop analysis?,"The features of IR Drope analysis are: reporting the worst IR drop, reporting the worst current density over all nodes and wire segments in the power distribution network (given a placed and PDN-synthesized design), checking for floating PDN stripes on the power and ground nets, and spice netlist writer for power distribution network wire segments." +What characteristics define IR Drop analysis?,"The features of IR Drope analysis are: reporting the worst IR drop, reporting the worst current density over all nodes and wire segments in the power distribution network (given a placed and PDN-synthesized design), checking for floating PDN stripes on the power and ground nets, and spice netlist writer for power distribution network wire segments." +What are the features of IR Drop analysis?,"IR Drop analysis features include identifying the most severe IR drop and current density across all nodes and wire segments of the power distribution network, detecting floating PDN stripes on power and ground nets, and generating spice netlists for PDN wire segments." +What is Flute3?,Flute3 is an open-source rectilinear Steiner minimum tree heuristic with improvements made by UFRGS students and James Cherry. This tool is used for the calculation of wirelength in grt and rsz. +What distinguishes Flute3?,Flute3 is an open-source rectilinear Steiner minimum tree heuristic with improvements made by UFRGS students and James Cherry. This tool is used for the calculation of wirelength in grt and rsz. +What is Flute3?,"Flute3, enhanced by UFRGS students and James Cherry, is an open-source heuristic for calculating the rectilinear Steiner minimum tree, crucial for estimating wirelength in tools like grt and rsz." +What does the global_connect command do?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The global_connect command is used to define logical connections between supply pins on design instances and their respective supply nets. Note that the global_connect command only creates a logical connection; it does not perform any routing for a physical connection. +What function does the global_connect command serve?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The global_connect command is used to define logical connections between supply pins on design instances and their respective supply nets. Note that the global_connect command only creates a logical connection; it does not perform any routing for a physical connection. +What does the global_connect command do?,"Global connections are designated for linking supply nets to cell supply pins without establishing physical routes, instead creating logical connections that are made using the global_connect command." +What does the clear_global_connect command do?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The clear_global_connect command is used to clear previously declared connections between supply pins on design instances and their respective supply nets. Note that the clear_global_connect command only clears the logical connections; it does not remove any routing or physical connections. +What is the effect of using the clear_global_connect command?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The clear_global_connect command is used to clear previously declared connections between supply pins on design instances and their respective supply nets. Note that the clear_global_connect command only clears the logical connections; it does not remove any routing or physical connections. +What does the clear_global_connect command do?,The clear_global_connect command removes logical connections between supply pins and their nets without affecting any physical routing or connections. +What does the report_global_connect command do?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The report_global_connect command is used to print out the currently defined global connection rules. +What information does the report_global_connect command provide?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The report_global_connect command is used to print out the currently defined global connection rules. +What does the report_global_connect command do?,"Global connections typically link supply nets to cell supply pins, and the report_global_connect command prints the existing global connection rules." +What does the report_cell_usage command do?,The report_cell_usage command is used to print out the number of instances of each type of cell (master) used in the design. +How does the report_cell_usage command assist users?,The report_cell_usage command is used to print out the number of instances of each type of cell (master) used in the design. +What does the report_cell_usage command do?,The report_cell_usage command displays the count of each cell type used within the design. +Is SystemVerilog support limited to the constructs that Yosys supports?,The OpenROAD Flow is limited to the RTL language support that the Yosys synthesizer provides. Yosys currently provides support for a limited subset of SystemVerilog and full support for Verilog. OpenROAD only supports structural Verilog netlists. +Are there limitations to SystemVerilog support based on Yosys compatibility?,The OpenROAD Flow is limited to the RTL language support that the Yosys synthesizer provides. Yosys currently provides support for a limited subset of SystemVerilog and full support for Verilog. OpenROAD only supports structural Verilog netlists. +Is SystemVerilog support limited to the constructs that Yosys supports?,"OpenROAD's RTL language support is contingent on Yosys synthesizer's capabilities, with full support for Verilog and partial support for SystemVerilog." +What is the job of Pin Placer?,"Place pins on the boundary of the die on the track grid to minimize net wirelengths. Pin placement also creates a metal shape for each pin using min-area rules. For designs with unplaced cells, the net wirelength is computed considering the center of the die area as the unplaced cells' position." +What is the function of the Pin Placer tool?,"Place pins on the boundary of the die on the track grid to minimize net wirelengths. Pin placement also creates a metal shape for each pin using min-area rules. For designs with unplaced cells, the net wirelength is computed considering the center of the die area as the unplaced cells' position." +What is the job of Pin Placer?,"For minimized net wirelengths, place pins on the die's boundary on the track grid, creating metal shapes for each pin according to min-area rules and considering the die center as the position for unplaced cells." +What is RePlAce in OpenROAD?,"RePlAce is a tool for advancing solution quality and routability validation in Global Placement. Its features are analytic and nonlinear placement algorithms. it solves electrostatic force equations using Nesterov's method, verified with various commercial technologies and research enablements using OpenDB, verified deterministic solution generation with various compilers and OS, and supports Mixed-size placement mode." +What is RePlAce and its function in OpenROAD?,"RePlAce is a tool for advancing solution quality and routability validation in Global Placement. Its features are analytic and nonlinear placement algorithms. it solves electrostatic force equations using Nesterov's method, verified with various commercial technologies and research enablements using OpenDB, verified deterministic solution generation with various compilers and OS, and supports Mixed-size placement mode." +What is RePlAce in OpenROAD?,"RePlAce advances global placement solution quality and routability with analytic and nonlinear algorithms, solving electrostatic force equations and ensuring deterministic solutions across various technologies." +What is Hierarchical Macro Placement/ Hier-RTLMP?,"""Hier-RTLMP"" is defined as a hierarchical automatic macro placer for large-scale complex IP blocks. This tool builds on the existing RTLMP (mpl) framework, adopting a multilevel physical planning approach that exploits the hierarchy and data flow inherent in the design RTL." +How is Hierarchical Macro Placement defined within OpenROAD?,"""Hier-RTLMP"" is defined as a hierarchical automatic macro placer for large-scale complex IP blocks. This tool builds on the existing RTLMP (mpl) framework, adopting a multilevel physical planning approach that exploits the hierarchy and data flow inherent in the design RTL." +What is Hierarchical Macro Placement/ Hier-RTLMP?,"Hier-RTLMP, building on the RTLMP framework, is a hierarchical macro placer leveraging design RTL's inherent hierarchy and data flow for complex IP blocks." +What file formats are supported by Parallax Static Timing Analyzer or OpenSTA?,"The Following standard file formats are supported by Parallax Static Timing Analyzer or OpenSTA: Verilog netlist, Liberty library, SDC timing constraints,SDF delay annotation, and SPEF parasitics." +Which file formats does Parallax Static Timing Analyzer accept?,"The Following standard file formats are supported by Parallax Static Timing Analyzer or OpenSTA: Verilog netlist, Liberty library, SDC timing constraints,SDF delay annotation, and SPEF parasitics." +What file formats are supported by Parallax Static Timing Analyzer or OpenSTA?,"OpenSTA supports Verilog netlist, Liberty library, SDC timing constraints, SDF delay annotation, and SPEF parasitics for timing verification." +"`auto_place_pins pin_layer` places pins on a single layer but It should be able to place vertical pins (sides of the die) and horizontal pins (top and bottom of the die) in separate layers, why is it not able to do this?","I currently recommend using `io_placer` instead of `auto_place_pins`. Here's an example:```io_placer -hor_layer 3 -ver_layer 2```Note that `io_placer` uses cell placement information to guide the I/O pin placement. If placement has not yet been run, the `-random` flag is required, which will distribute the pins evenly over the die boundary." +Why can't auto_place_pins pin_layer place pins on separate layers for vertical and horizontal orientations?,"I currently recommend using `io_placer` instead of `auto_place_pins`. Here's an example:```io_placer -hor_layer 3 -ver_layer 2```Note that `io_placer` uses cell placement information to guide the I/O pin placement. If placement has not yet been run, the `-random` flag is required, which will distribute the pins evenly over the die boundary." +"`auto_place_pins pin_layer` places pins on a single layer but It should be able to place vertical pins (sides of the die) and horizontal pins (top and bottom of the die) in separate layers, why is it not able to do this?","For pin placement, io_placer is recommended over auto_place_pins, using layer specifications for guided I/O pin placement or the -random flag for preliminary placement before cell placement." +Tell me about the parts of DFT insertion?,"A simple DFT insertion consists of the following parts: a scan_in pin where the test patterns are shifted in, a scan_out pin where the test patterns are read from, scan cells that replace flops with registers that allow for testing, one or more scan chains (shift registers created from your scan cells), a scan_enable pin to allow your design to enter and leave the test mode." +Could you describe the components involved in DFT insertion?,"A simple DFT insertion consists of the following parts: a scan_in pin where the test patterns are shifted in, a scan_out pin where the test patterns are read from, scan cells that replace flops with registers that allow for testing, one or more scan chains (shift registers created from your scan cells), a scan_enable pin to allow your design to enter and leave the test mode." +Tell me about the parts of DFT insertion?,"DFT insertion typically involves a scan_in pin for inputting test patterns, a scan_out pin for outputting test patterns, scan cells that are substituted for flops, one or more scan chains forming shift registers, and a scan_enable pin for toggling test mode on and off." +What is Metal fill?,"Metal filling is a common process in integrated circuit design to enhance manufacturability and yield by making the density of metal shapes more uniform across the design. In OpenROAD, the Finale module (fin) inserts floating metal fill shapes to meet metal density design rules while obeying DRC constraints. The rules for generating metal fill shapes are driven by a JSON configuration file, and the schema can be found in the OpenROAD documentation." +What is the purpose of Metal fill in OpenROAD?,"Metal filling is a common process in integrated circuit design to enhance manufacturability and yield by making the density of metal shapes more uniform across the design. In OpenROAD, the Finale module (fin) inserts floating metal fill shapes to meet metal density design rules while obeying DRC constraints. The rules for generating metal fill shapes are driven by a JSON configuration file, and the schema can be found in the OpenROAD documentation." +What is Metal fill?,"Metal filling, used to improve manufacturability and yield in IC design by standardizing metal shape density, is implemented in OpenROAD's Finale module. It places non-connecting metal fill shapes in accordance with metal density rules and Design Rule Checking (DRC) constraints, guided by a JSON configuration file detailed in the OpenROAD documentation." +What are the Gate Resizer commands?,The resizer commands stop when the design area is -max_utilization util percent of the core area. util is between 0 and 100. The resizer stops and reports an error if the maximum utilization is exceeded. +What are the functionalities of the Gate Resizer commands?,The resizer commands stop when the design area is -max_utilization util percent of the core area. util is between 0 and 100. The resizer stops and reports an error if the maximum utilization is exceeded. +What are the Gate Resizer commands?,"The resizer tool halts if the design exceeds -max_utilization percent of the core area's utilization, throwing an error if the limit is surpassed." +What is macro placement?,"The macro placement module in OpenROAD (mpl) is based on TritonMacroPlacer, an open-source ParquetFP-based macro cell placer. The macro placer places macros/blocks honoring halos, channels, and cell row ""snapping"". Run global_placement before macro placement." +What is macro placement and its significance in OpenROAD?,"The macro placement module in OpenROAD (mpl) is based on TritonMacroPlacer, an open-source ParquetFP-based macro cell placer. The macro placer places macros/blocks honoring halos, channels, and cell row ""snapping"". Run global_placement before macro placement." +What is macro placement?,"The macro placement module in OpenROAD, built on TritonMacroPlacer, places macros/blocks while respecting design constraints like halos, channels, and cell row alignment. It's recommended to run global_placement prior to macro placement." +Elaborate on FastRoute?,"FastRoute is a global routing tool for VLSI back-end design. It is based on sequential rip-up and re-route (RRR) and a lot of novel techniques. FastRoute 1.0 first uses FLUTE to construct congestion-driven Steiner trees, which will later undergo the edge-shifting process to optimize tree structure to reduce congestion. It then uses pattern routing and maze routing with a logistic function-based cost function to solve the congestion problem. FastRoute 2.0 proposed monotonic routing and multi-source multi-sink maze routing techniques to enhance the capability to reduce congestion. FastRoute 3.0 introduced the virtual capacity technique to adaptively change the capacity associated with each global edge to divert wire usage from highly congested regions to less congested regions. FastRoute 4.0 proposed via-aware Steiner tree, 3-bend routing, and a delicate layer assignment algorithm to effectively reduce via count while maintaining outstanding congestion reduction capability. FastRoute 4.1 simplifies the way the virtual capacities are updated and applies a single set of tuning parameters to all benchmark circuits" +How does FastRoute enhance routing processes?,"FastRoute is a global routing tool for VLSI back-end design. It is based on sequential rip-up and re-route (RRR) and a lot of novel techniques. FastRoute 1.0 first uses FLUTE to construct congestion-driven Steiner trees, which will later undergo the edge-shifting process to optimize tree structure to reduce congestion. It then uses pattern routing and maze routing with a logistic function-based cost function to solve the congestion problem. FastRoute 2.0 proposed monotonic routing and multi-source multi-sink maze routing techniques to enhance the capability to reduce congestion. FastRoute 3.0 introduced the virtual capacity technique to adaptively change the capacity associated with each global edge to divert wire usage from highly congested regions to less congested regions. FastRoute 4.0 proposed via-aware Steiner tree, 3-bend routing, and a delicate layer assignment algorithm to effectively reduce via count while maintaining outstanding congestion reduction capability. FastRoute 4.1 simplifies the way the virtual capacities are updated and applies a single set of tuning parameters to all benchmark circuits" +Elaborate on FastRoute?,"FastRoute utilizes a series of innovative techniques for global routing, including FLUTE for constructing congestion-driven Steiner trees, edge-shifting, pattern routing, and maze routing to address congestion, with further enhancements in subsequent versions to reduce congestion and via count effectively." +"Is there any way I can use just the RTL-MP2 stand-alone on either an RTL design or a gate netlist? The issue is, that we use proprietary tools so do not have an OpenDB database for our designs.","OpenROAD supports interoperability with other EDA tools through the industry standard Verilog, LEF, and DEF formats. In this case, you can import a DEF file into OpenROAD from an external tool, run RTL-MP2, and then export the DEF file. The DEF file format should be supported by nearly all EDA physical design tools." +Is it possible to use RTL-MP2 standalone for RTL designs or gate netlists without an OpenDB database?,"OpenROAD supports interoperability with other EDA tools through the industry standard Verilog, LEF, and DEF formats. In this case, you can import a DEF file into OpenROAD from an external tool, run RTL-MP2, and then export the DEF file. The DEF file format should be supported by nearly all EDA physical design tools." +"Is there any way I can use just the RTL-MP2 stand-alone on either an RTL design or a gate netlist? The issue is, that we use proprietary tools so do not have an OpenDB database for our designs.","OpenROAD facilitates interoperability with other EDA tools through standard formats like Verilog, LEF, and DEF, allowing for seamless DEF file imports and exports to and from external tools." +How do I check DRC?,"In OpenROAD, you can use the check_drc command to run the design rule check (DRC). It should be noted that check_drc is not a general-purpose checker and only verifies signal routing according to routing rules from the technology LEF file. check_drc also requires routing guides in order to run, so global routing must be performed first. DRC is also commonly performed by an external tool which will check all layers, not just the metal routing layers." +How do I perform a DRC check in OpenROAD?,"In OpenROAD, you can use the check_drc command to run the design rule check (DRC). It should be noted that check_drc is not a general-purpose checker and only verifies signal routing according to routing rules from the technology LEF file. check_drc also requires routing guides in order to run, so global routing must be performed first. DRC is also commonly performed by an external tool which will check all layers, not just the metal routing layers." +How do I check DRC?,"The check_drc command in OpenROAD performs design rule checks based on routing rules from the technology LEF file, requiring prior global routing and typically supplemented by external tools for comprehensive DRC across all layers." +What does the argument -floorplan_initialize do in read_def?,"When using the read_def command with the -floorplan_initialize argument, OpenROAD will read only physical placement information such as pin locations and instance locations. It does not read or redefine the netlist." +What does the -floorplan_initialize argument achieve in read_def?,"When using the read_def command with the -floorplan_initialize argument, OpenROAD will read only physical placement information such as pin locations and instance locations. It does not read or redefine the netlist." +What does the argument -floorplan_initialize do in read_def?,"Using the read_def command with -floorplan_initialize in OpenROAD loads only the physical placement data, excluding netlist alterations." +What does the argument -skip_pin_swap & -skip_gate_cloning do in repair_timing?,"These flags disable optimizations in case of trouble or unexpected results. They are mainly included as a failsafe for users, rather than something that is expected to be used." +What are the functions of -skip_pin_swap & -skip_gate_cloning in repair_timing?,"These flags disable optimizations in case of trouble or unexpected results. They are mainly included as a failsafe for users, rather than something that is expected to be used." +What does the argument -skip_pin_swap & -skip_gate_cloning do in repair_timing?,"Certain flags in OpenROAD disable optimizations as a safeguard against unexpected outcomes, intended as a last resort for troubleshooting." +What does the detailed_placement command do in OpenROAD?,"The detailed_placement command moves instances to legal locations after global placement. While the global placer (gpl) may place cells in a roughly optimal position, gpl may not place the cells in legal locations because they may not be aligned to cell rows or sites. The detailed placer (dpl) will legalize the cell by shifting it to a nearby location which is aligned to the cell site grid. The detailed_placement command only performs basic legalization and does not attempt to optimize placement. The optimize_mirroring and improve_placement commands will perform optimization on the legalized cells." +What is the purpose of the detailed_placement command?,"The detailed_placement command moves instances to legal locations after global placement. While the global placer (gpl) may place cells in a roughly optimal position, gpl may not place the cells in legal locations because they may not be aligned to cell rows or sites. The detailed placer (dpl) will legalize the cell by shifting it to a nearby location which is aligned to the cell site grid. The detailed_placement command only performs basic legalization and does not attempt to optimize placement. The optimize_mirroring and improve_placement commands will perform optimization on the legalized cells." +What does the detailed_placement command do in OpenROAD?,"The detailed_placement command in OpenROAD repositions instances to legal sites post-global placement, focusing on basic legalization without attempting placement optimization, which is handled by subsequent commands." +"What does the argument -max_displacement disp|{disp_x disp_y} do in detailed_placement +Command?","Max distance that an instance can be moved (in microns) when finding a site where it can be placed. Either set one value for both directions or set {disp_x disp_y} for individual directions. The default values are {0, 0}, and the allowed values within are integers [0, MAX_INT]. This argument is useful because it limits the amount of searching and therefore amount of runtime that the detailed placer can use." +How does the -max_displacement argument affect the detailed_placement command?,"Max distance that an instance can be moved (in microns) when finding a site where it can be placed. Either set one value for both directions or set {disp_x disp_y} for individual directions. The default values are {0, 0}, and the allowed values within are integers [0, MAX_INT]. This argument is useful because it limits the amount of searching and therefore amount of runtime that the detailed placer can use." +"What does the argument -max_displacement disp|{disp_x disp_y} do in detailed_placement +Command?","Specifies the maximum distance instances can be relocated during detailed placement, with default settings at {0, 0} and customizable values for x and y directions to limit search scope and runtime." +What does the argument -disallow_one_site_gaps do in the detailed_placement command?,"detailed_place -disallow_one_site_gaps will disallow the detailed placer from leaving gaps between cells that are exactly one cell sitewide. This feature is mainly useful for PDKs that do not have filler cells which are one site-wide. In this case, one-site-wide gaps are unfillable and will cause DRC violations." +What does the -disallow_one_site_gaps argument do in detailed_placement?,"detailed_place -disallow_one_site_gaps will disallow the detailed placer from leaving gaps between cells that are exactly one cell sitewide. This feature is mainly useful for PDKs that do not have filler cells which are one site-wide. In this case, one-site-wide gaps are unfillable and will cause DRC violations." +What does the argument -disallow_one_site_gaps do in the detailed_placement command?,"The detailed_place -disallow_one_site_gaps option prevents one-site-wide gaps between cells in detailed placement, addressing DRC issues in PDKs lacking one-site-wide filler cells." +What does the argument -report_file_name do in the detailed_placement command?,"The -report_file_name argument for the detailed_placement command specifies where the report for detailed placement should be saved. The report is saved in the JSON format and contains metrics related to detailed_placement. If this argument is not provided, no report will be saved for the detailed_placement command." +What role does the -report_file_name argument play in the detailed_placement command?,"The -report_file_name argument for the detailed_placement command specifies where the report for detailed placement should be saved. The report is saved in the JSON format and contains metrics related to detailed_placement. If this argument is not provided, no report will be saved for the detailed_placement command." +What does the argument -report_file_name do in the detailed_placement command?,"The detailed_placement command's -report_file_name argument designates the storage location for the placement report in JSON format, detailing metrics of the placement. Without this argument, the command does not save a report." +What does the Set Placement Padding command do?,"The set_placement_padding command sets left and right padding in multiples of the row site width. Use the set_placement_padding command before legalizing placement to leave room for routing. Use the -global flag for padding that applies to all instances. Use -instances for instance-specific padding. The instances insts can be a list of instance names, or an instance object returned by the SDC get_cells command. To specify padding for all instances of a common master, use the -filter ""ref_name == "" option to get_cells." +How does the Set Placement Padding command optimize placement?,"The set_placement_padding command sets left and right padding in multiples of the row site width. Use the set_placement_padding command before legalizing placement to leave room for routing. Use the -global flag for padding that applies to all instances. Use -instances for instance-specific padding. The instances insts can be a list of instance names, or an instance object returned by the SDC get_cells command. To specify padding for all instances of a common master, use the -filter ""ref_name == "" option to get_cells." +What does the Set Placement Padding command do?,"The set_placement_padding command adjusts the left and right padding based on row site width multiples, essential for spacing before placement legalization. It supports global padding via -global or specific instance padding through -instances, with flexibility in selecting instances via a list or the SDC get_cells command." +What is the significance of the filler_placement command?,"The filler_placement command fills gaps between detail-placed instances to connect the power and ground rails in the rows. filler_masters is a list of master/macro names to use for filling the gaps. Wildcard matching is supported, so FILL* will match, e.g., FILLCELL_X1 FILLCELL_X16 FILLCELL_X2 FILLCELL_X32 FILLCELL_X4 FILLCELL_X8. To specify a different naming prefix from FILLER_ use -prefix ." +What is the significance of the filler_placement command?,"The filler_placement command fills gaps between detail-placed instances to connect the power and ground rails in the rows. filler_masters is a list of master/macro names to use for filling the gaps. Wildcard matching is supported, so FILL* will match, e.g., FILLCELL_X1 FILLCELL_X16 FILLCELL_X2 FILLCELL_X32 FILLCELL_X4 FILLCELL_X8. To specify a different naming prefix from FILLER_ use -prefix ." +What is the significance of the filler_placement command?,The filler_placement command utilizes specified master names to fill gaps among placed instances for power and ground rail connectivity. It supports wildcard for master names selection and allows prefix customization with the -prefix option. +What is the purpose of the remove_fillers command?,This command removes all filler cells. +What does the remove_fillers command achieve?,This command removes all filler cells. +What is the purpose of the remove_fillers command?,This command clears all placed filler cells. +What does the check_placement command do?,The check_placement command checks the placement legality. It returns 0 if the placement is legal. +What does the check_placement command verify?,The check_placement command checks the placement legality. It returns 0 if the placement is legal. +What does the check_placement command do?,"The check_placement command verifies if the placement adheres to legality rules, returning 0 for a legal placement." +What does the argument -verbose in the check_placement command do?,The -verbose argument enables verbose logging in the check_placement command. +How does the -verbose argument in the check_placement command enhance its functionality?,The -verbose argument enables verbose logging in the check_placement command. +What does the argument -verbose in the check_placement command do?,Enabling the -verbose argument within the check_placement command activates detailed logging. +What does the argument -disallow_one_site_gaps in the check_placement command do?,The argument -disallow_one_site_gaps disables one site gap during placement check. +What effect does the -disallow_one_site_gaps argument have in the check_placement command?,The argument -disallow_one_site_gaps disables one site gap during placement check. +What does the argument -disallow_one_site_gaps in the check_placement command do?,The -disallow_one_site_gaps argument prevents gaps of one site in the placement legality check. +What role does this argument -report_file_name play in the check_placement command?,The argument -report_file_name in check_placement command files name for saving the report (e.g. report.json). +What information does the -report_file_name argument provide in the check_placement command?,The argument -report_file_name in check_placement command files name for saving the report (e.g. report.json). +What role does this argument -report_file_name play in the check_placement command?,"Within the check_placement command, the -report_file_name argument designates the report's filename, such as report.json." +What does the optimize_mirroring command do?,The optimize_mirroring command mirrors instances about the Y axis in a weak attempt to reduce the total half-perimeter wirelength (HPWL). No arguments are needed for this function. +What optimizations does the optimize_mirroring command perform?,The optimize_mirroring command mirrors instances about the Y axis in a weak attempt to reduce the total half-perimeter wirelength (HPWL). No arguments are needed for this function. +What does the optimize_mirroring command do?,"The optimize_mirroring command adjusts instances around the Y-axis to potentially lessen the total half-perimeter wirelength, requiring no additional arguments." +What are some useful developer commands in the detailed placement module in OpenROAD (dpl)?,"If you are a developer, you might find the following commands useful, 1. detailed_placement_debug: debug detailed placement. 2. get_masters_arg: get masters from a design. 3. get_inst_bbox: get the bounding box of an instance. 4. get_inst_grid_bbox: get the grid bounding box of an instance. 5. format_grid: format grid (takes in length x and site width w as inputs). 6. get_row_site: get row site name." +Can you list some advanced developer commands in the detailed placement module (dpl)?,"If you are a developer, you might find the following commands useful, 1. detailed_placement_debug: debug detailed placement. 2. get_masters_arg: get masters from a design. 3. get_inst_bbox: get the bounding box of an instance. 4. get_inst_grid_bbox: get the grid bounding box of an instance. 5. format_grid: format grid (takes in length x and site width w as inputs). 6. get_row_site: get row site name." +What are some useful developer commands in the detailed placement module in OpenROAD (dpl)?,"Developers might find commands like detailed_placement_debug, get_masters_arg, get_inst_bbox, get_inst_grid_bbox, format_grid, get_row_site beneficial for various debugging and configuration tasks." +What does the argument [-max_length ] do in the set_dft_config command of DFT- Design For Testing?,The argument [-max_length ] takes an integer as input for setting the maximum number of bits that can be in each scan chain. +What does the [-max_length ] argument in the set_dft_config command control?,The argument [-max_length ] takes an integer as input for setting the maximum number of bits that can be in each scan chain. +What does the argument [-max_length ] do in the set_dft_config command of DFT- Design For Testing?,The [-max_length ] argument sets a limit on the scan chain length in bits. +What does the argument [-clock_mixing] do in the set_dft_config command of DFT?,The argument [-clock_mixing] dictates how the architect mixes the scan flops based on the clock driver. The value no_mix creates scan chains with only one type of clock and edge. This may create unbalanced chains. The value clock_mix creates scan chains mixing clocks and edges. Falling edge flops are going to be stitched before the rising edge. +How does the [-clock_mixing] argument in the set_dft_config command affect DFT?,The argument [-clock_mixing] dictates how the architect mixes the scan flops based on the clock driver. The value no_mix creates scan chains with only one type of clock and edge. This may create unbalanced chains. The value clock_mix creates scan chains mixing clocks and edges. Falling edge flops are going to be stitched before the rising edge. +What does the argument [-clock_mixing] do in the set_dft_config command of DFT?,"The [-clock_mixing] argument controls the scan flops' arrangement based on the clock driver, with options for mixing or separating clock types and edges." +What does the report_dft_config command do in DFT- Design For Testing?,The report_dft_config command prints the current DFT configuration to be used by preview_dft and insert_dft. +What insights does the report_dft_config command offer in DFT- Design For Testing?,The report_dft_config command prints the current DFT configuration to be used by preview_dft and insert_dft. +What does the report_dft_config command do in DFT- Design For Testing?,The report_dft_config command outputs the current DFT setup for use in preview_dft and insert_dft. +What does the preview_dft command do in DFT- Design For Testing?,This command prints a preview of the scan chains that will be stitched by insert_dft. Use this command to iterate and try different DFT configurations. This command does not perform any modification to the design. +What preview does the preview_dft command provide in DFT- Design For Testing?,This command prints a preview of the scan chains that will be stitched by insert_dft. Use this command to iterate and try different DFT configurations. This command does not perform any modification to the design. +What does the preview_dft command do in DFT- Design For Testing?,"This command offers a glimpse into the scan chains to be established by insert_dft, allowing for DFT configuration experimentation without altering the design." +What does the argument [-verbose] do in the preview_dft command of DFT- Design For Testing?,The preview_dft command shows more information about each one of the scan chains that will be created. +How does the [-verbose] argument in the preview_dft command enhance its output?,The preview_dft command shows more information about each one of the scan chains that will be created. +What does the argument [-verbose] do in the preview_dft command of DFT- Design For Testing?,The preview_dft command provides detailed insights into the forthcoming scan chains. +What does the insert_dft command do in DFT- Design For Testing?,"The insert_dft command implements the scan chains into the design by performing the following actions: Scan Replace, Scan Architect, Scan Stitch. The result is a design with scan flops connected to form the scan chains." +What is the process of the insert_dft command in DFT- Design For Testing?,"The insert_dft command implements the scan chains into the design by performing the following actions: Scan Replace, Scan Architect, Scan Stitch. The result is a design with scan flops connected to form the scan chains." +What does the insert_dft command do in DFT- Design For Testing?,"By executing actions like Scan Replace, Scan Architect, and Scan Stitch, the insert_dft command integrates scan chains into the design." +Can you give me an example of a basic Design for Testing command?,Here is an example that will create scan chains with a max length of 10 bits mixing all the scan flops in the scan chains: set_dft_config -max_length 10 -clock_mixing clock_mix report_dft_config preview_dft -verbose insert_dft. +Could you provide a basic example of a Design for Testing command?,Here is an example that will create scan chains with a max length of 10 bits mixing all the scan flops in the scan chains: set_dft_config -max_length 10 -clock_mixing clock_mix report_dft_config preview_dft -verbose insert_dft. +Can you give me an example of a basic Design for Testing command?,An example command to create 10-bit long scan chains with mixed flops is: set_dft_config -max_length 10 -clock_mixing clock_mix report_dft_config preview_dft -verbose insert_dft. +What are the limitations of Design for Testing (DFT)?,"The limitations of DFT-Design for Testing are as follows: there are no optimizations for the scan chains, this is a WIP, there is no way to specify existing scan ports to be used by scan insertion, there is currently no way to define a user-defined scan path, and can only work with one-bit cells." +What are the known limitations of Design for Testing (DFT)?,"The limitations of DFT-Design for Testing are as follows: there are no optimizations for the scan chains, this is a WIP, there is no way to specify existing scan ports to be used by scan insertion, there is currently no way to define a user-defined scan path, and can only work with one-bit cells." +What are the limitations of Design for Testing (DFT)?,"DFT limitations include the absence of scan chain optimizations, the inability to specify existing scan ports for insertion, the lack of a method for defining custom scan paths, and compatibility only with one-bit cells." +What is the report_cts command in Clock Tree Synthesis (cst) in OpenROAD used for?,"It is used to extract metrics after a successful clock_tree_synthesis run. These metrics are the number of Clock Roots, number of Buffers Inserted, number of Clock Subnets, and number of Sinks." +What is the purpose of the report_cts command in Clock Tree Synthesis (cts) in OpenROAD?,"It is used to extract metrics after a successful clock_tree_synthesis run. These metrics are the number of Clock Roots, number of Buffers Inserted, number of Clock Subnets, and number of Sinks." +What is the report_cts command in Clock Tree Synthesis (cst) in OpenROAD used for?,"After running clock_tree_synthesis, use this to collect metrics such as the number of Clock Roots, Buffers Inserted, Clock Subnets, and Sinks." +What does the argument -out_file in report_cts command in Clock Tree Synthesis (cst) in OpenROAD do?,"The file to save cts reports. If this parameter is omitted, the report is streamed to stdout and not saved." +What does the -out_file argument in the report_cts command achieve?,"The file to save cts reports. If this parameter is omitted, the report is streamed to stdout and not saved." +What does the argument -out_file in report_cts command in Clock Tree Synthesis (cst) in OpenROAD do?,"Specifies the file for saving cts reports, defaulting to streaming to stdout if not provided." +What does the clock_tree_synthesis_debug command in Clock Tree Synthesis (cst) in OpenROAD do?,This command is an option to plot the CTS to GUI. +How does the clock_tree_synthesis_debug command assist in CST troubleshooting?,This command is an option to plot the CTS to GUI. +What does the clock_tree_synthesis_debug command in Clock Tree Synthesis (cst) in OpenROAD do?,This command allows for CTS visualization in the GUI. +What does the create_power_domain command do in upf?,This command creates power domain for a group of modules. +What does the create_power_domain command achieve in upf?,This command creates power domain for a group of modules. +What does the create_power_domain command do in upf?,Creates power domain for module groups. +What does the create_logic_port command do in upf?,"This command creates logic port. Direction must be specified from: in, out, inout." +What function does the create_logic_port command serve in upf?,"This command creates logic port. Direction must be specified from: in, out, inout." +What does the create_logic_port command do in upf?,Creates logic ports with specified directions. \ No newline at end of file diff --git a/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/Tools/Tools.xlsx b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/Tools/Tools.xlsx new file mode 100644 index 0000000..b29e92f Binary files /dev/null and b/flow-Agent/EDA-Corpus-main/Augmented_Data/Question-Answer/Tools/Tools.xlsx differ diff --git a/flow-Agent/EDA-Corpus-main/LICENSE b/flow-Agent/EDA-Corpus-main/LICENSE new file mode 100644 index 0000000..2f244ac --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/LICENSE @@ -0,0 +1,395 @@ +Attribution 4.0 International + +======================================================================= + +Creative Commons Corporation ("Creative Commons") is not a law firm and +does not provide legal services or legal advice. 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For +the avoidance of doubt, this paragraph does not form part of the +public licenses. + +Creative Commons may be contacted at creativecommons.org. diff --git a/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/DB_Dataset.csv b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/DB_Dataset.csv new file mode 100644 index 0000000..d5326bc --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/DB_Dataset.csv @@ -0,0 +1,4819 @@ +code,prompt +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input2' as mentioned in the prompt +inst = block.findInst('input2') +#Set the location to coordinates (22500, 33459) +inst.setLocation(22500,33459)","Set the location of the instance named 'input2' to coordinates (22500, 33459)." +"# Get the design block +block = design.getBlock() + +# Find the instance named ""output52"" +inst = block.findInst(""output52"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Print the net name + print(""Net:"", net.getName()) + + # Print the wire opcodes + net.printWire()",Print the wire opcode information of the the nets connecting to the instance output52 +"def get_metal_layers_and_io_top_layer(layer_name): + # Get the current block of the design + block = design.getBlock() + + # Get the technology information + tech = block.getTech() + + # Find the specified layer in the technology + layer = tech.findLayer(layer_name) + + # Get the upper and lower layers of the specified layer + upper_lower_layer = { + ""upper"": layer.getUpperLayer(), + ""lower"": layer.getLowerLayer() + } + + # Get the top layer of the IO Placer object of the design + iop = design.getIOPlacer() + iop_top_layer = iop.getTopLayer() + + # Return a tuple containing the upper and lower layer of the specified layer and the top layer used for the IO pin placer + return (upper_lower_layer, iop_top_layer) + +# Call the function with ""metal5"" as the argument +metal5_layers_info = get_metal_layers_and_io_top_layer(""metal5"")","Retrieve the upper and lower layers of the 'metal5' layer and encapsulate them in a dictionary with ""upper"" and ""lower"" as keys. Additionally, retrieve the setting of the top layer used for the IO pin placer. Return the results as a tuple." +"# Vertically flip the rotation of the instances whose library cell types are 'AND2_X1' + +#define flipping function +def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'NAND2_X1' + if inst.getMaster().getName() == 'NAND2_X1': + # Vertically flip the rotation of the instance + transform = inst.getTransform() + orient = transform.getOrient() + orient = flipY(orient) + inst.setOrient(orient)",Vertically flip the rotation of the instances whose library cell types are 'NAND2_X1' +"# Set the rotation of the instance '_411_' to 'MX' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('_411_') + +# Set the rotation of the instance to 'MX' +inst.setOrient('MX')",set the rotation of the instance '_411_' to 'MX' +"# Get the design block +block = ord.get_db_block() +# Get the database +db = ord.get_db() +# Get all nets +nets = block.getNets() +# Find the POWER and GROUND nets +for net in nets: + if net.getSigType() == 'POWER': + power_net = net + elif net.getSigType() == 'GROUND': + ground_net = net +# Find the source instance named ""_350_"" +source_inst = block.findInst(""_350_"") +# Find the pin connected to net ""_036_"" +for pin in source_inst.getITerms(): + if pin.getNet() is not None: + if pin.getNet().getName() == '_036_': + source_pin = pin + source_net = pin.getNet() + break +# Create a new net +new_net = odb.dbNet_create(block,'new_net_1') +# Find the master instance named 'BUF_X2' +mast = db.findMaster('BUF_X2') +# Create a new instance named 'new_inst_1' using the 'BUF_X2' master +new_inst = odb.dbInst_create(block,mast,'new_inst_1') +# Disconnect the source pin +source_pin.disconnect() +# Connect the source pin to the new net +source_pin.connect(new_net) +# Connect the pins of the new instance +for pin in new_inst.getITerms(): + if pin.isInputSignal(): + pin.connect(new_net) + elif pin.isOutputSignal(): + pin.connect(source_net) + elif pin.getSigType() == 'POWER': + pin.connect(power_net) + elif pin.getSigType() == 'GROUND': + pin.connect(ground_net) +","Add a new instance 'new_inst_1' using buffer cell BUF_X2 after the instance '_350_' on the net '_036', and connect the instances using a new net 'new_net_1'" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""req_val"" +port = block.findBTerm('req_val') +# Disconnect the port +port.disconnect()",Disconnect the port named 'req_val' from the nets it is connected to +"# Get the current design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# Dictionary to store Capacitance Coupling Match Ratio of each net +net_cc_match_ratio = {} + +# Iterate through each net and store its Capacitance Coupling Match Ratio +for net in nets: + net_cc_match_ratio[net.getName()] = net.getCcMatchRatio() + +# List of net names to set Capacitance Coupling Match Ratio to 1 +nets = [""req_msg[13]"", ""clk""] + +# Iterate through each net name in the list and set its Capacitance Coupling Match Ratio to 1 +for net_name in nets: + net = block.findNet(net_name) + net.setCcMatchRatio(1)","Calculate the Capacitance Coupling Match Ratio for each net and organize the results into a dictionary. Use the net names as keys and their corresponding Capacitance Coupling Match Ratios as values. Additionally, ensure that the Capacitance Coupling Match Ratios for the nets named ""req_msg[13]"" and ""clk"" are set to 1." +"# Get the current design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get the vias defined in the technology +vias = tech.getVias() + +# Get the Via Count of the technology +via_count = tech.getViaCount() + +# Set the Clearance Measure of the technology to 500 +print(tech.getClearanceMeasure()) + +# Create a dictionary containing vias and the count of vias +result = { + ""vias"": vias, + ""count"": via_count +}","Get the vias and via count as a dictionary with ""vias"" and ""count"" as keys, and print the Clearance Measure." +"# Get the current design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers defined in the technology file +layers = tech.getLayers() + +# Dictionary to store areas of layers with their names +layer_area_dict = {} + +# Iterate through each layer +for layer in layers: + # Store the area of the layer with its name in the dictionary + layer_area_dict[layer.getName()] = layer.getArea() + +# Create a result dictionary containing layer area dictionary and list of layer names +result = { + ""area_dict"": layer_area_dict, + ""layer_names"": list(layer_area_dict.keys()) +}","Retrieve the layer names defined in the technology as a list and obtain the corresponding areas of these layers of the technology, associating each area with its respective layer name in a dictionary. Return this result encapsulated in a dictionary with ""area_dict"" representing the areas of the layers and ""layer_names"" representing the list of layer names." +"# Get the current design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get the Via Count of the technology +via_count = tech.getViaCount() + +# Get the Via Generate Rules of the technology +via_rules = tech.getViaGenerateRules() + +# Get the current value of database units per micron and add 500 +db_microns = block.getDbUnitsPerMicron() + 500 + +# Set the new value of database units per micron +tech.setDbUnitsPerMicron(db_microns) + +# Create a dictionary containing via count, via rules, and the updated value of database units per micron +result = { + ""count"": via_count, + ""rules"": via_rules +}","Retrieve the via count and via generate rules of the technology. Return the result as a dictionary with ""count"" and ""rules"" as keys for the via count and via generate rules, respectively." +"# Get the current design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store rotation of the instances whose library cells are of type 'NOR2_X1' +NOR_transform_orient = {} + +# Iterate through each instance +for inst in insts: + # Check if the library cell name is ""NOR2_X1"" + if inst.getMaster().getName() == ""NOR2_X1"": + # Store the rotation of the instance + NOR_transform_orient[inst.getName()] = inst.getTransform().getOrient() + + # Check if the instance name is ""_411_"" or ""input1"" + if inst.getName() == ""_411_"" or inst.getName() == ""input1"": + # Mark the first output net of the instance + inst.getFirstOutput().getNet().setMark(True)","Get the rotation of the instances whose library cells are of type 'NOR2_X1' and return as a dict with instance name as keys, and mark the first output nets of the instances '_411_' and 'input1'." +"# Get the current design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Iterate through each instance +for inst in insts: + # Check if the master cell name contains ""NAND2_X1"" + if inst.getMaster().getName() == ""NAND2_X1"": + # Invert the instance + inst.getTransform().invert() + + # Check if the instance name is ""_411_"" or ""input1"" + if inst.getName() == ""_411_"" or inst.getName() == ""input1"": + # Get the transform of the instance + transform = inst.getTransform() + # If the orientation is 'R0', set it to 'MX'; if 'MX', set it to 'R0' + if transform.getOrient() == 'R0': + transform.setOrient('MX') + elif transform.getOrient() == 'MX': + transform.setOrient('R0')",Invert the offset and the rotation of instances whose library cells are 'NAND2_X1' and set the orient of the instance '_411_' to 'R0' if 'MX' or 'MX' if 'R0'. +"# Get the current design block +block = design.getBlock() + +# Find the instance '_411_' +inst = block.findInst('_411_') + +# Set the orientation of the instance '_411_' to 'MX' +inst.getTransform().setOrient('MX') + +# Get all instances +insts = block.getInsts() + +# Dictionary to store halos of instances +inst_halos = {} + +# Iterate through each instance +for inst in insts: + # Store the halo of the instance in the inst_halos dictionary + inst_halos[inst.getName()] = inst.getHalo()",Set the orientation of the instance '_411_' to 'MX' and retrieve all the halos of instances. Return the result as a dictionary with each instance's name as the key mapped to their halo. +"# Get the current design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Get the technology information +tech = block.getTech() + +# Get all layers defined in the technology +layers = tech.getLayers() + +# Initialize lists to store non-core instances and vertical tech layers with capacitance +vertical_layers = [] +non_core_insts = [] + +# Define the direction for the layers +direction = 'VERTICAL' + +# Iterate through each instance +for inst in insts: + # Check if instance is not core instance + if not inst.getMaster().isCore(): + # Add the instance to the list of non-core instances + non_core_insts.append(inst) + +# Iterate through each layer in the technology +for layer in layers: + # Check if the layer direction is VERTICAL + if layer.getDirection() == direction: + # Add the layer and its capacitance to the list of vertical layers + vertical_layers.append((layer, layer.getCapacitance()))",Get a list of all the non-core instances and a list of the vertical layers and their capacitance as a list of tuples. +"def get_signal_types_and_endcap_status(target_instance_name, check_instance_name='_411_'): + # Get the current design block + block = design.getBlock() + + # Get all the instances + insts = block.getInsts() + + # Find the instance with the name check_instance_name + check_instance = block.findInst(check_instance_name) + + # Dictionary to store signal types in nets + signal_type_dict = {} + + # Check if check_instance is of type ENDCAP or any of its subtypes + endcap_status = check_instance.isEndCap() + print(f""End cap status of cell '{check_instance_name}':"", endcap_status) + + # Loop through all instances + for inst in insts: + # Check if any of the user flags are set to true + if inst.getUserFlag1() or inst.getUserFlag2() or inst.getUserFlag3(): + # Set the level of the instance to 1 + inst.setLevel(1) + + # Check if the instance name matches target_instance_name + if inst.getName() == target_instance_name: + # Get the nets connected to the target instance + nets = [pin.getNet() for pin in inst.getITerms()] + + # Iterate through each net + for net in nets: + # Check if the net exists + if net: + # Store the signal type of the net in the dictionary + signal_type_dict[net.getName()] = net.getSigType() + break + + # Return the dictionary containing signal types in nets + return signal_type_dict + +# Call the function to get the signal types for 'input1' and check '_411_' +signal_types = get_signal_types_and_endcap_status('input1')","Check if the library cell of instance '_411_' is type ENDCAP and get all the instances whose user flags are set and set those instances to level 1, also get the signal types in the nets of instance 'input1'" +"# Set userFlags 1 and 3 true for instance '411' and retrieve the LEQ (Logic Equivalent) information associated with the library cell of instance '411'. + +# Get the dsign block +block = design.getBlock() + +# Find the instance '411' +inst = block.findInst(""_411_"") + +# Set userFlags 1 and 3 true +inst.setUserFlag1() +inst.setUserFlag3() + +# Get the library cell of instance '411' +master = inst.getMaster() + +# Retrieve the LEQ information associated with the library cell +LEQ = master.getLEQ()",Set userFlags 1and 3 true for instance '411' and retrieves the LEQ (Logic Equivalent) information associated with the library cell of instance '411'. +"def get_and_nand_info(): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Dictionary to store offsets of 'AND2_X1' instances + offset_dict_AND = {} + # Dictionary to store orientations of 'NAND2_X1' instances + orient_dict_NAND = {} + + # Iterate through instances + for inst in insts: + # Check if the master cell name is 'AND2_X1' + if inst.getMaster().getName() == ""AND2_X1"": + # Get transform and store offset + transform = inst.getTransform() + offset_dict_AND[inst.getName()] = transform.getOffset() + + # Check if the master cell name is 'NAND2_X1' + elif inst.getMaster().getName() == ""NAND2_X1"": + # Get transform and store orientation + transform = inst.getTransform() + orient_dict_NAND[inst.getName()] = transform.getOrient() + + # Return dictionaries of offsets and orientations + return offset_dict_AND, orient_dict_NAND + +# Call the function to retrieve the information +and_offsets, nand_orientations = get_and_nand_info()",Get the location of the instances whose library cell is 'AND2_X1' as a dicitonary with instance names as keys and get rotation of instance whose library cells are of type 'NAND2_X1'. +"# Set all the COVER master cells to frozen + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Iterate through instances +for inst in insts: + # Get the master of the instance + master = inst.getMaster() + # Check if the master is of type COVER + if master.isCover(): + # Set the COVER master cell to frozen so dbMTerms cannot be added or delete from the master + master.setFrozen()",set all the COVER master cells to frozen +"def get_signal_nets_and_blockages(): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # List to store nets with signal type 'SIGNAL' + signal_nets = [] + + # Iterate through instances + for inst in insts: + # Get all pins of the instance + pins = inst.getITerms() + # Iterate through pins + for pin in pins: + # Check if the signal type is 'SIGNAL' + if pin.getSigType() == 'SIGNAL': + # Add the net to the list + signal_nets.append(pin.getNet()) + + # Get all blockages in the block + blockages = block.getBlockages() + + # Return a tuple containing the list of nets and blockages + return (signal_nets, blockages) + +# Call the function to retrieve the information +signal_nets, blockages = get_signal_nets_and_blockages()","Get a list of all the nets of the instances whose signal type is ""SIGNAL"" and get all the blockages. Return the result as a tuple" +"# Get the design block +block =design.getBlock() + +# Reset the tapcell in the design +tapcell = design.getTapcell() +tapcell.reset() + +# Retrieve the coupling capacitance segments +coupling_segments = block.getCCSegs()",Reset the tapcell in the design and retrieve the coupling capacitance segments of the design block. +"# Get the list of hierarchical filler cell instances. + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# List to store hierarchical instances with filler cells +inst_list = [] + +# Iterate through instances +for inst in insts: + # Check if the instance is hierarchical and its master is a filler cell + if inst.isHierarchical() and inst.getMaster().isFiller(): + inst_list.append(inst)",Get the list of hierarchical filler cell instances. +"def get_resistor_segments_and_hybrid_rows(): + # Get the design block + block = design.getBlock() + + # Retrieve resistor segments + resistor_segments = block.getRSegs() + + # Get the sites of rows + rows = block.getRows() + hybrid_rows = {} + + # Iterate through rows to find hybrid sites + for row in rows: + if row.getSite().isHybrid(): + hybrid_rows[row] = row.getSite() + + # Return resistor segments and hybrid rows + return (resistor_segments, hybrid_rows) + +# Call the function to get the information +resistor_segments, hybrid_rows = get_resistor_segments_and_hybrid_rows()","Get the resistor segments and a dictionary of the hybrid sites of the rows, with the row as the key and the site as the value." +"# Get source type of all the instance on level 1 with filler cells and set the placement Status of the instance 'input1' to 'UNPLACED'. + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store source types +source_dict = {} + +# Iterate through instances +for inst in insts: + # Check if the instance's master is a filler cell and it is set as level 1 + if inst.getMaster().isFiller() and inst.getLevel() == 1: + # Get and store the source type + source_dict[inst.getName()] = inst.getSourceType() + + # Check if the instance is 'input1' and set its placement status to 'UNPLACED' + if inst.getName() == ""input1"": + inst.setPlacementStatus('UNPLACED')","Get source type of all the filler cell instances set as level 1 as a dictionary with inst name as keys. Also, set the placement status flag of the instance 'input1' to 'UNPLACED'." +"def set_layer_aliases_and_get_min_spacing(): + # Get the design block + block = design.getBlock() + + # Get the technology information + tech = block.getTech() + + # Get all layers + layers = tech.getLayers() + + # Initialize a dictionary to store the alias of each layer + layer_alias = {} + + # Iterate through all layers + for layer in layers: + # Construct the alias using the layer index + alias = ""LayerX"" + str(layer.getNumber()) + + # Set the alias of the layer + layer.setAlias(alias) + + # Store the alias of the layer in the dictionary + layer_alias[layer.getName()] = alias + + # Get the status of USEMINSPACING for pins in LEF + min_spacing_pin = tech.getUseMinSpacingPin() + + # Return the dictionary containing the updated alias of layers and min spacing status + return { + ""Alias"": layer_alias, + ""min_spacing_pin"": min_spacing_pin + } + +# Call the function to get the results +results = set_layer_aliases_and_get_min_spacing()","Set the alias of the layers by the naming convention ''LayerXi"" where i is the index of the layer and get the status of USEMINSPACING for pins in LEF. return the results as a dict with each requirement as key names." +"def get_mterms_and_input_mterms(inst_name_1, inst_name_2): + # Get the current block of the design + block = design.getBlock() + + # Find the instances using the provided names + inst1 = block.findInst(inst_name_1) + inst2 = block.findInst(inst_name_2) + + # Get the library cells of the instances + master1 = inst1.getMaster() + master2 = inst2.getMaster() + + # Get the MTerms of the library cell of the instance inst_name_1 + mterms1 = master1.getMTerms() + + # Get the MTerms of the library cell of the instance inst_name_2 + mterms2 = master2.getMTerms() + + # List to store input MTerms of the instance inst_name_2 + input_mterms = [] + + # Iterate through each MTerm of the instance inst_name_2 + for mterm in mterms2: + # Check if the IoType is 'INPUT' + if mterm.getIoType() == 'INPUT': + # Append the MTerm to the list of input MTerms + input_mterms.append(mterm) + + # Return a tuple containing MTerms of the library cell of instance inst_name_1 and input MTerms of instance inst_name_2 + return (mterms1, input_mterms) + +# Example call to the function +results = get_mterms_and_input_mterms('_411_', 'input1')",Get the MTerms of the library cell of the instance '_411_' and get the list of mterms of the instance 'input1' whose IoType is 'INPUT'. Return the results as a tuple +"# Get the current block of the design +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get the LEF version of the technology +lef_version = tech.getLefVersion() + +# get clearance measure of the technology +clearance_measure = tech.getClearanceMeasure() + +# Set Db units per micron to 1500 for the chip +tech.setDbUnitsPerMicron(1500) + +# Return the clearance measure and the LEF version of the technology +result = (clearance_measure, lef_version)",Get the clearance measure and set the Db units per micron to 1500 to the chip and get Lef version. return the result as a tuple. +"def check_input_pins_without_nets(): + # Get the design block + block = ord.get_db_block() + + # Get all instances + insts = block.getInsts() + + # Initialize a list to store input pins without nets + input_pin_wout_net = [] + + # Iterate over instances + for inst in insts: + # Get all pins of the instance + pins = inst.getITerms() + + # Iterate over pins + for pin in pins: + # Check if the pin is an input signal + if pin.isInputSignal(): + # Get the net connected to the pin + nets = pin.getNet() + # Check if the pin has no net connected + if nets is None: + # Append the pin to the list + input_pin_wout_net.append(pin) + + # Check if there are no input pins without nets + return len(input_pin_wout_net) == 0 + +# Call the function and print the result +result = check_input_pins_without_nets()",Check if all the input pins of all instances have a valid net connection +"# Get the design block +block = ord.get_db_block() +# Find the instance ""_split30_"" +inst = block.findInst(""_split30_"") +# Set the instance as don't touch type +inst.setDoNotTouch(True)","Set the instance ""_split30_"" as don't touch type" +"# Get the design block +block = ord.get_db_block() +# Get all instances +insts = block.getInsts() +# Create a list to store pin names +pin_name_list = [] +# Loop through all instances +for inst in insts: + # Get the pins of this instance + inst_ITerms = inst.getITerms() + # Loop through all pins + for ITerm in inst_ITerms: + # Append pin names to the list + pin_name_list.append(design.getITermName(ITerm))",Get the name of every pin +"# Invert the rotation and the location of instances with the library cell type 'NAND2_X1'. + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the name of the library cell type is 'NAND2_X1' + if inst.getMaster().getName() == 'NAND2_X1': + # Invert the rotation and the location of the instance + transform = inst.getTransform() + transform.invert() + inst.setTransform(transform)",Invert the rotation and the location of instances with the library cell type 'NAND2_X1' +"# Horizontally flip the rotation of the instances whose library cell types are 'AND2_X1' + +#define flipping function +def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Horizontally flip the rotation of the instance + orient = inst.getOrient() + orient = flipX(orient) + inst.setOrient(orient)",Horizontally flip the rotation of the instances whose library cell types are 'AND2_X1' +"# Horizontally flip the rotation of the instances whose library cell types are 'AND2_X1' + +#define flipping function +def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Horizontally flip the rotation of the instance + transform = inst.getTransform() + orient = transform.getOrient() + orient = flipX(orient) + transform.setOrient(orient) + inst.setTransform(transform)",Horizontally flip the rotation of the instances whose library cell types are 'AND2_X1' +"# Vertically flip the rotation of the instances whose library cell types are 'AND2_X1' + +#define flipping function +def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90"" + +# Get the design block +block = design.getBlock() + +# Get all instances in the block +insts = block.getInsts() + +# Iterate through all instances in the block +for inst in insts: + # Check if the library cell type is 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Vertically flip the rotation of the instance + transform = inst.getTransform() + orient = transform.getOrient() + orient = flipY(orient) + transform.setOrient(orient) + inst.setTransform(transform) +",Vertically flip the rotation of the instances whose library cell types are 'AND2_X1' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the technology layer with name 'metal8' +layer = tech.findLayer('metal8') +# Get the cut layer spacing rules +techLayerCutSpacingRules = layer.getTechLayerCutSpacingRules()",Get the cut layer spacing rules of layer with name 'metal8' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal10"" +layer = tech.findLayer('metal10') +# Return the end of line extension rules +techLayerEolExtensionRules = layer.getTechLayerEolExtensionRules()",Get the end of line extension rules of the technology layer with name 'metal10' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology object with technology information +tech = block.getTech() +# Find the layer with name ""via8"" +layer = tech.findLayer('via8') +# Return the tech layer forbidden spacing rules +techLayerForbiddenSpacingRules = layer.getTechLayerForbiddenSpacingRules()",Get the forbidden spacing rules of the technology layer with name 'via8' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""via1"" +layer = tech.findLayer('via1') +# Return the keepout zone rules +techLayerKeepOutZoneRules = layer.getTechLayerKeepOutZoneRules()",Get the keepout zone rules of the technology layer with name 'via1' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the technology layer called ""OVERLAP"" +layer = tech.findLayer('OVERLAP') +# Return two widths spacing rules +# API for version 5.7 two widths spacing rules, expressed as a 2D matrix +# with index tables +twoWidthsSpacingTableNumWidths = layer.getTwoWidthsSpacingTableNumWidths()",Get the two widths spacing rules of the technology layer with name 'OVERLAP' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the technology layer with name ""metal1"" +layer = tech.findLayer('metal1') +# Return the min cut rules +techLayerMinCutRules = layer.getTechLayerMinCutRules()",Get the minimum cut rules of the technology layer with name 'metal1' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the technology layer with name ""via2"" +layer = tech.findLayer('via2') +# Return the minimum step rules +techLayerMinStepRules = layer.getTechLayerMinStepRules()",Get the minimum step rules of the technology layer with name 'via2' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal3"" +layer = tech.findLayer('metal3') +# Return the collection of spacing rules for the object, assuming +# coding in LEF 5.4 format. +v54SpacingRules = layer.getV54SpacingRules()",Get the collection of spacing rules for the layer with name 'metal3' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal4"" +layer = tech.findLayer('metal4') +# Return the spacing end of line rules +techLayerSpacingEolRules = layer.getTechLayerSpacingEolRules()",Get the spacing end of line rules of layer with name 'metal4' +"def get_layer_type(layer_name): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get the technology information + tech = block.getTech() + + # Find the layer with the specified name + layer = tech.findLayer(layer_name) + + # Return the layer type + return layer.getType() + +# Call the function with the argument ""metal5"" +metal5_layer_type = get_layer_type('metal5')",Get the type of technology layer with name 'metal5' +"def get_via3_wrong_dir_spacing_rules(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get the technology information + tech = block.getTech() + + # Find the layer with name ""via3"" + layer = tech.findLayer('via3') + + # Return the wrong direction spacing rules + return layer.getTechLayerWrongDirSpacingRules() + +# Call the function to get the wrong direction spacing rules for ""via3"" +via3_wrong_dir_spacing_rules = get_via3_wrong_dir_spacing_rules()",Get the wrong direction spacing rules of layer with name 'via3' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal1"" +layer = tech.findLayer('metal1') +# Return the x-axis offset +offset = layer.getOffset()",Get the offset along the x-axis of the technology layer with name 'metal1' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal2"" +layer = tech.findLayer('metal2') +# Return the x-axis offset +offsetX = layer.getOffsetX()",Get the offset along the x-axis of the technology layer with name 'metal2' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal3"" +layer = tech.findLayer('metal3') +# Return the y-axis offset +offsetY = layer.getOffsetY()",Get the offset along the y-axis of the technology layer with name 'metal3' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal3"" +layer = tech.findLayer('metal3') +# Return the y-axis offset +layer.setOffsetXY(0.2, 0.15)",Change the offset setting along the x-axis to 0.2 microns and the y-axis to 0.15 microns for the technology layer named 'metal3'. +"def get_design_info(): + # Retrieve block information + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Get the technology information + tech = block.getTech() + + # Initialize a dictionary to store instance halos + inst_halos = {} + + # Iterate through each instance and store halo information + for inst in insts: + inst_halos[inst.getName()] = inst.getHalo() + + # Find layer information for 'metal4' and get EOL rules + layer4 = tech.findLayer('metal4') + layer_spacing_eol_rules = layer4.getTechLayerSpacingEolRules() + + # Find layer information for 'metal8' and get corner spacing rules + layer8 = tech.findLayer('metal8') + layer8_corner_spacing_rules = layer8.getTechLayerCornerSpacingRules() + + # Find layer information for 'metal5' and get cut class rules + layer5 = tech.findLayer('metal5') + layer_cut_class_rules = layer5.getTechLayerCutClassRules() + + # Store all the collected information in a dictionary + result = { + ""halos"": inst_halos, + ""metal4_EOL"": layer_spacing_eol_rules, + ""metal8_corner_spacing_rules"": layer8_corner_spacing_rules, + ""cut_class_rules"": layer_cut_class_rules + } + + # Return the collected information + return result + +# Call the function to get the design information +design_info = get_design_info()","Get the following in a dictionary, with the given key names: +1. get all the halos of the instances with inst name as key. the key should be halos. +2. Get the routing layers spacing EOL rules of layer with name 'metal4'. The key should be metal4_EOL. +3. Get the routing layers corner spacing rules of layer with name 'metal8'. The key should be metal8_corner_spacing_rules. +4. get the routing layers cut class rules of layer with name 'metal8'. The key name for this will be cut_class_rules." +"# Get the current design block +block = design.getBlock() + +# Retrieve the capacitor-coupled segments +cc_segments = block.getCCSegs() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store source type of instances on level 1 whose master cells are either NAND or NOR +src_type = {} + +# Iterate through each instance +for inst in insts: + # Get the library cell of the instance + master = inst.getMaster() + + # Check if the library cell is special power type + if master.isSpecialPower(): + # Set the master of the instance as frozen so dbMTerms cannot be added or delete from the master once it is frozen. + inst.getMaster().setFrozen(True) + + # Check if the name of library cell is ""NAND2_X1"" or ""NOR3_X1"" and the instance is on level 1 + if (master.getName() == ""NAND2_X1"" or master.getName() == ""NOR3_X1"") and inst.getLevel() == 1: + # Store the source type of the instance in the dictionary + src_type[inst.getName()] = inst.getSourceType()","Retrieve the capacitor-coupled segments and frozen the library cells with special power type, then get source type of all the instances on level 1 whose master cells are either ""NAND2_X1"" or ""NOR3_X1""." +"# Get the current design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Find the instance '_411_' +inst1 = block.findInst('_411_') + +# Set user-defined flags 1 and 3 for instance '_411_' +inst1.setUserFlag1() +inst1.setUserFlag3() + +# Find the instance 'input1' +inst2 = block.findInst('input1') + +# Mark the first output nets of the instances '_411_' and 'input1' +net1 = inst1.getFirstOutput().getNet() + +# Dictionary to store instance transform offsets +inst_transform_offset_dict = {} + +# Iterate through each instance +for inst in insts: + # Check if the master cell name is ""AND2X_1"" + if inst.getMaster().getName() == ""AND2X_1"": + # Store the offset of the instance with master 'AND2_X1' + inst_transform_offset_dict[inst.getName()] = inst.getTransform().getOffset()","Set user-defined flags 1 and 3 for instance '_411_' and mark the first output nets of the instances '_411_' and 'input1', followed by getting the offset of the instances whose master is 'AND2_X1' in the form of dictionary with instance name as key." +"# Get the current design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store instances and their respective regions +inst_regions = {} + +# List to store pad instances on level 0 +inst_list = [] + +# Iterate through each instance +for inst in insts: + # Store instance name and its region in the inst_regions dictionary + inst_regions[inst.getName()] = inst.getRegion() + + # Check if the instance is a pad and it's on level 0 + if inst.isPad() and inst.getLevel() == 0: + # Append the instance to the list of pad instances + inst_list.append(inst) + + # Check if the instance name is ""input1"" + if inst.getName() == ""input1"": + # Iterate through each pin of the instance + for pin in inst.getITerms(): + # Get the net connected to the pin + net = pin.getNet() + # Check if the net exists + if net: + # Set RC disconnected for the net + net.setRCDisconnected(True)",Retrieve the instances and their corresponding areas if they are PAD or any of its subtypes and set as level 0. Proceed to disconnect the RC for the networks associated with the 'input1' instance. +"# Get the current design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Dictionary to store offsets of instances whose master cell is 'NAND2_X1' +NAND_offsets = {} + +# Iterate through each instance +for inst in insts: + # Check if the library cell name is ""NAND2_X1"" + if inst.getMaster().getName() == ""NAND2_X1"": + # Store the xy location of the instance + NAND_offsets[inst.getName()] = inst.getTransform().getOffset() + + # Check if the instance name is ""_411_"" + if inst.getName() == ""_411_"": + # Iterate through each pin of the instance + for pin in inst.getITerms(): + # Get the net connected to the pin + net = pin.getNet() + # Check if the net exists + if net: + # Set RC disconnected for the net + net.setRCDisconnected(True) +",Get the offset of all 'NAND2_X1' cells and set the RC disconnected for the nets of the instance 'input1'. +"# Get the current block of the design +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get the count of Manufacturing Grid +mfg = tech.getManufacturingGrid() + +# Find the net with name ""req_msg[13]"" +net = block.findNet(""req_msg[13]"") + +# Set the Capacitance Coupling Adjust Order of the net to 1 +net.setCcAdjustOrder(1)","Get the count of manufacturing grid and set the capacitance Coupling Adjust Order of the net with name ""req_msg[13]"" to 1." +"# Get the nets of the input pins of instance 'output53' + +block = design.getBlock() + +# find the instance 'output53' +inst = block.findInst('output53') + +# Initialize a list to store nets of input pins +input_nets = [] + +# Get all input pins (ITerms) of the instance +pins = inst.getITerms() + +# Iterate through all input pins +for pin in pins: + # Check if the pin is an input signal + if pin.isInputSignal() and pin: + # If it's an input signal, add its net to the list + input_nets.append(pin.getNet())",get the nets connected to the input pins of the instance 'output53' +"# Retrieve all instances that have a hierarchy and whose library cell type is 'AND2_X1' and are on level 1. + +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a list to store matching instances +inst_list = [] + +# Iterate through all instances +for inst in insts: + # Check if the instance has hierarchy, its library cell is 'AND2_X1', and it is on level 1 + if inst.isHierarchical() and inst.getMaster().getName()==""AND2_X1"" and inst.getLevel() == 1: + # Add the instance to the list + inst_list.append(inst)",Retrieve all instances that have a hierarchy and whose library cell type is 'AND2_X1' and are on level 1. +"# Get the resistor segments + +# Get the design block +block = design.getBlock() + +# Return the resistor segments +RSegs = block.getRSegs()",get the resistor segments of the design block +"# Retrieve the LEQ (Logical equivalent) information associated with the library cell of instance '_411_' + +# Get the design block +block = design.getBlock() + +# Find the instance with name '_411_' +inst = block.findInst('_411_') + +# Get the library cell associated with the instance +master = inst.getMaster() + +# Retrieve the LEQ information +leq_info = master.getLEQ()",Retrieves the LEQ (Logical equivalent) information associated with the library cell of instance '_411_' +"# Get all the pad and set as level 1 + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Initialize a list to store matching instances +inst_list = [] + +# Iterate through all instances +for inst in insts: + # Check if the instance is a pad and it is level 1 + if inst.isPad() and inst.getLevel() == 1: + # Add the instance to the list + inst_list.append(inst)",get all the pad instances that are level 1 +"# Get the vertical thickness multiplier for the IO pin placer's parameters and set corner avoidance to 50 + +# Get the IO pin placer +iop = design.getIOPlacer() + +# Get the parameters of the IO pin placer +parameters = iop.getParameters() + +# Set corner avoidance to 50 +parameters.setCornerAvoidance(50) + +# Return the vertical thickness multiplier +verticalThicknessMultiplier = parameters.getVerticalThicknessMultiplier()",get the vertical thickness multiplier for the IO pin placer's parameters and set corner avoidance to 50 +"# Get the design block +block = design.getBlock() + +# Find the instance named ""FILLER_0_17_159"" +inst = block.findInst(""FILLER_0_17_159"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Reverse the resistor segment sequence of the net + net.reverseRSegs() +",Reverse the resistor segment seqence of the nets of the instance FILLER_0_17_159 +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store nets with wire-ordered flag set as True +ordered_wires = [] + +# Iterate through each net +for net in nets: + # Check if the wire-ordered flag is set to true + if net.isWireOrdered(): + # Append the net to the list + ordered_wires.append(net)","Get the nets if their wire-ordered flag is set as True, and return it as a list" +"# Get the design block +block = design.getBlock() + +# List to store nets with ordered wires +ordered_wires = [] + +# List of net names +nets = [ + ""net1"", + ""net10"", + ""net11"", + ""net12"", + ""net13"", + ""net14"", + ""net15"", + ""net16"", + ""net17"", + ""net18"", + ""net19"" +] + +# Iterate through each net name +for name in nets: + # Find the net object by name + net = block.findNet(name) + + # Set the wire ordered flag to true + net.setWireOrdered(True) + + # Append the net to the list of nets with ordered wires + ordered_wires.append(net)","Set the wires ordered flag to true for the following nets and return a list of these nets: net1, net10, net11, net12, net13, net14, net15, net16, net17, net18, net19 +" +"# Get the design block +block = design.getBlock() + +# List to store nets +altered_wires_net = [] + +# List of net names +nets = [ + ""_000_"", + ""_001_"", + ""_002_"", + ""_003_"", + ""_004_"", + ""_005_"", + ""_006_"", + ""_007_"", + ""_008_"", + ""_009_"", + ""_010_"" +] + +# Iterate through each net name +for name in nets: + # Find the net object by name + net = block.findNet(name) + + # Set the wire update flag to true + net.setWireAltered(True) + + # Append the net to the list of nets + altered_wires_net.append(net)","Set the wire update flag to true for the wires of the following nets and return a list of these nets: _000_, _001_, _002_, _003_, _004_, _005_, _006_, _007_, _008_, _009_, _010_ +" +"# Get the design block +block = design.getBlock() + +# List to store selected nets +selected_nets = [] + +# List of net names to select +net_names = [ + ""net1"", + ""net10"", + ""net11"", + ""net12"", + ""net13"", + ""net14"", + ""net15"", + ""net16"", + ""net17"", + ""net18"", + ""net19"" +] + +# Iterate through each net name +for name in net_names: + # Find the net object by name + net = block.findNet(name) + + # Set the net as selected + net.setSelect(True) + + # Append the selected net to the list + selected_nets.append(net)","set the select flag true for the following nets and return the list of these nets: net1, net10, net11, net12, net13, net14, net15, net16, net17, net18, net19 +" +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store nets +wild_connected_nets = [] + +# Iterate through each net +for net in nets: + # Check if the net is connected using a wild-card + if net.isWildConnected(): + # Append the net to the list + wild_connected_nets.append(net)",Get the nets connected using a wild-card. +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store nets marked as ""do not touch"" +do_not_touch_nets = [] + +# Iterate through each net +for net in nets: + # Check if the net is set as ""do not touch"" + if net.isDoNotTouch(): + # Append the net to the list + do_not_touch_nets.append(net)",Get the nets that are set as do not touch and return as a list +"# Get the design block +block = design.getBlock() + +# Find the instance named ""input6"" +inst = block.findInst(""input6"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective coupled capacitor adjust orders +net_Cc_adjust_order = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its coupled capacitor adjust order in the dictionary + net_Cc_adjust_order[net.getName()] = net.getCcAdjustOrder()",Get the coupled capacitor adjust order for the nets of the instance input6 and return the result as a dict with key being net name and value being the coupled capacitor adjust order +"# Get the design block +block = design.getBlock() + +# Find the instance named ""input6"" +inst = block.findInst(""input6"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective wire types +net_wire_type = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its wire type in the dictionary + net_wire_type[net.getName()] = net.getWireType()",Get the wire types of the nets connecting to the instance input6 and return the result as a dictionary with key being net name and value being the wire type +"# Get the design block +block = design.getBlock() + +# List to store marked nets +marked_nets = [] + +# List of net names to mark +nets_to_mark = [ + ""resp_msg[4]"", + ""resp_msg[5]"", + ""resp_msg[6]"", + ""resp_msg[7]"", + ""resp_msg[8]"", + ""resp_msg[9]"", + ""resp_rdy"", + ""resp_val"" +] + +# Iterate through each net name +for name in nets_to_mark: + # Find the net object by name + net = block.findNet(name) + + # Set the mark flag of the net to True + net.setMark(True) + + # Append the marked net to the list + marked_nets.append(net)","Set mark flags to the nets resp_msg[4], resp_msg[5], resp_msg[6], resp_msg[7], resp_msg[8], resp_msg[9], resp_rdy, resp_val and return the list of market nets." +"# Get thedesign block +block = design.getBlock() + +# Find the instance named ""input6"" +inst = block.findInst(""input6"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective total resistances +net_total_resistance = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its total resistance in mil ohms in the dictionary + net_total_resistance[net.getName()] = net.getTotalResistance()","Get the total resistance in mil ohms of the nets connecting to the instance ""input6"" and return the result as a dict using net name as key and resistance as value" +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store nets connected by abutment +abutment_nets = [] + +# Iterate through each net +for net in nets: + # Check if the net have its pins connected by abutment + if net.isConnectedByAbutment(): + # Append the net to the list + abutment_nets.append(net)",Get the nets that have their pins connected by abutment and return as a list +"# Get the design block +block = design.getBlock() + +# Find the instance named ""_699_"" +inst = block.findInst(""_699_"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective coupled capacitor match ratio +net_cc_match_ratio = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its coupled capacitor match ratio in the dictionary + net_cc_match_ratio[net.getName()] = net.getCcMatchRatio()","Get the coupled capacitor match ratio of the nets connecting to the instance ""_699_"" and return as a dict using net name as key and coupled capacitor match ratio as value" +"# Get the design block +block = design.getBlock() + +# Find the instance named ""input10"" +inst = block.findInst(""input10"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective node capacitors +net_cap_nodes = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its cap nodes in the dictionary + net_cap_nodes[net.getName()] = net.getCapNodes()","Get the node capacitor of the RC segment belong to each net connecting to the instance input10, and return the result as a dict with net name being keys and node capacitors as values" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name ""metal4"" +layer = tech.findLayer('metal4') +# Return the pitch of the layer +pitch = layer.getPitch()","Get the pitch setting of ""metal 4"" layer" +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store extracted nets +extracted_nets = [] + +# Iterate through each net +for net in nets: + # Check if the net is extracted + if net.isExtracted(): + # Append the extracted net to the list + extracted_nets.append(net)",Get all extracted nets as a list +"# Get the design block +block = design.getBlock() + +# Find the instance named ""input10"" +inst = block.findInst(""input10"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective routing guides +net_guides = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its routing guides in the dictionary + net_guides[net.getName()] = net.getGuides()","Get the routing guides of the nets connecting to the instance ""input10"" as a dictionary, using net name as keys and routing guide as values" +"# Get the design block +block = design.getBlock() + +# Find the instance named ""FILLER_0_17_13"" +inst = block.findInst(""FILLER_0_17_13"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective tracks +net_tracks = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its tracks in the dictionary + net_tracks[net.getName()] = net.getTracks()","Get the tracks of the nets connecting to the instance ""FILLER_0_17_13"", and return it as a dict using net name as keys and tracks as values" +"# Get the design block +block = design.getBlock() + +# Find the instance named ""rebuffer29"" +inst = block.findInst(""rebuffer29"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Reverse the coupled capacitor segments of the net + net.reverseCCSegs()",Reverse the coupled capacitor segments of the nets connecting to the instance called rebuffer29 +"# Get the design block +block = design.getBlock() + +# Find the instance named ""rebuffer9"" +inst = block.findInst(""rebuffer9"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective driving ITerms +net_driving_iterm = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its driving term id assigned of this net. -1 if not set, 0 if non existent + net_driving_iterm[net.getName()] = net.getDrivingITerm()","Get the driving term ids for the nets connecting to the instance rebuffer9, and return the rsult as a dict using net name as keys and driving term ids as values" +"# Get the design block +block = design.getBlock() + +# Find the instance named ""_706_"" +inst = block.findInst(""_706_"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective Cap node counts +net_cap_node_count = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its node capacitor count in the dictionary + net_cap_node_count[net.getName()] = net.getCapNodeCount()","Get the node capacitor count of RC segments of the nets connecting to the instance _706_, and return the result as a dictionary with keys being net name, and values being node capacitor count " +"# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets() + +# List to store nets that are RC graphs +rc_graph_nets = [] + +# Iterate through each net +for net in nets: + # Check if the rc_graph flag set, and the flag is set when Rseg and CapNodes were created + if net.isRCgraph(): + # Append the net to the list + rc_graph_nets.append(net)","Get all the nets if their rc_graph flag is set, and return the result as a list" +"# Get the design block +block = design.getBlock() + +# Find the instance named ""split30"" +inst = block.findInst(""split30"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective term counts +net_term_count = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and the amount of pins and ports of this net in the dictionary + net_term_count[net.getName()] = net.getTermCount()","Get the amount of pins and ports of the nets connecting to the instance ""split30"" and return it as a dictionary with net name being keys" +"# Get the design block +block = design.getBlock() + +# Find the instance named ""clkbuf_0_clknet_2_3__leaf_clk"" +inst = block.findInst(""clkbuf_0_clknet_2_3__leaf_clk"") + +# Get all pins (interface terms) connecting to the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective x-talk classes +net_X_Talk_class = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its x-talk class in the dictionary + net_X_Talk_class[net.getName()] = net.getXTalkClass()","Get the x-talk-class of the nets connecting to the instance ""clkbuf_0_clknet_2_3__leaf_clk"", as a dictionary with the net names as key values." +"# Get the design block +block = design.getBlock() + +# Find the instance named ""rebuffer5"" +inst = block.findInst(""rebuffer5"") + +# Get all pins (interface terms) connecting to the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective first BTerms +net_first_bterms = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its first BTerm in the dictionary + net_first_bterms[net.getName()] = net.get1stBTerm()","Get the first port of the nets connecting to the instance rebuffer5, as a dictionary with the net names as key values." +"# Get the design block +block = design.getBlock() + +# Find the instance named ""input22"" +inst = block.findInst(""input22"") + +# Get all pins (interface terms) connecting to the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective R segment counts +net_R_seg_count = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its R segment count in the dictionary + net_R_seg_count[net.getName()] = net.getRSegCount()","Get the R segment count of the RC network connected to the nets of the instance input22, return the result as a dictionary with net names as key values." +"# Get the design block +block = design.getBlock() + +# Find the instance named ""_686_"" +inst = block.findInst(""_686_"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective nondefault rule applied for wiring +net_non_default_rule = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and the nondefault rule applied to this net for wiring in the dictionary, returns nullptr if there is no nondefault rule. + net_non_default_rule[net.getName()] = net.getNonDefaultRule()",Get the nondefault rule applied to the nets connected to the instance _686_ as a dictionary with the net names as key values. +"# Get the design block +block = design.getBlock() + +# Find the instance named ""_706_"" +inst = block.findInst(""_706_"") + +# Get all pins (interface terms) of the instance +pins = inst.getITerms() + +# Dictionary to store net names and their respective zeroth R segments +net_zero_R_segment = {} + +# Iterate through each pin of the instance +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + + # Check if a net is connected to the pin + if net: + # Store the net name and its zeroth R segment in the dictionary + net_zero_R_segment[net.getName()] = net.getZeroRSeg()",Get the zeroth R segment of the nets of the instance _706_ as a dictionary with the net names as key values. +"# Get the current design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Get all layers defined in the technology +layers = tech.getLayers() + +# Dictionary to store layer directions with their names +layer_direction_dict = {} + +# Dictionary to store upper and lower layers of the 'poly' layer +poly_upper_lower_layers = {} + +# Iterate through each layer +for layer in layers: + # Store the direction of the layer with its name in the dictionary + layer_direction_dict[layer.getName()] = layer.getDirection() + + # If the layer name is 'poly', store its upper and lower layers + if layer.getName() == ""poly"": + poly_upper_lower_layers = { + ""upper"": layer.getUpperLayer(), + ""lower"": layer.getLowerLayer() + } + +# Create a result dictionary containing layer directions and 'poly' upper and lower layers +result = { + ""layer_directions"": layer_direction_dict, + ""poly"": poly_upper_lower_layers +}","Get the routing directions of the layers with their names as keys and also get the layers above and below the layer with name 'poly'. Finally, return them as dict of dicts" +"def get_io_placer_report(): + # Get the IO Placer object of the design + iop = design.getIOPlacer() + + # Get the parameters of the IO Placer + parameters = iop.getParameters() + + # Construct the output string with corner avoidance, HPWL report, and number of slots + output_string = ""Corner Avoidance: {}\nHPWL Report: {}\nNumber of slots: {}"".format( + parameters.getCornerAvoidance(), + parameters.getReportHPWL(), + parameters.getNumSlots() + ) + + return output_string + +# Call the function to get the IO Placer report +io_placer_report = get_io_placer_report()","Get the corner avoidance, number of slots and HPWL report of the IO pin placer" +"def get_io_placer_lengths(): + # Get the IO Placer object of the design + iop = design.getIOPlacer() + + # Get the parameters of the IO Placer + parameters = iop.getParameters() + + # Return the vertical and horizontal length as a tuple + return (parameters.getVerticalLength(), parameters.getHorizontalLength()) + +# Call the function to get the lengths +io_placer_lengths = get_io_placer_lengths()",Get the vertical and horizontal length of the setting of the IO pin placer +"from openroad import Tech, Design + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 10 um +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks()","Show me the piece of code to perform floorplanning using a utilization rate of 50% and an aspect ratio of 0.66, and set the spacing between the core and the die to 10 microns" +"def get_master_types_of_instances(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Retrieve all instances present in the design block + insts = block.getInsts() + + # Initialize an empty list to store the names of library cell type for each instance + masters_list = [] + + # Iterate over each instance in the design block + for inst in insts: + # Retrieve the library cell type of the current instance + master_type = inst.getMaster() + # Get the name of the library cell type + master_type_name = master_type.getName() + # Append the name of the library cell type to the list + masters_list.append(master_type_name) + + return masters_list + +# Call the function to get the master types +master_types_list = get_master_types_of_instances()",Give me the names of library cell type of every instance +"def get_instance_levels(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Retrieve all instances present in the design block + insts = block.getInsts() + + # Dictionary to store the level of each instance + level_of_instance = {} + + # Iterate over each instance in the design block + for inst in insts: + # Retrieve the name of the instance and its level, then store it in the dictionary + level_of_instance[inst.getName()] = inst.getLevel() + + return level_of_instance + +# Call the function to get the instance levels +instance_levels = get_instance_levels()",Get the level of all instances with the instance name as a dictionary. Key of the dictionary is name of the instance and value is the level of the instance +"def get_const_names_of_instances(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Retrieve all instances present in the design block + insts = block.getInsts() + + # Initialize an empty list to store the constant names of the instances + const_name = [] + + # Iterate over each instance in the design block + for inst in insts: + # Append the constant name of the instance + const_name.append(inst.getConstName()) + + return const_name + +# Call the function to get the constant names +constant_names = get_const_names_of_instances()",Get all the Constant names of the instances and return as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +print("" name | net_type | pin&wire_capacitance"") +# Retrieve all nets present in the design block +nets = block.getNets() +# Iterate over each net in the design block +for net in nets: + # Get the net capacitance + pin_and_wire_cap = timing.getNetCap(net, corner, timing.Max) + # Get the name of the net + net_name = net.getName() + # Get the signal Type of the net + net_type = net.getSigType() + print(f""{net_name:<12}| {net_type:<9}| {pin_and_wire_cap:19.4e}"")","Write a code to Print the name of the net, its net type, and the wire capacitance of all the nets" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Retrieve all instances present in the design block +insts = block.getInsts() +print("" name | rise_arrival_time | fall_arrival_time | rise_slack | fall_slack | slew"") +# Iterate over each instance in the design block +for inst in insts: + # Get the pins associated with the instance + inst_ITerms = inst.getITerms() + # Iterate through all the pins + for pin in inst_ITerms: + # Check if the pin is in supply + if design.isInSupply(pin): + continue + # Get the pin name + pin_name = design.getITermName(pin) + # Get the pin rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Get the pin fall arrival time + pin_fall_arr = timing.getPinArrival(pin, timing.Fall) + # Get the pin rise slack + pin_rise_slack = timing.getPinSlack(pin, timing.Fall, timing.Max) + # Get the pin fall slack + pin_fall_slack = timing.getPinSlack(pin, timing.Rise, timing.Max) + # Get the pin slew + pin_slew = timing.getPinSlew(pin) + print(f""{pin_name:<12} | {pin_rise_arr:17.4e} | {pin_fall_arr:17.4e} | {pin_rise_slack:10.4e} | {pin_fall_slack:10.4e} | {pin_slew:6.4e}"") ","Write a code to print all the pin names, rising arrival time, fall arrival time, rise stack, fall stack and slew of all the pins" +"def get_number_of_library_cell_types(): + # Get the OpenROAD database + db = ord.get_db() + + # Get the number of library cell types + return db.getNumberOfMasters() + +# Call the function to get the number of library cell types +num_library_cell_types = get_number_of_library_cell_types()",Get the number of library cells in the library +"def calculate_die_area(): + # Get the design block + block = ord.get_db_block() + + # Get the die area of the design + area = block.getDieArea() + + # Get the width and height of the die area + dx = area.dx() + dy = area.dy() + + # Calculate the die area + die_area = dx * dy + + return die_area + +# Call the function to calculate the die area +die_area = calculate_die_area()",Get the die area +"def calculate_core_area(): + # Get the design block + block = ord.get_db_block() + + # Get the core area of the design + area = block.getCoreArea() + + # Get the width and height of the core area + dx = area.dx() + dy = area.dy() + + # Calculate the core area + core_area = dx * dy + + return core_area + +# Call the function to calculate the core area +core_area = calculate_core_area()",Get the core area +"def report_global_connections(): + # Get the design block + block = ord.get_db_block() + + # Report global connection of the design + global_connection = block.reportGlobalConnect() + + return global_connection + +# Call the function to report global connections +global_connections = report_global_connections()",Report all the global connection rules +"def calculate_total_pins(): + # Get the design block + block = ord.get_db_block() + + # Initialize a variable to store the total number of pins + total_pins = 0 + + # Get instances + insts = block.getInsts() + + # Iterate over instances + for inst in insts: + # Add the number of pins of the instance to the total + total_pins += len(inst.getITerms()) + + return total_pins + +# Call the function to calculate the total number of pins +total_pins = calculate_total_pins()",Get the total number of pins +"def check_clock_nets_exist(): + # Get the design block + block = ord.get_db_block() + + # Initialize a list to store clock nets + clock_nets = [] + + # Get all nets + nets = block.getNets() + + # Iterate over nets + for net in nets: + # Check if the net is a CLOCK net + if net.getSigType() == 'CLOCK': + clock_nets.append(net) + + # Check if CLOCK nets exist + return len(clock_nets) > 0 + +# Call the function to check for the existence of clock nets +clock_nets_exist = check_clock_nets_exist()",Check if the design has any clock nets +"def count_power_and_ground_nets(): + # Get the design block + block = ord.get_db_block() + + # Initialize variables to count power and ground nets + power_nets = 0 + ground_nets = 0 + + # Get all nets + nets = block.getNets() + + # Iterate over nets + for net in nets: + # Check if the net is a POWER net + if net.getSigType() == 'POWER': + power_nets += 1 + # Check if the net is a GROUND net + elif net.getSigType() == 'GROUND': + ground_nets += 1 + + # Return the counts of power and ground nets + return power_nets, ground_nets + +# Call the function to get the counts of power and ground nets +power_net_count, ground_net_count = count_power_and_ground_nets()",Get the total number of power and ground nets +"# Get the chip associated with the design's block. + +# Retrieve the design block +block = design.getBlock() + +# Get the chip associated with the design block. +chip = block.getChip() ",Give me the chip of a given block +"# Get the nets in a given block + +# Get the design block +block = design.getBlock() + +# Get all nets +nets = block.getNets()",Get all nets in a given block +design.getBlock().getName(),Get the name of the design block +"# Get the logic ports for a given block + +# Get the design block +block = design.getBlock() + +# Get all logic ports +logic_ports = block.getLogicPorts()",Get the logic ports for a given block +"# Get the location of all instances +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Iterate through all instances +for inst in insts: + # Print the instance name and its location + print(inst.getName(), ""Location:"", inst.getLocation())",Get the location of all instances +"def is_instance_placed(instance_name): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Iterate through all instances + for inst in insts: + # Check if the instance name matches the target instance + if inst.getName() == instance_name: + # Return the placement status of the instance + return inst.isPlaced() + + # Return None if the instance is not found + return None + +# Call the function to check if 'FILLER_0_0_1' is placed +is_filler_placed = is_instance_placed('FILLER_0_0_1')",Check if the instance 'FILLER_0_0_1' placed or not +"def get_instance_children(instance_name): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Iterate through all instances + for inst in insts: + # Check if the instance name matches the target instance + if inst.getName() == instance_name: + # Get the children instances of the target instance + return inst.getChildren() + + # Return an empty list if the instance is not found or has no children + return [] + +# Call the function to get the children of 'FILLER_0_0_1' +filler_children = get_instance_children('FILLER_0_0_1')",Get the children of 'FILLER_0_0_1' instance +"def get_net_with_max_capacitance(block, timing, corner): + # Get all nets + nets = block.getNets() + # Initialize variables to track the net with the maximum capacitance + max_cap_net = None + max_cap = float('-inf') + # Iterate over nets + for net in nets: + # Get the total capacitance of the net + cap = timing.getNetCap(net, corner, timing.Max) + # Check if the capacitance of the current net is greater than the maximum capacitance found so far + if cap > max_cap: + # Update the maximum capacitance and the corresponding net + max_cap = cap + max_cap_net = net + # Return the name of the net with the maximum capacitance + return max_cap_net.getName() if max_cap_net else None + +# Example usage: +# Assuming `ord`, `timing`, and `corner` are initialized appropriately. +block = ord.get_db_block() +net_with_max_cap = get_net_with_max_capacitance(block, timing, corner)",Identify the nets with the highest capacitance +"def get_high_fanout_nets(): + # Get the design block + block = ord.get_db_block() + # Get all nets + nets = block.getNets() + # Define the fanout threshold + gt_fanout = 10 + # Initialize a list to store nets with fanout greater than the threshold + net_fanout = [] + # Iterate over nets + for net in nets: + # Get the name of the net + net_name = net.getName() + # Initialize a list to store output pins + output_pins = [] + # Get all ITerms associated with the net + net_ITerms = net.getITerms() + # Iterate over ITerms + for net_ITerm in net_ITerms: + # Check if the ITerm represents an input signal + if net_ITerm.isInputSignal(): + # Get the name of the pin + pin_name = design.getITermName(net_ITerm) + # Append the pin name to the list of output pins + output_pins.append(pin_name) + # Check if the number of output pins exceeds the fanout threshold + if len(output_pins) > gt_fanout: + # Append the net name and its fanout to the list + net_fanout.append([net_name, len(output_pins)]) + # Return the list of nets with fanout greater than the threshold + return net_fanout + +# Call the function +high_fanout_nets = get_high_fanout_nets()",Give me a list of nets with a fanout greater than 10 +"# Get the design block +block = ord.get_db_block() +# Get all nets +nets = block.getNets() +# Initialize variables to store maximum fanout and its corresponding net +max_fanout = 0 +# Lists to store net names and their corresponding fanouts +net_fanout_list = [] +net_name_list = [] +# Iterate over nets +for net in nets: + # Get the name of the net + net_name = net.getName() + # Initialize a list to store output pins + output_pins = [] + # Get all ITerms associated with the net + net_ITerms = net.getITerms() + # Iterate over ITerms + for net_ITerm in net_ITerms: + # Check if the ITerm represents an input signal + if (net_ITerm.isInputSignal()): + # Get the name of the pin + pin_name = design.getITermName(net_ITerm) + # Append the pin name to the list of output pins + output_pins.append(pin_name) + # Append the net name and its fanout to the respective lists + net_name_list.append(net_name) + net_fanout_list.append(len(output_pins)) +# Find the maximum fanout +max_fanout = max(net_fanout_list) +# Find the index of the net with the maximum fanout +max_fanout_index = net_fanout_list.index(max_fanout) +# Get the name of the net with the maximum fanout +max_fanout_net = net_name_list[max_fanout_index] +# Return the net with the maximum fanout +return max_fanout_net",Give me a list of nets with the maximum fanout +"def get_unique_master_cell_names(): + # Get the design block + block = ord.get_db_block() + # Get all instances + insts = block.getInsts() + # Initialize a list to store unique name of library cell types + masters_list = [] + # Iterate over instances + for inst in insts: + # Get the master associated with the instance + mast = inst.getMaster() + mast_name = mast.getName() + # Check if the library cell name is not already in the list + if mast_name not in masters_list: + # Append the library cell name to the list + masters_list.append(mast_name) + # Return the list of unique library cell names + return masters_list + +# Call the function +unique_masters = get_unique_master_cell_names()",List all the library cells used +"# Get the design block +block = ord.get_db_block() +# Get the total number of connections (nets) +total_connections = len(block.getNets())",Get the total number of connections (nets) +"def get_io_nets(): + # Get the design block + block = design.getBlock() + + # Get all nets + nets = block.getNets() + + # Initialize a list to store input/output nets + io_nets = [] + + # Iterate through all nets + for net in nets: + # Check if the net is an input/output net + if net.isIO(): + # If it's an input/output net, add it to the list + io_nets.append(net) + + # Return the list of input/output nets + return io_nets + +# Call the function +io_nets = get_io_nets()",get all the input output nets for a given block +"def get_output_pins(): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Initialize a list to store output pins + output_pins_list = [] + + # Iterate through all instances + for inst in insts: + # Get all input pins (ITerms) of the instance + pins = inst.getITerms() + # Iterate through all input pins + for pin in pins: + # Check if the pin is an output signal + if pin.isOutputSignal(): + # If it's an output signal, add it to the list + output_pins_list.append(pin) + + # Return the list of output pins + return output_pins_list + +# Call the function +output_pins = get_output_pins()",get a list of all the output pins +"def get_nets_for_instance(inst_name): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Initialize a variable to store the nets of the instance + nets = None + + # Iterate through all instances + for inst in insts: + # Check if the instance name matches the target instance + if inst.getName() == inst_name: + # Get all pins (ITerms) of the instance and extract their associated nets + nets = [pin.getNet() for pin in inst.getITerms()] + break + + # Return the nets of the instance + return nets + +# Call the function with the instance name '_411_' +instance_nets = get_nets_for_instance('_411_')",Give me all nets connecting to the instance '_411_' +"def get_instance_weights(): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Initialize a dictionary to store weights of instances + inst_weight_dict = {} + + # Iterate through all instances + for inst in insts: + # Get the instance name + name = inst.getName() + # Check if the instance name is not already in the dictionary + if name not in inst_weight_dict: + # If not, add the instance name and its weight to the dictionary + inst_weight_dict[name] = inst.getWeight() + + # Return the dictionary containing weights of instances + return inst_weight_dict + +# Call the function to get the instance weights +instance_weights = get_instance_weights()",get Weights of all the instances +"def get_instance_bbox_dimensions(inst_name='_411_'): + # Get the design block + block = design.getBlock() + + # Find the instance with the specified name + inst = block.findInst(inst_name) + + # Get the length and width of the Bounding Box of the instance + length = inst.getBBox().getLength() + width = inst.getBBox().getWidth() + + # Return the length and width + return (length, width) + +# Call the function to get the length and width of the instance '_411_' +bbox_dimensions = get_instance_bbox_dimensions('_411_')",get length and width of the bounding Box of the instance ''_411_' +"def get_source_types_of_instances_at_level(level=1): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Initialize a dictionary to store source types of instances at the specified level + inst_src_type_dict = {} + + # Iterate through all instances + for inst in insts: + # Check if the instance is at the specified level + if inst.getLevel() == level: + # Add the instance name and its source type to the dictionary + inst_src_type_dict[inst.getName()] = inst.getSourceType() + + # Return the dictionary containing source types of instances at the specified level + return inst_src_type_dict + +# Call the function to get source types of instances on level 1 +lvl1_inst_src_type = get_source_types_of_instances_at_level(1)",get source type of all the instance on level 1 +"# Set the placement status of the instance '_411_' to 'UNPLACED' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('_411_') + +# Set the placement status of the instance to 'UNPLACED' +inst.setPlacementStatus('UNPLACED') +",set the placement Status of the instance '_411_' to 'UNPLACED' +"# Get all the blockages + +# Get the design block +block = design.getBlock() + +# Return all blockages +blockages = block.getBlockages()",get all the blockages +"# Reset the tapcell in the design + +# Get the tapcell in the design +tapcell = design.getTapcell() + +# Reset the tapcell +tapcell.reset()",reset the tapcell in the design +"# Retrieve the capacitor-coupled segments + +# Get the design block +block = design.getBlock() + +# Return the capacitor-coupled segments +CCSegs = block.getCCSegs()",retrieve the capacitor-coupled segments +"def get_sites_of_rows(): + # Get the design block + block = design.getBlock() + + # Get all rows + rows = block.getRows() + + # Initialize a dictionary to store row names and their corresponding sites + row_site_dict = {} + + # Iterate through all rows + for row in rows: + # Add the row name and its site to the dictionary + row_site_dict[row.getName()] = row.getSite() + + # Return the dictionary containing row names and their sites + return row_site_dict + +# Call the function to get the sites of rows +row_sites = get_sites_of_rows()",get the sites of rows +"def get_row_site_dimensions(): + # Get the design block + block = design.getBlock() + + # Get all rows + rows = block.getRows() + + # Initialize a dictionary to store row names and their corresponding site dimensions + row_site_dict = {} + + # Iterate through all rows + for row in rows: + # Check if the row has a site + if row.getSite(): + # Add the row name and its site dimensions to the dictionary + row_site_dict[row.getName()] = [row.getSite().getHeight(), row.getSite().getWidth()] + + # Return the dictionary containing row names and their site dimensions + return row_site_dict + +# Call the function to get row site dimensions +row_site_dimensions = get_row_site_dimensions()",get the height and width of the sites of each row +"# Get the location, orientation, direction, and spacing of rows + +# Get the design block +block = design.getBlock() + +# Get all rows +rows = block.getRows() + +# Iterate through all rows +for i in range(len(rows)): + row = rows[i] + # Print row information + print(""Row"", i, row.getName()) + print(""Location:"", row.getOrigin()) + print(""Rotation:"", row.getOrient()) + print(""Direction:"", row.getDirection()) + print(""Block spacing:"", row.getSpacing()) +","get the location, rotation, direction and spacing of rows" +"def get_rows_with_hybrid_sites(): + # Get the design block + block = design.getBlock() + + # Get all rows + rows = block.getRows() + + # Initialize a list to store rows with hybrid sites + hybrid_row_site = [] + + # Iterate through all rows + for i in range(len(rows)): + row = rows[i] + site = row.getSite() + # Check if the site is hybrid + if site.isHybrid(): + # Append the row and its site to the list + hybrid_row_site.append((row, site)) + + # Return the list of rows with hybrid sites + return hybrid_row_site + +# Call the function to get rows with hybrid sites +hybrid_rows = get_rows_with_hybrid_sites()",get the rows with hybrid sites +"def get_instances_and_halos(): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Initialize a dictionary to store instances and their halos + inst_halos = {} + + # Iterate through all instances + for inst in insts: + # Add the instance name and its halo to the dictionary + inst_halos[inst.getName()] = inst.getHalo() + + # Return the dictionary containing instances and their halos + return inst_halos + +# Call the function to get instances and their halos +instances_and_halos = get_instances_and_halos()",get all the instances and there halos +"def get_instances_and_regions(): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Initialize a dictionary to store instances and their regions + inst_regions = {} + + # Iterate through all instances + for inst in insts: + # Add the instance name and its region to the dictionary + inst_regions[inst.getName()] = inst.getRegion() + + # Return the dictionary containing instances and their regions + return inst_regions + +# Call the function to get instances and their regions +instances_and_regions = get_instances_and_regions()",get the instances and their respective regions +"def get_and_set_do_not_touch(): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Initialize a dictionary to store do not touch instances + do_not_touch_elements = {} + + # Iterate through all instances + for inst in insts: + # Check if the instance is marked as do not touch + if inst.isDoNotTouch(): + # Add the instance to the dictionary + do_not_touch_elements[inst.getName()] = inst + else: + # Set do not touch to true for instances marked as false + inst.setDoNotTouch(True) + + # Return the dictionary containing do not touch instances + return do_not_touch_elements + +# Call the function to get and set ""do not touch"" instances +do_not_touch_instances = get_and_set_do_not_touch()",get the all the do not touch instance and set do not touch to true if false for instances +"def set_eco_create_and_destroy(inst_name): + # Get the design block + block = design.getBlock() + + # Find the instance by name + inst = block.findInst(inst_name) + + # Set EcoCreate and EcoDestroy to true + inst.setEcoCreate(True) + inst.setEcoDestroy(True) + + # Return the modified instance + return inst + +# Call the function for instance '_411_' +modified_instance = set_eco_create_and_destroy('_411_')",set the EcoCreate and EcoDestroy for instance '_411_' true +"# Mark the first output nets of the instances '_411_' and 'input1' + +# Get the design block +block = design.getBlock() + +# Find the instances '_411_' and 'input1' +inst1 = block.findInst('_411_') +inst2 = block.findInst('input1') + +# Mark the first output net of instance '_411_' +inst1.getFirstOutput().getNet().setMark(True) + +# Mark the first output net of instance 'input1' +inst2.getFirstOutput().getNet().setMark(True) +",mark the first output nets of the instances '_411_' and 'input1' +"def get_rc_disconnected_nets(): + # Get the design block + block = design.getBlock() + + # Get all the nets + nets = block.getNets() + + # Initialize a list to store RC disconnected nets + rc_disconnected_nets = [] + + # Iterate through all the nets + for net in nets: + # Check if the net is RC disconnected + if net.isRCDisconnected(): + # Add the net to the list + rc_disconnected_nets.append(net) + + # Return the list of RC disconnected nets + return rc_disconnected_nets + +# Call the function to get RC disconnected nets +disconnected_nets = get_rc_disconnected_nets()",Get the nets that are disconnected from RC network +"def get_placement_boundary_points(): + # Hard-coded parameters + block_name = '_411_' + + # Get the design block + block = design.getBlock() + + # Find the instance with the specified name + inst = block.findInst(block_name) + + # Get the library cell associated with the instance + master = inst.getMaster() + + # Get the placement bounding box of the library cell + placement_boundary = master.getPlacementBoundary() + + # Return the points of the placement bounding box + return placement_boundary.getPoints() + +# Call the function and store the result +boundary_points = get_placement_boundary_points() +print(boundary_points)",get the points of the placement bounding box of the library cell of the instance '_411_' +"# Clear user flags of instance '_411_' + +# Get the design block +block = design.getBlock() + +# Find the instance with name '_411_' +inst = block.findInst('_411_') + +# Clear user flags 1, 2, and 3 of the instance +inst.clearUserFlag1() +inst.clearUserFlag2() +inst.clearUserFlag3()",clear user flags of instance '_411_' +"def check_end_cap_status(): + # Hard-coded parameter + instance_name = '_411_' + + # Get the design block + block = design.getBlock() + + # Find the instance with the specified name + inst = block.findInst(instance_name) + + # Check if the instance is marked as an end cap + return inst.isEndCap() + +# Call the function and store the result +is_end_cap = check_end_cap_status() +print(is_end_cap)",Check if the instance '_411_' is marked as an end cap cell. +"def map_nets_to_wires(): + # Get the design block + block = design.getBlock() + + # Get all nets + nets = block.getNets() + + # Initialize a dictionary to store net-wire mappings + net_wire_dict = {} + + # Iterate through all nets + for net in nets: + # Get the name of the net + net_name = net.getName() + + # If the net name is not already in the dictionary, initialize an empty list + if net_name not in net_wire_dict: + net_wire_dict[net_name] = [] + + # Append the wire connected to the net to the list in the dictionary + net_wire_dict[net_name].append(net.getWire()) + + # Return the net-wire dictionary + return net_wire_dict + +# Call the function and store the result +net_wire_mapping = map_nets_to_wires() +print(net_wire_mapping)",map nets to the wires +"def get_master_cell_mterms(): + # Hard-coded parameter + instance_name = '_411_' + + # Get the design block + block = design.getBlock() + + # Find the instance with the specified name + inst = block.findInst(instance_name) + + # Get the MTerms of the master cell + mterms = inst.getMaster().getMTerms() + + # Return the MTerms + return mterms + +# Call the function and store the result +master_cell_mterms = get_master_cell_mterms() +print(master_cell_mterms)",get the MTerms of the master cell of the instance '_411_' +"def get_iotypes_of_pins(): + # Hard-coded parameter + instance_name = '_411_' + + # Get the design block + block = design.getBlock() + + # Find the instance with the specified name + inst = block.findInst(instance_name) + + # Get the MTerms of the master cell + mterms = inst.getMaster().getMTerms() + + # Initialize a dictionary to store IoTypes + iotype_dict = {} + + # Iterate through all MTerms + for term in mterms: + # Store the IoType of each term in the dictionary + iotype_dict[term.getName()] = term.getIoType() + + # Return the dictionary containing IoTypes + return iotype_dict + +# Call the function and store the result +pin_iotypes = get_iotypes_of_pins() +print(pin_iotypes)",get the IoType of the pins of the instance '_411_' +"def get_non_core_instances(): + # Get the design block + block = design.getBlock() + + # Get all instances in the block + insts = block.getInsts() + + # Initialize an empty list for non-core instances + inst_list = [] + + # Iterate through all instances + for inst in insts: + # If the instance's master cell is not a core, add it to the list + if not inst.getMaster().isCore(): + inst_list.append(inst) + + # Return the list of non-core instances + return inst_list + +# Call the function and store the result +non_core_instances = get_non_core_instances() +print(non_core_instances)",get the instances whose masters are not of type CORE +"def get_num_masks_per_layer(): + # Get the design block + block = design.getBlock() + + # Get the technology information + tech = block.getTech() + + # Get all layers + layers = tech.getLayers() + + # Initialize a dictionary to store the number of masks for each layer + num_masks = {} + + # Iterate through all layers + for layer in layers: + # Store the number of masks for each layer + num_masks[layer.getName()] = layer.getNumMasks() + + # Return the dictionary containing the number of masks for each layer + return num_masks + +# Call the function and store the result +layer_masks = get_num_masks_per_layer() +print(layer_masks)",get the number of masks of each layer +"def get_clearance_measure(): + # Get the design block + block = design.getBlock() + + # Get the technology information + tech = block.getTech() + + # Return the clearance measure + return tech.getClearanceMeasure() + +# Call the function and store the result +clearance_measure = get_clearance_measure() +print(clearance_measure)",get the measure system +"def check_use_min_spacing(): + # Get the design block + block = design.getBlock() + + # Get the technology information + tech = block.getTech() + + # Return whether UseMinSpacingObs is set in the technology + return tech.getUseMinSpacingObs() + +# Call the function and store the result +use_min_spacing = check_use_min_spacing() +print(use_min_spacing)",Check LEF USEMINSPACING is set or not +"def get_rect_only_layers(): + # Get the design block + block = design.getBlock() + + # Get the technology information + tech = block.getTech() + + # Get all layers + layers = tech.getLayers() + + # Initialize a list to store layers set as RectOnly + rect_layers = [] + + # Iterate through all layers + for layer in layers: + # Check if the layer is set as RectOnly + if layer.isRectOnly(): + # Append the rectangle-only layer to the list + rect_layers.append(layer) + + # Return the list of rectangle-only layers + return rect_layers + +# Call the function and store the result +rect_only_layers = get_rect_only_layers() +print(rect_only_layers)",Get the layers if they are set as isRectOnly +"def get_layer_aliases(): + # Get the design block + block = design.getBlock() + + # Get the technology information + tech = block.getTech() + + # Get all layers + layers = tech.getLayers() + + # Initialize a dictionary to store the Alias of each layer + layer_alias = {} + + # Iterate through all layers + for layer in layers: + # Store the Alias of each layer + layer_alias[layer.getName()] = layer.getAlias() + + # Return the dictionary containing the Alias of all layers + return layer_alias + +# Call the function and store the result +layer_aliases = get_layer_aliases() +print(layer_aliases)",Get the alias of all the layers +"def set_layer_aliases(): + # Get the design block + block = design.getBlock() + + # Get the technology information + tech = block.getTech() + + # Get all layers + layers = tech.getLayers() + + # Initialize a dictionary to store the Alias of each layer + layer_alias = {} + + # Iterate through all layers + for layer in layers: + # Construct the Alias using the layer index + alias = ""Layer "" + str(layer.getNumber()) + + # Set the Alias of the layer + layer.setAlias(alias) + + # Store the Alias of the layer in the dictionary + layer_alias[layer.getName()] = alias + + # Return the dictionary containing the updated Alias of layers + return layer_alias + +# Call the function and store the result +updated_layer_aliases = set_layer_aliases() +print(updated_layer_aliases)","Set the Alias of the layers by the name convention ''layer i"" where i is the index of the layer" +"# Get LEF version + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Return the LEF version of the technology +LefVersion = tech.getLefVersion()",Get LEF version +"# Get LEF version as a string + +# Get the design block +block = design.getBlock() + +# Get the technology information +tech = block.getTech() + +# Return the LEF version of the technology as a string +LefVersionString = tech.getLefVersionStr()",Get LEF version as a string +"def get_layer_resistances(): + # Get the design block + block = design.getBlock() + + # Get the technology information + tech = block.getTech() + + # Get all layers + layers = tech.getLayers() + + # Initialize a dictionary to store the resistance of each layer + layer_resistance = {} + + # Iterate through all layers + for layer in layers: + # Get the resistance of the layer and store it in the dictionary + layer_resistance[layer.getName()] = layer.getResistance() + + # Return the dictionary containing the resistance of each layer + return layer_resistance + +# Call the function and store the result +layer_resistances = get_layer_resistances() +print(layer_resistances)",Get the resistance of all the layers +"def get_layer_edge_capacitances(): + # Get the design block + block = design.getBlock() + + # Get the technology information + tech = block.getTech() + + # Get all layers + layers = tech.getLayers() + + # Initialize a dictionary to store the edge capacitance of each layer + layer_edge_capacitance = {} + + # Iterate through all layers + for layer in layers: + # Get the edge capacitance of the layer and store it in the dictionary + layer_edge_capacitance[layer.getName()] = layer.getEdgeCapacitance() + + # Return the dictionary containing the edge capacitance of each layer + return layer_edge_capacitance + +# Call the function and store the result +layer_edge_capacitances = get_layer_edge_capacitances()",get edge capacitance of all the layers +"def get_upper_lower_layers(layer_name): + # Get the design block + block = design.getBlock() + + # Get the technology information + tech = block.getTech() + + # Find the layer with the specified name + layer = tech.findLayer(layer_name) + + # Return the upper and lower layer of the specified layer + return (layer.getUpperLayer(), layer.getLowerLayer()) + +# Call the function and store the result with 'metal5' as the argument +upper_lower_layers = get_upper_lower_layers('metal5')",get the upper and lower layer of the layer 'metal5' +"def check_buffer_and_end_cap(): + # Hard-coded parameter + instance_name = '_411_' + + # Get the design block + block = design.getBlock() + + # Find the instance with the specified name + inst = block.findInst(instance_name) + + # Get the master of the instance + master = inst.getMaster() + + # Check if the design is buffer for the master and if the master is End Cap + return design.isBuffer(master) and master.isEndCap() + +# Call the function and store the result +buffer_and_end_cap_status = check_buffer_and_end_cap()",Check if instance '_411_' is buffer and if it is an End Cap cell +"def process_sequential_instances(): + target_inst_name = ""_411_"" + + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock(block_name) # Get the block + insts = block.getInsts() # Get all instances + + seq_insts = [] # List to store sequential instances + + # Iterate through instances + for inst in insts: + master = inst.getMaster() # Get the master of the instance + + # Check if the instance is '_411_' + if inst.getName() == target_inst_name: + # Make the master of instance '_411_' sequential + master.setSequential(True) + + # Check if the master is of type sequential + if master.isSequential(): + seq_insts.append(inst) + + # Return sequential instances + return seq_insts + +# Call the function +sequential_instances = process_sequential_instances()",Get the instances whose masters are of type sequential and make the master of instance '_411_' sequential +"def check_clocked_pins(inst_name): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Find the instance based on the provided name + inst = block.findInst(inst_name) + + # Get all pins of the instance + pins = inst.getITerms() + + clocked_ports = [] # List to store pins set as clocked + + # Check if any pin is set as clocked + for pin in pins: + if pin.isClocked(): + clocked_ports.append(pin) + + # Return clocked ports + return clocked_ports + +# Call the function with '_411_' as an argument +clocked_pins = check_clocked_pins('_411_')",Check if the instance '411' has any pin set as clocked +"# Display the location, orient, direction, and spacing of each row +block = design.getBlock() +rows = block.getRows() + +# Print table header +print(""{:<15} {:<15} {:<15} {:<15}"".format(""Row Name"", ""Location"", ""Direction"", ""Spacing"")) + +# Print data in a table format +for row in rows: + location = str(row.getOrigin()) + direction = str(row.getDirection()) + spacing = str(row.getSpacing()) + + print(""{:<15} {:<15} {:<15} {:<15}"".format(row.getName(), location, direction, spacing))","Display the location, orient, direction, and spacing of each row" +"def get_rows_and_output_pins_by_orient(orient): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + rows = block.getRows() # Get all rows + insts = block.getInsts() # Get all instances + + output_pins_dict = {} # Dictionary to store output pins + orient_rows = [] # List to store rows with the specified orientation + + # Iterate over rows to find those with the specified rotation orientation + for row in rows: + if row.getOrient() == orient: + orient_rows.append(row) + + # Iterate over instances to find their output pins + for inst in insts: + if inst.getFirstOutput(): + output_pins_dict[inst.getName()] = inst.getFirstOutput() + + # Return the rows with the specified orientation and output pins of instances + return (orient_rows, output_pins_dict) + +# Call the function with 'MX' as the argument +orient_rows, output_pins_dict = get_rows_and_output_pins_by_orient('MX')",Get the rows with 'MX' rotation and get the instances and the first output pin of all instances. +"def get_instances_halos_and_regions(): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + insts = block.getInsts() # Get all instances + + inst_halo_region_dict = {} # Dictionary to store instance names with their halos and regions + + # Iterate over instances to collect their halos and regions + for inst in insts: + inst_halo_region_dict[inst.getName()] = (inst.getHalo(), inst.getRegion()) + + # Return the dictionary with instance names as keys and a tuple of halo net and region as values + return inst_halo_region_dict + +# Call the function +inst_halo_region_dict = get_instances_halos_and_regions()",Get all the instances and their halos and regions in a dictionary with the instance name as the key and a tuple of halo net and region as value +"def set_do_not_touch_and_eco_create_destroy(inst_name): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + insts = block.getInsts() # Get all instances + + dnt_insts = [] # List to store 'Do Not Touch' instances + + # Iterate over instances to set 'Do Not Touch' for pads and collect 'Do Not Touch' instances + for inst in insts: + if inst.isPad(): + inst.setDoNotTouch(True) # Set Do Not Touch to True for pad instances + + if inst.isDoNotTouch(): + dnt_insts.append(inst) # Collect Do Not Touch instances + + # Set the EcoCreate and EcoDestroy for the specified instance to True + if inst.getName() == inst_name: + inst.setEcoCreate(True) + inst.setEcoDestroy(True) + + # Return the list of 'Do Not Touch' instances + return dnt_insts + +# Call the function with '_411_' as an argument +dnt_insts = set_do_not_touch_and_eco_create_destroy('_411_')",Get the all the do not touch instances and set do not touch to true for pad instances and set the EcoCreate and EcoDestroy for instance '_411_' to True. +"def mark_first_output_and_set_rc_disconnected(inst_name1, inst_name2): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Find the instances by names + inst1 = block.findInst(inst_name1) + inst2 = block.findInst(inst_name2) + + # Mark the first output nets of the instances and set RC disconnected true for the nets + inst1.getFirstOutput().getNet().setMark(True) + inst2.getFirstOutput().getNet().setMark(True) + + # Set RC disconnected true for the net of the first output of the first instance + inst1.getFirstOutput().getNet().setRCDisconnected(True) + + # Set RC disconnected true for the net of the first output of the second instance + inst2.getFirstOutput().getNet().setRCDisconnected(True) + +# Call the function with '_411_' and 'input1' as arguments +mark_first_output_and_set_rc_disconnected('_411_', 'input1')",Mark the first output nets of the instances '411' and 'input1' and set RC disconnected to True for the nets. +"def set_rc_disconnected_and_get_coordinates(inst_name): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Find the instance by name + inst = block.findInst(inst_name) + + # Set RC disconnected true for the nets of the instance + nets = [pin.getNet() for pin in inst.getITerms()] + for net in nets: + if net: + net.setRCDisconnected(True) + + # If the instance is '_411_', get the placement coordinates of its master cell + if inst.getName() == ""_411_"": + placement_boundary = inst.getMaster().getPlacementBoundary() + coordinates = { + ""ul"": placement_boundary.ul(), + ""ll"": placement_boundary.ll(), + ""lr"": placement_boundary.lr(), + ""ur"": placement_boundary.ur() + } + return coordinates + +# Call the function with 'input1' to set RC disconnected and get coordinates for '_411_' +coordinates = set_rc_disconnected_and_get_coordinates('input1')","Set the RC disconnected true for the nets of the instance 'input1' and get the upper-left, lower-left, lower-right, upper-right coordinates of the placement bounding box of the master cell of the instance '411'." +"def clear_user_flags_and_get_placement_points(inst_name): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Find the instance by name + inst = block.findInst(inst_name) + + # Get the placement bounding box of the master cell of the instance + placement_boundary = inst.getMaster().getPlacementBoundary() + + # Get the points of the placement bounding box + points = placement_boundary.getPoints() + + # Clear user flags 1, 2, and 3 of the instance + inst.clearUserFlag1() + inst.clearUserFlag2() + inst.clearUserFlag3() + + # Return the points of the placement bounding box + return points + +# Call the function with '_411_' to clear user flags and get placement points +placement_points = clear_user_flags_and_get_placement_points('_411_')",Get the points of the placement bounding box of the master cell of the instance '411' and clear user flags of instance '_411_'. +"def getMasterCellCoordinates(): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Get all instances + instances = block.getInsts() + + # Initialize a dictionary to store coordinates for each master cell + masterCoordinates = {} + + # Iterate through each instance + for instance in instances: + # Get the master cell of the instance + masterCell = instance.getMaster() + + # Get the placement bounding box of the master cell + placementBoundary = masterCell.getPlacementBoundary() + + # Check if the master cell name is not already in the masterCoordinates dictionary + if masterCell.getName() not in masterCoordinates: + # Store the center x, y coordinates, and minimum and maximum x, y coordinates in the dictionary + masterCoordinates[masterCell.getName()] = { + ""center"": [placementBoundary.xCenter(), placementBoundary.yCenter()], + ""min"": [placementBoundary.xMin(), placementBoundary.yMin()], + ""max"": [placementBoundary.xMax(), placementBoundary.yMax()] + } + + # Return the dictionary containing coordinates for each master cell + return masterCoordinates + +# Call the function to get the coordinates +masterCoordinates = getMasterCellCoordinates()","Get the center x, y and minimum and maximum x, y coordinates of the placement bounding box of the master cell of the all instance." +"def getLayerSpacingAndMasks(): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Get the technology information + tech = block.getTech() + + # Get all layers defined in the technology + layers = tech.getLayers() + + # Dictionary to store spacing and number of masks for each layer + spacingAndMask = {} + + # Iterate through each layer in the technology + for layer in layers: + # Store the spacing and number of masks for the current layer in the dictionary + spacingAndMask[layer.getName()] = { + ""spacing"": layer.getSpacing(), + ""masks"": layer.getNumMasks() + } + + # Return the dictionary containing spacing and number of masks for each layer + return spacingAndMask + +# Call the function to get the spacing and masks for all layers +layerSpacingAndMasks = getLayerSpacingAndMasks()",Get the spacing and the number of masks of each layer +"def getBlockagesAndRCDisconnectedNets(instanceName): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Get all blockages + blockages = block.getBlockages() + + # Get all nets + nets = block.getNets() + + # List to store RC disconnected nets + rcDisconnectedNets = [] + + # Iterate through each net + for net in nets: + # Check if the net is RC disconnected + if net.isRCDisconnected(): + # Append the net to the list of RC disconnected nets + rcDisconnectedNets.append(net) + + # Find the instance by name passed as argument + inst = block.findInst(instanceName) + + # Get the MTerms of the master cell of the specified instance + mterms = inst.getMaster().getMTerms() + + # Return a tuple containing blockages, RC disconnected nets, and MTerms + return (blockages, rcDisconnectedNets, mterms) + +# Call the function with 'rebuffer7' as the argument +blockagesRCDisconnectedNetsMterms = getBlockagesAndRCDisconnectedNets('rebuffer7')","Get all the blockages and get the nets that are RC disconnected, followed by getting the MTerms of the master cell of the instance 'rebuffer7'." +"def getHorizontalLayersAndTechInfo(): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Get the technology information + tech = block.getTech() + + # Get all layers defined in the technology + layers = tech.getLayers() + + # Define the direction for the layers + direction = 'HORIZONTAL' + + # List to store horizontal tech layers and their capacitance + horizontalLayers = [] + + # Iterate through each layer in the technology + for layer in layers: + # Check if the layer direction is HORIZONTAL + if layer.getDirection() == direction: + # Append the layer and its capacitance to the list of horizontal layers + horizontalLayers.append((layer, layer.getCapacitance())) + + # Retrieve the clearance measure + clearanceMeasure = tech.getClearanceMeasure() + + # Get the setting of UseMinSpacingObs in the tech file + minSpaceObs = tech.getUseMinSpacingObs() + + # Construct a dictionary containing horizontal layers, clearance measure, and minimum spacing obstacle + result = { + ""horizontalLayers"": horizontalLayers, + ""clearanceMeasure"": clearanceMeasure, + ""minSpaceObs"": minSpaceObs + } + + # Return the result dictionary + return result + +# Call the function to get horizontal layers and tech info +horizontalLayersTechInfo = getHorizontalLayersAndTechInfo()","Get the horizontal layers and their capacitance, then retrieve the clearance measure system and check if UseMinSpacingObs is set for this technology" +"def getRowAndNetInfo(): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Get rows and nets + rows = block.getRows() + nets = block.getNets() + + # Dictionary to store row information with row index as key + rowInfoDict = {} + + # Dictionary to store sites of rows with row name as key + rowSiteDict = {} + + # Dictionary to map nets to wires + netWireDict = {} + + # Iterate through each row + for i in range(len(rows)): + row = rows[i] + # Store row information in the rowInfoDict + rowInfoDict[i] = { + ""location"": row.getOrigin(), + ""rotation"": row.getOrient(), + ""direction"": row.getDirection(), + ""spacing"": row.getSpacing() + } + + # Store site of the row in the rowSiteDict + rowSiteDict[row.getName()] = row.getSite() + + # Iterate through each net + for net in nets: + # Map net name to its wire + netWireDict[net.getName()] = net.getWire() + + # Return a tuple containing row information, row sites, and net wire mappings + return (rowInfoDict, rowSiteDict, netWireDict) + +# Call the function to get row and net information +rowAndNetInfo = getRowAndNetInfo()","Get the location, rotation, direction, and spacing of rows as a dictionary with row index as key and get the sites of rows, followed by a dictionary with nets as keys and their wires as values." +"# Get the tapcell and reset it +tap_cell = design.getTapcell() +tap_cell.reset() + +# Get the current block of the design +block = design.getBlock() + +# Find the instance '_411_' +inst = block.findInst('_411_') + +# Set the placement status of the instance to 'UNPLACED' +inst.setPlacementStatus('UNPLACED') + +# Retrieve the capacitor-coupled segments +cc_segs = block.getCCSegs() + +# Return the coupling capacitance segments +return cc_segs","reset the tapcell, set the placement Status of the instance '_411_' to 'UNPLACED' and retrieve the capacitor-coupled segments of the bock" +"# Get the tapcell in the design and reset it +tap_cell = design.getTapcell() +tap_cell.reset() + +# Get the current block of the design +block = design.getBlock() + +# Return all blockages +Blockages = block.getBlockages()",Get all the blockages and reset the tapcell in the design. +"def markOutputNetsAndGetCoordinates(instanceName1, instanceName2): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Find the instances by names passed as arguments + inst1 = block.findInst(instanceName1) + inst2 = block.findInst(instanceName2) + + # Mark the first output nets of the instances + inst1.getFirstOutput().getNet().setMark(True) + inst2.getFirstOutput().getNet().setMark(True) + + # Get the placement bounding box of the master cell of the instance '_411_' + placementBoundary = inst1.getMaster().getPlacementBoundary() + + # Extract coordinates of the placement bounding box + coordinates = { + ""ul"": placementBoundary.ul(), + ""ll"": placementBoundary.ll(), + ""lr"": placementBoundary.lr(), + ""ur"": placementBoundary.ur() + } + + # Return the coordinates + return coordinates + +# Call the function with '_411_' and 'input1' as arguments +coordinates = markOutputNetsAndGetCoordinates('_411_', 'input1')","Mark the first output nets of the instances '_411_' and 'input1' and get the ul, ll, lr, ur coordinates of the placement bounding box of the master cell of the instance '_411_'." +"def getNonCoreMasterInstancesAndHorizontalLayers(direction): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Get all instances + insts = block.getInsts() + + # Get the technology information + tech = block.getTech() + + # Get all layers defined in the technology + layers = tech.getLayers() + + # List to store horizontal tech layers and their capacitance + horizontalLayers = [] + + # List to store instances whose masters are not of type CORE + nonCoreMasterInsts = [] + + # Iterate through each instance + for inst in insts: + # Check if the master cell of the instance is not of type CORE + if not inst.getMaster().isCore(): + # Append the instance to the list of non-core master instances + nonCoreMasterInsts.append(inst) + + # Iterate through each layer in the technology + for layer in layers: + # Check if the layer direction matches the passed direction + if layer.getDirection() == direction: + # Append the layer and its capacitance to the list of horizontal layers + horizontalLayers.append((layer, layer.getCapacitance())) + + # Reset the tapcell + tapCell = design.getTapcell() + tapCell.reset() + + # Return a tuple containing non-core master instances and horizontal layers + return (nonCoreMasterInsts, horizontalLayers) + +# Call the function with 'HORIZONTAL' as the argument +direction = 'HORIZONTAL' +nonCoreMasterInstsAndHorizontalLayers = getNonCoreMasterInstancesAndHorizontalLayers(direction)","Get the instances whose masters are not of type CORE and get the horizontal tech layers and their capacitance, followed by resetting the tapcell" +"def getRectOnlyLayerAliases(): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Get the technology information + tech = block.getTech() + + # Get all layers defined in the technology + layers = tech.getLayers() + + # Initialize a list to store layers that are set as RectOnly + rectLayersAlias = [] + + # Iterate through all layers + for layer in layers: + # Check if the layer is set as RectOnly + if layer.isRectOnly(): + # Append the rectangle-only layer aliases to the list + rectLayersAlias.append(layer.getAlias()) + + # Return the list of rectangle-only layers + return rectLayersAlias + +# Call the function to get the rectangle-only layer aliases +rectLayersAlias = getRectOnlyLayerAliases()",Get the layers that are set as RectOnly and get their alias. +"def getLayerResistanceAndEdgeCapacitance(): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Get the technology information + tech = block.getTech() + + # Get all layers defined in the technology + layers = tech.getLayers() + + # Initialize dictionaries to store resistance and edge capacitance of all layers + layerResistance = {} + layerEdgeCapacitance = {} + + # Iterate through each layer to retrieve resistance and edge capacitance + for layer in layers: + layerResistance[layer.getName()] = layer.getResistance() + layerEdgeCapacitance[layer.getName()] = layer.getEdgeCapacitance() + + # Combine resistance and edge capacitance dictionaries into a single result dictionary + result = { + ""edge_capacitance"": layerEdgeCapacitance, + ""layer_resistance"": layerResistance + } + + # Return the result dictionary + return result + +# Call the function to get the layer resistance and edge capacitance +layerDetails = getLayerResistanceAndEdgeCapacitance()",Get the resistance and edge capacitance of all the layers +"def handlePortAndGetLogicPorts(portName): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Find the port with the given name + port = block.findBTerm(portName) + + # Disconnect the port from the nets it is connected to + port.disconnect() + + # Set the port to special + port.setSpecial() + + # Get the logic ports + logicPorts = block.getLogicPorts() + + # Return the logic ports + return logicPorts + +# Call the function with 'req_val' as the argument to handle the port +logicPorts = handlePortAndGetLogicPorts('req_val')","Disconnect the port named 'req_val' from the nets it is connected to and set the port named 'req_val' to special, and return the logic ports" +"def getUpdatedNetsAndHorizontalLayers(): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Get all nets + nets = block.getNets() + + # Get the wire updated nets + updatedNets = block.getWireUpdatedNets(nets) + + # Get the technology information + tech = block.getTech() + + # Get all layers defined in the technology + layers = tech.getLayers() + + # List to store horizontal layers in the technology file + horizontalLayers = [] + + # Iterate through each layer in the technology + for layer in layers: + # Check if the layer direction is 'HORIZONTAL' + if layer.getDirection() == 'HORIZONTAL': + # Append the horizontal layer to the list + horizontalLayers.append(layer) + + # Create a dictionary containing updated nets and horizontal layers + result = { + ""nets"": updatedNets, + ""layers"": horizontalLayers + } + + # Return the result dictionary + return result + +# Call the function to get updated nets and horizontal layers +updatedNetsAndLayers = getUpdatedNetsAndHorizontalLayers()",Get all the wire_updated nets and get the horizontal layers +"def getLayerAndPortInfo(): + # Assuming `design.getBlock()` and similar functions are available in the environment + block = design.getBlock() # Get the block + + # Get the technology information + tech = block.getTech() + + # Get the count of layers + layerCount = tech.getLayerCount() + + # Get the Routing Layer Count + routingLayerCount = tech.getRoutingLayerCount() + + # Get the logic ports + logicPorts = block.getLogicPorts() + + # Create a dictionary containing layer count, routing layer count, and logic ports + result = { + ""layer_count"": layerCount, + ""routing_layer_count"": routingLayerCount, + ""logic_ports"": logicPorts + } + + # Return the result dictionary + return result + +# Call the function to get layer count, routing layer count, and logic ports +layerAndPortInfo = getLayerAndPortInfo()","Get the count of layers and get the routing layer count, along with the logic ports" +"# Get the current block of the design +block = design.getBlock() + +# Find the net with name ""req_msg[11]"" +net1 = block.findNet(""req_msg[11]"") +# Set the Capacitance Coupling Adjust Factor to 1 +net1.setCcAdjustFactor(1) + +# Find the net with name ""req_msg[12]"" +net2 = block.findNet(""req_msg[12]"") +# Set the Capacitance Coupling Calibration Factor to 2 +net2.setCcCalibFactor(2)","Set the Capacitance Coupling Adjust Factor of the net with name ""req_msg[11]"" to 1 and set the Capacitance Coupling Calib Factor of the net with name ""req_msg[12]"" to 2." +"def getClockPins(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get all the pins (which are also called Iterms in OpenROAD) + pins = block.getITerms() + + result = [] + + # Iterate through all the pins + for pin in pins: + # Check if the pin is in clock + if design.isInClock(pin.getInst()): + # Append the pin to the result + result.append(pin) + + # Return the list of clock pins + return result + +# Call the function to get the clock pins +clockPins = getClockPins()",Get all the Pins which are in clock net as a list. +"def getInstanceBBox(instance_name): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Find the instance with the given name + inst = block.findInst(instance_name) + + # Get the Bounding box of the instance + BBox = inst.getBBox() + + # Get the X Minimum of the Bounding Box of the instance + xmin = BBox.xMin() + + # Get the Y Minimum of the Bounding Box of the instance + ymin = BBox.yMin() + + # Get the X Maximum of the Bounding Box of the instance + xmax = BBox.xMax() + + # Get the Y Maximum of the Bounding Box of the instance + ymax = BBox.yMax() + + # Return the coordinates of the bounding box + return [[xmin, ymin], [xmax, ymax]] + +# Call the function with the instance name ""input1"" +instanceBBox = getInstanceBBox(""input1"")","Get the Bounding Box of an instance named ""input1"". Return a list of coordinates (Xmin, Ymin in one list and Xmax, Ymax in next list) " +"def getLibrariesAndCells(db): + # Get all the libraries in the database + libs = db.getLibs() + library_cells_dict = {} + + # Iterate through all the libraries + for lib in libs: + # Get the library cells of the library + master_cells = lib.getMasters() + cells = [] + + # Iterate through all the library cells + for master in master_cells: + # Append the library cell to the cells list + cells.append(master) + + # Add the library name and its cells to the dictionary + library_cells_dict[lib.getName()] = cells + + return library_cells_dict + +# Example of how to call the function +libraries_and_cells = getLibrariesAndCells(db)",Get all the library cells as a dictionary of list. Key of the dictionary is library name and the value is the list of all the library cells in the library file +"def getLibraryCellNames(db): + # Get all the libraries in the database + libs = db.getLibs() + libcell_name_list = [] + + # Iterate through all libraries + for lib in libs: + # Get all library cells in this library file + lib_masters = lib.getMasters() + + # Iterate through all library cells + for master in lib_masters: + # Get the name of the library cell + libcell_name = master.getName() + # Add the name to the list + libcell_name_list.append(libcell_name) + + return libcell_name_list + +# Example of how to call the function +library_cell_names = getLibraryCellNames(db)",Get the name of every liberty cell +"def get_instance_orientations(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + orientation = [] + + # Retrieve all instances present in the design block + insts = block.getInsts() + + # Iterate over each instance in the design block + for inst in insts: + # Append the name and orientation of the instance + orientation.append([inst.getName(), inst.getOrient()]) + + return orientation + +# Call the function and store the result +instance_orientations = get_instance_orientations()",Get the rotations of all instances as a list of lists +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input1' as mentioned in the prompt +inst = block.findInst('input1') +# Set the rotation of the instance as ""MX"" +inst.setOrient('MX')",Set the rotation of an instance 'input1' as 'MX' +"def get_output_nets(instance_name): + # Get the current block from the design + block = design.getBlock() + + # Retrieve the instance within the design + inst = block.findInst(instance_name) + + # Initialize a list to store the net of the output pin + output_nets = [] + + pins = inst.getITerms() + + # Iterate through each pin of the instance + for pin in pins: + # Check if the pin represents an output signal + if pin.isOutputSignal(): + # Retrieve the net associated with this output pin + net = pin.getNet() + # If net is not None then append it to the output_nets + if net: + output_nets.append(net) + + return output_nets + +# Call the function with the desired instance name +output_nets_for_instance = get_output_nets('output53')",get the nets of the output pins of the instance 'output53' +"def get_instance_bbox_dimensions(instance_name): + # Get the design block + block = design.getBlock() + + # Find the instance with the specified name + inst = block.findInst(instance_name) + + # Get the Bounding Box + bounding_box = inst.getBBox() + + # Get the DX and DY of the Bounding Box of the instance + return (bounding_box.getDX(), bounding_box.getDY()) + +# Call the function with the desired instance name +bbox_dimensions = get_instance_bbox_dimensions('_411_')",Get the width and height of the bounding box of instance '_411_' +"# Set the level of all 'AND2_X1' gate instances in the design to 1 + +# Get the design block +block = design.getBlock() + +# Get all instances +insts = block.getInsts() + +# Iterate through all instances +for inst in insts: + # Check if the instance's master name contains 'AND2_X1' + if inst.getMaster().getName() == 'AND2_X1': + # Set the level of the instance to 1 + inst.setLevel(1, False)",set the level of all 'AND2_X1' gate instance in the design to 1 +"def get_lower_left_corners(cell_type): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Initialize a dictionary to store the coordinates of the lower-left corner of the bounding box of the instances + inst_to_master_transform_offset = {} + + # Iterate through all instances + for inst in insts: + # Check if the name of the library cell type matches the provided cell_type + if inst.getMaster().getName() == cell_type: + # Add the instance name and the coordinates of the lower-left corner of the bounding box to the dictionary + inst_to_master_transform_offset[inst.getName()] = inst.getTransform().getOffset() + + return inst_to_master_transform_offset + +# Call the function with 'AND2_X1' as the argument +and2_x1_coordinates = get_lower_left_corners('AND2_X1')",Get the coordinates of the lower-left corner of the bounding box of the instances whose library cell type is 'AND2_X1' +"def get_lower_left_corners(cell_type): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Initialize a dictionary to store the coordinates of the lower-left corner of the bounding box of the instances + inst_to_master_transform_offset = {} + + # Iterate through all instances + for inst in insts: + # Check if the name of the library cell type matches the provided cell_type + if inst.getMaster().getName() == cell_type: + # Add the instance name and the coordinates of the lower-left corner of the bounding box to the dictionary + inst_to_master_transform_offset[inst.getName()] = inst.getOrigin() + + return inst_to_master_transform_offset + +# Call the function with 'AND2_X1' as the argument +and2_x1_coordinates = get_lower_left_corners('AND2_X1')",Get the coordinates of the lower-left corner of the bounding box of the instances whose library cell type is 'AND2_X1' +"def get_instance_orientations(cell_type): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Initialize a dictionary to store the orientation of instances + inst_to_master_transform_orient = {} + + # Iterate through all instances + for inst in insts: + # Check if the master name matches the provided cell_type + if inst.getMaster().getName() == cell_type: + # Add the instance name and its orientation to the dictionary + inst_to_master_transform_orient[inst.getName()] = inst.getTransform().getOrient() + + return inst_to_master_transform_orient + +# Call the function with 'AND2_X1' as the argument +and2_x1_orientations = get_instance_orientations('AND2_X1')",Retrieve the rotation of instances that have 'AND2_X1' as their library cell type. +"def get_instance_orientations(cell_type): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Initialize a dictionary to store the orientation of instances + inst_to_master_transform_orient = {} + + # Iterate through all instances + for inst in insts: + # Check if the master name matches the provided cell_type + if inst.getMaster().getName() == cell_type: + # Add the instance name and its orientation to the dictionary + inst_to_master_transform_orient[inst.getName()] = inst.getOrient() + + return inst_to_master_transform_orient + +# Call the function with 'AND2_X1' as the argument +and2_x1_orientations = get_instance_orientations('AND2_X1')",Retrieve the rotation of instances that have 'AND2_X1' as their library cell type. +"def get_instance_first_output_pins(): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Initialize a dictionary to store instances and their output pins + inst_outputs = {} + + # Iterate through all instances + for inst in insts: + # Add the instance name and its first output pin to the dictionary + inst_outputs[inst.getName()] = inst.getFirstOutput() + + return inst_outputs + +# Call the function to get the instance output pins +instance_output_pins = get_instance_first_output_pins()",Get the first output pin of an instance and map it to the instance names as the value in the dictionary. +"def set_user_flags_for_instance(instance_name): + # Get the design block + block = design.getBlock() + + # Find the instance with the specified name + inst = block.findInst(instance_name) + + # Set the user-defined flags 1 and 3 to true + inst.setUserFlag1() + inst.setUserFlag3() + + # Return the modified instance + return inst + +# Call the function with the desired instance name +modified_instance = set_user_flags_for_instance('_411_')",Set the user-defined flags 1and 3 to true for instance '_411_' and return the instance +"def get_placement_bounding_box_coordinates(instance_name): + # Get the design block + block = design.getBlock() + + # Find the instance with the specified name + inst = block.findInst(instance_name) + + # Get the master cell associated with the instance + master = inst.getMaster() + + # Get the placement bounding box of the master cell + placement_boundary = master.getPlacementBoundary() + + # Get the coordinates of the placement bounding box + # Upper Left placement bounding box + ul = placement_boundary.ul() + # Lower Left placement bounding box + ll = placement_boundary.ll() + # Lower Right placement bounding box + lr = placement_boundary.lr() + # Upper Right placement bounding box + ur = placement_boundary.ur() + + # Return the coordinates as a list + coordinates = [ul, ur, lr, ll] + return coordinates + +# Call the function with the desired instance name +placement_coordinates = get_placement_bounding_box_coordinates('_411_')","get the upper left, upper right, lower left, lower right coordinates of the placement bounding box of the master cell of the instance '_411_'" +"def check_instance_and_collect_hierarchical_instances(instance_name, target_master_name): + # Get the current block of the design + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Find the specified instance + inst = block.findInst(instance_name) + + # Check if the instance is of type ENDCAP or any of its subtypes + inst_is_endcap = inst.isEndCap() + + # Clear user-defined flags of the specified instance + inst.clearUserFlag1() + inst.clearUserFlag2() + inst.clearUserFlag3() + + # List to store instances having hierarchy and whose library cell name matches the target + inst_list = [] + + # Iterate through each instance + for inst in insts: + # Check if the instance is hierarchical, its library cell name matches the target, and is level 1 + if inst.isHierarchical() and inst.getMaster().getName() == target_master_name and inst.getLevel() == 1: + # Append the instance to the list + inst_list.append(inst) + + # Return a tuple containing the status of the specified instance and the list of hierarchical instances + return (inst_is_endcap, inst_list) + +# Call the function with the desired instance name and target master name +result = check_instance_and_collect_hierarchical_instances('_411_', 'AND2X_1')","Check if the instance '_411_' is type ENDCAP or any of its subtypes, and clear user-defined flags of instance '_411_', then get all the instances with hierarchicy and whose library cell is AND2X_1 and the instance is level 1." +"def get_instance_design_block(instance_name): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Find the instance with the specified name + inst = block.findInst(instance_name) + + # Return the corresponding design block of the instance + return inst.getBlock() + +# Call the function with the desired instance name +design_block = get_instance_design_block('input1')","Given the instance name 'input1', get the design block this instance belongs to." +"def get_db_units_per_micron(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Return the DB units per micron + return block.getDbUnitsPerMicron() + +# Call the function to get the DB units per micron +db_units_per_micron = get_db_units_per_micron()",Convert 1 um to units used in this technology in OpenROAD +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the DEF units of this technology +DefUnit = block.getDefUnits()",Get the DEF units of this technology. +"def get_db_rows_info(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get the DB rows + rows = block.getRows() + d = {} + + # Iterate through all the rows + for row in rows: + # Get the name of the DB row + name = row.getName() + # Get the spacing of the DB row + spacing = row.getSpacing() + # Store the row information in the dictionary + d[row] = [name, spacing] + + return d + +# Call the function to get the database rows information +db_rows_info = get_db_rows_info()","Get the rows with its name and spacing in a form of a dictionary. The key of the dictionary is the row object, the value is a list containing name and spacing of the row object" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Set the unit used in def file to 3000 as mentioned in the prompt +block.setDefUnits(3000)",Set the def units per micron to 3000 +"def get_module_names(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get the modules + modules = block.getModules() + module_names = [] + + # Iterate through all the modules + for module in modules: + # Append the names of the module + module_names.append(module.getName()) + + return module_names + +# Call the function to get the module names +module_names_list = get_module_names()",Get all the modules and return the names of modules as a list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input1' as mentioned in the prompt +inst = block.findInst(""inpu1"") +inst.setUserFlag1()","Set user-defined flag 1 to ture on the instance with name ""input1""" +"def get_net_cc_adjust_factors(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get all the nets + nets = block.getNets() + adjust_factors = [] + + # Iterate through all the nets + for net in nets: + # Append the capacitance coupling adjust factor of the net + adjust_factors.append(net.getCcAdjustFactor()) + + return adjust_factors + +# Call the function to get the capacitance coupling adjust factors +net_adjust_factors = get_net_cc_adjust_factors()",Get the capacitance coupling Adjust Factor of every net and return them as a list. +"def get_net_cc_adjust_orders(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get all the nets + nets = block.getNets() + adjust_orders = [] + + # Iterate through all the nets + for net in nets: + # Append the capacitance coupling adjust order of the net + adjust_orders.append(net.getCcAdjustOrder()) + + return adjust_orders + +# Call the function to get the capacitance coupling adjust orders +net_adjust_orders = get_net_cc_adjust_orders()",Get the capacitance coupling Adjust Order of every net and return them as a list. +"def get_net_tracks(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get all the nets + nets = block.getNets() + track_list = [] + + # Iterate through all the nets + for net in nets: + # Get the tracks of the net + tracks = net.getTracks() + # Append the tracks to the track list + track_list.append(tracks) + + return track_list + +# Call the function to get the tracks for all nets +net_tracks = get_net_tracks()",Get the tracks of every net as a list of lists. Each list in the output list should contain the tracks of respective net +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the instance with name 'input1' as mentioned in the prompt +inst = block.findInst(""input1"") +# Get the nets of the instance +nets = inst.getNets() +track_list = [] +# Iterate through all the nets +for net in nets: + # Get the tracks of the net + tracks = net.getTracks() + track_list.append(tracks)","Get the tracks of nets that are connected to instance with name ""input1"" as a list of list. Each list in the output list should contain the tracks of respective net" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the nets +nets = block.getNets() +types = [] +# Iterate through all the nets +for net in nets: + # Append the wire type of the net + types.append(net.getWireType())",Get the wire type of each net and return them as a list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the nets +nets = block.getNets() +termsCount = [] +# Iterate through all the nets +for net in nets: + # Get term counts of the net and append to the array + termsCount.append(net.getTermCount())",Get term count of every net and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +output = [] +insts = block.getInsts() +# Iterate through all the instances +for inst in insts: + # Get all the pins connected to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rise arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is greater than 0.5 second as mentioned in the prompt + if pin_rise_arr > 0.5: + output.append(pin)",Get all the pins which has the rising arrival time greater than 0.5 sec and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +insts = block.getInsts() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins connected to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the rising arrival time + pin_rise_arr = timing.getPinArrival(pin, timing.Rise) + # Check if the rising arrival time is less than or equal 0.5 second as mentioned in the prompt + if pin_rise_arr <= 0.5: + output.append(pin)",Get all the pins which has the rising arrival time less than or equal to 0.5 second and return them as list +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +insts = block.getInsts() +output = [] +# Iterate through all the instances +for inst in insts: + # Get all the pins connected to the instance + inst_ITerms = inst.getITerms() + # Iterate through the pins + for pin in inst_ITerms: + if design.isInSupply(pin): + continue + # Get the falling arrival time + pin_fall_arr = timing.getPinArrival(pin, timing.Fall) + # Check if the fall arrival time is greater than 0.8 second as mentioned in the prompt + if pin_fall_arr > 0.8: + # Append the pin to the output + output.append(pin)",Get all the pins which has Pin Fall Arrival Time greater than 0.8 sec and return them as list +"def check_if_any_wire_altered(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get all the nets + nets = block.getNets() + + # Iterate through all the nets + for net in nets: + # Check if the wire is replaced with a new wire + if net.isWireAltered(): + return True + + return False + +# Call the function to check if any wire is altered +is_wire_altered = check_if_any_wire_altered()",Check all the nets and check if any of its wires is replaced with a new wire. Return True if Altered and false otherwise +"def get_ports_and_nets(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get all the ports (which are known as BTerms in OpenROAD) + ports = block.getBTerms() + port_net_dict = {} + + # Iterate through all the ports + for port in ports: + # Append the name and net of the port in the dictionary + port_net_dict[port.getName()] = port.getNet() + + return port_net_dict + +# Call the function to get the ports and their associated nets +ports_and_nets = get_ports_and_nets()",Get all the net of ports and return a dictionay with port name as key and Net of the port as Value of the dictionary +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the ports (which are known of BTerms in OpenROAD) +ports = block.getBTerms() +d = {} +# Iterate through all the ports +for port in ports: + # Append the name and block pins objects of the port in the dictionary + d[port.getName()] = port.getBPins()",Get all the design block pins objects of ports and return a dictionay with port name as key and pins of the port as Value of the dictionary +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the design block ports (which are known of BTerms in OpenROAD) +ports = block.getBTerms() +placement_status_with_name = {} +# Iterate through all the ports +for port in ports: + # Get the name of the port + name = port.getName() + # Get the placement status of the port + status = port.getFirstPinPlacementStatus() + # Append the placement status and name of the port to the dictionary + placement_status_with_name[name] = status",Get the name of every design block port with the placement status of the first pin as a dictionary +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the ports (which are known of BTerms in OpenROAD) +ports = block.getBTerms() +d = {} +output = [] +# Iterate through all the ports +for port in ports: + # Append the port name and IO type of the port to the dictionary + d[port.getName()] = port.getIoType()",Get all the I/O types of ports and return a dictionay with port name as keys and IO Type of the port as values +"def get_port_bounding_box(port_name=""req_val""): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Find the port with the specified name + port = block.findBTerm(port_name) + + # Find the boundary box of the port + BBox = port.getBBox() + + # Get the coordinates of the bounding box + xmin = BBox.xMin() + ymin = BBox.yMin() + xmax = BBox.xMax() + ymax = BBox.yMax() + + return [[xmin, ymin], [xmax, ymax]] + +# Call the function to get the bounding box of the port ""req_val"" +bounding_box = get_port_bounding_box()","Get the Bounding Box of a port named ""req_val"". Return a list of coordinates (Xmin, Ymin in one list and Xmax, Ymax in another list) " +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""req_val"" +port = block.findBTerm('req_val') +# Set SPECIAL attribute to the port +port.setSpecial()",Set SPECIAL attribute port named 'req_val' +"def is_port_special(port_name): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Find the port with the specified name + port = block.findBTerm(port_name) + + # Return whether the port has the SPECIAL attribute + return port.isSpecial() + +# Call the function with the argument ""req_val"" +port_special_status = is_port_special('req_val')",Check if the port named 'req_val' has SPECIAL attribute +"def get_wire_updated_nets(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get all the nets + nets = block.getNets() + + # Get and report wire-updated nets + wire_updated_nets = block.getWireUpdatedNets(nets) + + return wire_updated_nets + +# Call the function to get wire-updated nets +updated_nets = get_wire_updated_nets()",Get the of nets for any wire changes and report the statistics of the nets with changed wires. +"def get_technology_layers(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get the technology information + tech = block.getTech() + + # Return the technology layers + return tech.getLayers() + +# Call the function to get the technology layers +technology_layers = get_technology_layers()",Get the technolgy layers. The layers are ordered from the bottom mask number to the top mask number. +"def get_layer_count(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get the technology information + tech = block.getTech() + + # Return the number of layers in this technology + return tech.getLayerCount() + +# Call the function to get the layer count +layer_count = get_layer_count()",Get the number of layers in this technology. +"def get_routing_layer_count(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get the technology information + tech = block.getTech() + + # Return the number of routing layers in this technology + return tech.getRoutingLayerCount() + +# Call the function to get the routing layer count +routing_layer_count = get_routing_layer_count()",Get the number of routing-layers in this technology. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Return the number of vias in this technolgy. +viaCount = tech.getViaCount()",Get the number of vias in this technolgy. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Return the via generate rules in this technolgy +viaGenerateRule = tech.getViaGenerateRules()",Get the via generate rules in this technolgy. +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Get the technolgy vias. This includes non-default-rule-vias. +vias = tech.getVias()",Get the technolgy vias +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Get LEF CLEARANCEMEASURE +clearanceMeasure = tech.getClearanceMeasure()",Get LEF CLEARANCEMEASURE +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Return MANUFACTURINGGRID +# NOTE: Assumes conversion to internal DB units, +# NOT microns or LEF/DEF units +ManufacturingGrid = tech.getManufacturingGrid()",Get MANUFACTURINGGRID +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the net with name ""req_msg[11]"" +net = block.findNet(""req_msg[11]"") +# Set the capacitance coupling adjust factor of the net to 1 +net.setCcAdjustFactor(1)","Set the capacitance coupling adjust factor of the net with name ""req_msg[11]"" to 1" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the net with name ""req_msg[11]"" +net = block.findNet(""req_msg[11]"") +# Set the capacitance coupling calibration factor of the net to 2 +net.setCcCalibFactor(2)","Set the capacitance coupling calibration factor of the net with name ""req_msg[11]"" to 2" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get all the nets +nets = block.getNets() +output = {} +# Iterate through all the nets +for net in nets: + # Append the net name and capacitance coupling match ratio against the net to a dictionary + output[net.getName()] = net.getCcMatchRatio()",Get the capacitance coupling match ratio against this nets with the name of the net. Return a dictionary with key being the name of the net and value of the dictionary is the capacitance coupling match ratio against the net +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Iterate through the net names ""req_msg[13] and ""clk"" as mentioned in the prompt +for net_name in [""req_msg[13]"", ""clk""]: + # Find the net with net name as parameter + net = block.findNet(net_name) + # Set the coupling capacitance match ratio against the net to 1 + net.setCcMatchRatio(1)","Set the coupling capacitance match ratio against the net with name ""req_msg[13]"" and ""clk"" to 1" +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Get the technology layers +layers = tech.getLayers() +output = [] +# Iterate through all the layers +for layer in layers: + # Get the names of the technology layers + output.append(layer.getName())",Get the names of the technology layers +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Get all the tehnology layers +layers = tech.getLayers() +output = {} +# Iterate through all the technology layers +for layer in layers: + # Append the layer name and AREA parameter to the dictionary + output[layer.getName()] = layer.getArea()",Get the AREA parameter of the technology layers with their name. Return a dictionary with key as the layer name and value as the AREA parameter +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Get all the technology layers +layers = tech.getLayers() +output = {} +# Iterate through all the layers +for layer in layers: + # Append the layer name and layer direction to the dictionary + output[layer.getName()] = layer.getDirection()",Get the directions of the technology layers with their name. Return a dictionary with key as the layer name and value as the layer direction +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Get the technology information +tech = block.getTech() +# Find the layer with name 'metal8' +layer = tech.findLayer('metal8') +# Return the routing layer corner spacing rule +techLayerCornerSpacingRules = layer.getTechLayerCornerSpacingRules()",Get the routing layer corner spacing rules of technology layer with name 'metal8' +"# Get the design block +block = ord.get_db_block() +# Find the instance named ""split30"" +split30 = block.findInst(""split30"")",Find instance split30 +"def get_instance_names(): + # Get the design block + block = ord.get_db_block() + + # Get instances + insts = block.getInsts() + + # Initialize a list to store instance names + inst_names = [] + + # Iterate over instances and append their names to the list + for inst in insts: + inst_names.append(inst.getName()) + + return inst_names + +# Call the function +instance_names = get_instance_names()",List all the instances name +"# Define the function to select nets +def get_selected_nets(): + # Get the design block + block = design.getBlock() + + # Get all nets + nets = block.getNets() + + # List to store selected nets + selected_nets = [] + + # Iterate through each net + for net in nets: + # Check if the net is selected + if net.isSelect(): + # Append the net to the list + selected_nets.append(net) + + return selected_nets + +# Call the function +selected_nets = get_selected_nets()",Get the selected nets +"def get_cut_class_rules(layer_name='metal8'): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + + # Get the technology information + tech = block.getTech() + + # Find the technology layer with the given name + layer = tech.findLayer(layer_name) + + # Return the cut layer class rule + return layer.getTechLayerCutClassRules() + +# Calling the function with the default 'metal8' layer +cut_class_rules = get_cut_class_rules()",Get the cut layer class rule of layer with name 'metal8' +"def set_wire_type_as_routed(design, nets): + # Get the design block + block = design.getBlock() + + # Iterate through each net name + for name in nets: + # Find the net object by name + net = block.findNet(name) + + # Set the wire type of the net as ROUTED + net.setWireType('ROUTED') + +# List of net names to set wire type as ROUTED +nets = [ + ""_000_"", + ""_001_"", + ""_002_"", + ""_003_"", + ""_004_"", + ""_005_"", + ""_006_"", + ""_007_"", + ""_008_"", + ""_009_"", + ""_010_"" +] + +# Assuming `design` is an object that's already available +set_wire_type_as_routed(design, nets)","Set the following nets wire type to ROUTED: _000_, _001_, _002_, _003_, _004_, _005_, _006_, _007_, _008_, _009_, _010_ +" +"def get_port_signals(block=None): + if block is None: + block = ord.get_db_block() # Default to current database block if no block is provided. + + ports = block.getBTerms() + port_signals = {} + + for port in ports: + port_signals[port.getName()] = port.getSigType() + + return port_signals + +# Call the function +port_signals = get_port_signals() +print(port_signals)",Get the name of every block port with its signal type as a dictionary +"def check_output_pins_without_nets(): + # Get the design block + block = ord.get_db_block() + # Get all instances + insts = block.getInsts() + # Initialize a list to store output pins without nets + outputPinWithoutNet = [] + + # Iterate over instances + for inst in insts: + # Get all pins of the instance + pins = inst.getITerms() + # Iterate over pins + for pin in pins: + # Check if the pin is an output signal + if pin.isOutputSignal(): + # Get the net connected to the pin + nets = pin.getNet() + # Check if the pin has no net connected + if nets is None: + # Append the pin to the list + outputPinWithoutNet.append(pin) + + # Check if there are no output pins without nets + return len(outputPinWithoutNet) == 0 + +# Call the function +result = check_output_pins_without_nets() +print(""No output pins without nets:"" if result else ""Output pins without nets found."")",Check if all the output pins of all instances have a valid net connection +"def get_instance_locations(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + # Retrieve all instances present in the design block + insts = block.getInsts() + loc = [] + for inst in insts: + # Append the location of the instance to the list + loc.append(inst.getLocation()) + return loc + +# Call the function +locations = get_instance_locations()",Give me the location of every instance in the design and return it in a list called loc. +"def get_placement_status(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + # Retrieve all instances present in the design block + insts = block.getInsts() + placement_status_with_name = {} + # Iterate over each instance in the design block + for inst in insts: + # Get the name of the particular instance + name = inst.getName() + # Get the placement status of the instance + status = inst.getPlacementStatus() + # Add the respective instance name and its status + placement_status_with_name[name] = status + return placement_status_with_name + +# Call the function +placement_status = get_placement_status()",Get the name of every instance with its placement status as a dictionary +"def get_placed_instances(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + # Retrieve all instances present in the design block + insts = block.getInsts() + placed_instances = [] + # Iterate over each instance in the design block + for inst in insts: + # Check if this instance is placed + if inst.isPlaced() == True: + # Append the instance name to the array + placed_instances.append(inst.getName()) + return placed_instances + +# Call the function +placed_instances_list = get_placed_instances()",Get the names of every instance which are placed and return a list of names +"def get_net_cap_res_coupling(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + # Retrieve all nets present in the design block + nets = block.getNets() + result = [] + # Iterate over each net in the design block + for net in nets: + # Check the signal type of the net + if net.getSigType() != 'POWER' and net.getSigType() != 'GROUND': + # Get the name of the net + net_name = net.getName() + # Get the total Capacitance of the net + net_cap = net.getTotalCapacitance() + # Get the total resistance of the net + net_res = net.getTotalResistance() + # Get the total coupling capacitance of the net + net_coupling = net.getTotalCouplingCap() + # Append the net name, net capacitance, net resistance, and net coupling + result.append([net_name, net_cap, net_res, net_coupling]) + return result + +# Call the function +net_info = get_net_cap_res_coupling()","Get the total capacitance, total resistance, Coupling Capacitance of all the nets except the nets that are connected to Ground and Power External Power Supply. Get them as list of lists, in which each list contains the net name, net capacitance, net resistance and net coupling." +"def get_nets_with_no_pins(): + # Get the current design block from the OpenROAD database + block = ord.get_db_block() + # Retrieve all nets present in the design block + nets = block.getNets() + result = [] + # Iterate over each net in the design block + for net in nets: + # Get the Pins of the net + pins = net.getITerms() + # Check if the length of the number of pins of the net is Zero + if len(pins) == 0: + # Append the net to the result + result.append(net) + return result + +# Call the function +nets_with_no_pins = get_nets_with_no_pins()",Get all the nets which are not connected to any pins and return them as list. +"def flip_nand2_instances(cell_type): + # Define the flipping function + def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270"" + + # Get the design block + block = design.getBlock() + + # Get all instances in the block + insts = block.getInsts() + + # Iterate through all instances in the block + for inst in insts: + # Check if the library cell type matches the provided cell_type + if inst.getMaster().getName() == cell_type: + # Horizontally flip the rotation of the instance + orient = inst.getTransform().getOrient() + orient = flipX(orient) + inst.setOrient(orient) + +# Call the function with the hard-coded 'NAND2_X1' cell type +flip_nand2_instances('NAND2_X1')",Horizontally flip the rotation of the instances whose library cell types are 'NAND2_X1' +"def flip_and2_instances(cell_type): + # Define the flipping function + def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90"" + + # Get the design block + block = design.getBlock() + + # Get all instances in the block + insts = block.getInsts() + + # Iterate through all instances in the block + for inst in insts: + # Check if the library cell type matches the provided cell_type + if inst.getMaster().getName() == cell_type: + # Vertically flip the rotation of the instance + orient = inst.getOrient() + orient = flipY(orient) + inst.setOrient(orient) + +# Call the function with the hard-coded 'AND2_X1' cell type +flip_and2_instances('AND2_X1')",Vertically flip the rotation of the instances whose library cell types are 'AND2_X1' +"# Get the current design block from the OpenROAD database +block = ord.get_db_block() +# Find the port with name ""req_val"" +port = block.findBTerm('req_val') +# Find the net with name ""req_msg[17]"" +net = block.findNet('req_msg[17]') +# Connect the port and the net +port.connect(net)",Connect the port named 'req_val' and net named 'req_msg[17]' +"def swap_instance_master(instance_name, new_master_name): + # Get the design block + block = ord.get_db_block() + # Get the database + db = ord.get_db() + # Find the instance by its name + inst = block.findInst(instance_name) + # Check if the required library cell exists in the database + if db.findMaster(new_master_name) is not None: + # Find the required library cell + new_mast = db.findMaster(new_master_name) + # Swap the instance's library cell with the new library cell + inst.swapMaster(new_mast) + return True + else: + return False + +# Call the function with hard-coded arguments +instance_swapped = swap_instance_master(""split30"", ""BUF_X4"")",Upsize the instance split30 to BUF_X4 +"def invert_transform_and_get_offset(instance_names, master_cell_name): + # Get the design block + block = design.getBlock() + + # Get all instances + insts = block.getInsts() + + # Dictionary to store offset of transforms for specific instances + inst_transform_offset = {} + + # Iterate through instances + for inst in insts: + # Check if the master cell name matches the provided master_cell_name + if inst.getMaster().getName() == master_cell_name: + # Get transform and invert + transform = inst.getTransform() + transform.invert() + + # Check if instance name is in the provided instance_names list + if inst.getName() in instance_names: + # Get transform and store offset + transform = inst.getTransform() + inst_transform_offset[inst.getName()] = transform.getOffset() + + return inst_transform_offset + +# Call the function with hard-coded arguments +instance_offsets = invert_transform_and_get_offset(['_411_', 'input1'], 'NAND2_X1')","Invert the location and rotation of instances whose library cells are 'NAND2_X1'. Then, retrieve the location of the instances '_411_' and 'input1' and return them as a dictionary with the instance names as keys and their respective location as values." +"# Set the rotation of the instance '_411_' to 'MX' + +# Get the design block +block = design.getBlock() + +# Find the instance with the specified name +inst = block.findInst('_411_') + +# Set the rotation of the instance to 'MX' +transform = inst.getTransform() +transform.setOrient('MX') +inst.setTransform(transform)",Set the rotation of the instance '_411_' to 'MX' +"def get_input_pins_for_instance(instance_name): + # Get the design block + block = design.getBlock() + + # Find the instance by name + inst = block.findInst(instance_name) + + # Initialize a list to store the input pins of the instance + input_pins = [] + + # Obtain all pins associated with this instance + pins = inst.getITerms() + + # Iterate through each pin of the instance + for pin in pins: + # Check if the pin represents an input signal + if pin.isInputSignal() and pin: + # Append the input pin to the list of input pins + input_pins.append(pin) + + return input_pins + +# Call the function with the hard-coded 'output53' instance name +input_pins_for_output53 = get_input_pins_for_instance('output53')",get the input pins of the instance 'output53' +"# Get the design block +block = ord.get_db_block() +# Find the instance ""_split30_"" +inst = block.findInst(""_split30_"") +# Set the instance as don't touch type +inst.setDoNotTouch(False)","Reset the instance ""_split30_"" as don't touch type" \ No newline at end of file diff --git a/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/DB_Dataset.xlsx b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/DB_Dataset.xlsx new file mode 100644 index 0000000..c3d737e Binary files /dev/null and b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/DB_Dataset.xlsx differ diff --git a/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/Flow_Dataset.csv b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/Flow_Dataset.csv new file mode 100644 index 0000000..60daaa9 --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/Flow_Dataset.csv @@ -0,0 +1,31931 @@ +code,prompt +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the standard cells and the macros. Place each macro at least 5 um away from each other, and set a halo region around each macro as 5 um. Set the number of iteration of the global router as 30. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk_i"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. During detailed placement, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a gate-level netlist with a clock port called ""clk"", read the tech file, lef files, and library files, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the standard cells and the macros. Place each macro at least 5 um away from each other, and set a halo region around each macro as 5 um. Set the number of iteration of the global router as 30. During detailed placement, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 30 um,15 um, and the top-right corner as 55 um,35 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 um,15 um, and the top-right corner as 55 um,35 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 50% +floorplan_utilization = 50 +# Set the aspect ratio of the design (height/width) as 1 +floorplan_aspect_ratio = 1 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 50%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 10 +floorplan_core_spacing = [design.micronToDBU(10) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 10 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the standard cells and the macros. Place each macro at least 5 um away from each other, and set a halo region around each macro as 5 um. Set the number of iteration of the global router as 10. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the standard cells and the macros. Place each macro at least 5 um away from each other, and set a halo region around each macro as 5 um. Set the number of iteration of the global router as 10. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 30 um,15 um, and the top-right corner as 55 um,35 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 30 um,15 um, and the top-right corner as 55 um,35 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(15, 30, 10, 40) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 15 um,10 um, and the top-right corner as 30 um,40 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After placement, do CTS and use BUF_X3 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 40 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(40), design.micronToDBU(60)) +core_area = odb.Rect(design.micronToDBU(10), design.micronToDBU(10), + design.micronToDBU(30), design.micronToDBU(50)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 40,60. Set the bottom-left corner of the core's bounding box as 10,10 and the top-right corner as 30,50. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 20 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform CTS with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 50 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(70), design.micronToDBU(70)) +core_area = odb.Rect(design.micronToDBU(6), design.micronToDBU(6), + design.micronToDBU(64), design.micronToDBU(64)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 20 times +gpl.setInitialPlaceMaxIter(20) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_spacing = [design.micronToDBU(4), design.micronToDBU(4)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 50 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 70,70. Set the bottom-left corner of the core's bounding box as 6,6 and the top-right corner as 64,64. After floorplanning, place the standard cells and the macros. Place each macro at least 5 um away from each other, and set a halo region around each macro as 5 um. Set the number of iteration of the global router as 20. During detailed placement, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 4 and 4 um, and for the power rings on M8, set the width and spacing to 4 and 4 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +core_area = odb.Rect(design.micronToDBU(8), design.micronToDBU(8), + design.micronToDBU(52), design.micronToDBU(42)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a placed design with a clk port called ""clk_i"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,50. Set the bottom-left corner of the core's bounding box as 8,8 and the top-right corner as 52,42. After floorplanning, place the macros and the standard cells. Make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M6. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 45% +floorplan_utilization = 45 +# Set the aspect ratio of the design (height/width) as 1.5 +floorplan_aspect_ratio = 1.5 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(32, 55, 32, 60) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M2"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk_i"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 45%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 32 um,32 um, and the top-right corner as 55 um,60 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform clock tree synthesis with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M6. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile make sure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 14 +floorplan_core_spacing = [design.micronToDBU(14) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 14 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as1. After the placement stage, perform CTS with using BUF_X3 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.0435 and 0.0817, respectively. Then construct PDN with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 2 um and set the spacing to 2 um. And if there are parallel grids, set the pitch of the via between two grids to 2 um. Last, set the offset to 0 for all cases. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 60% +floorplan_utilization = 60 +# Set the aspect ratio of the design (height/width) as 1.3 +floorplan_aspect_ratio = 1.3 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_spacing = [design.micronToDBU(1.5), design.micronToDBU(1.5)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +macro_ring_connect_to_pad_layers = [l for l in design.getTech().getDB().getTech().getLayers() if l.getType() == ""ROUTING""] +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = macro_ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""PDN.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 60%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 um,15 um, and the top-right corner as 55 um,35 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. During detailed placement, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After placement, do CTS and use BUF_X2 as clock buffers, then set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power rings and power grids for macros on M5 and M6 , set the width and spacing of both the M5 and the M6 grids to 1.2 um, and set the pitch to 6 um. For the power ring on M5 and M6, set the width to 1.5 um and set the spacing to 1.5 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After PDN construction, get the IR drop analysis result on M1 layer and dump the def file and name it ""PDN.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 5 +floorplan_core_spacing = [design.micronToDBU(5) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 5 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, dump the def file and name it ""placement.def"". " +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In the end, dump the def file and name it ""final.def""." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 40% +floorplan_utilization = 40 +# Set the aspect ratio of the design (height/width) as 0.66 +floorplan_aspect_ratio = 0.66 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +design.writeDef(""floorplan_place_pins.def"") + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +design.writeDef(""global_placement.def"") + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(18, 43, 12, 42) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +design.writeDef(""macro_placement.def"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""detailed_placement.def"") + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""cts.def"") + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +design.writeDef(""filler_placement.def"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +design.writeDef(""PDN.def"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +# Report Power + +design.evalTclString(""report_power"") + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +design.writeDef(""final.def"") + +","Given a synthesized netlist with a clock port named ""clk"", read the library and set the clock period as 20 ns. Then, perform floorplanning and set the target utilization as 40%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 18 um,12 um, and the top-right corner as 43 um,42 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. After constructing power grids, perform IR drop analysis on M1 nodes of the power grids. And report the switching, leakage, internal, and total power of the design. In the routing stage, route the design from M1 to M7. In each stage, dump the def file and name it according to the stage." +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 40 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0.5) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a verilog-described netlist with a clk port called ""clk"", read the tech files and cell library information and set the clock period as 40 ns. Then, perform floorplanning and set the target utilization as 35%, and set the spacing between core and die as 12 microns. After that, place the pins on M8 and M9. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 30 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0.5 um, and the y-axis as0.5. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 5 and 5 um, and for the power rings on M8, set the width and spacing to 5 and 5 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"# Disconnect the nets of the instance 'input1' from the RC network + +# Get the design block +block = design.getBlock() + +# Find the instance with name 'input1' +inst = block.findInst('input1') + +# Get the pins of the instance +pins = inst.getITerms() + +# Iterate through the pins +for pin in pins: + # Get the net connected to the pin + net = pin.getNet() + if net: + # Set the RC disconnected flag for the net + net.setRCDisconnected(True) +",Disconnect the nets of the instance 'input1' from the RC network +"from openroad import Design, Tech + +tech = Tech() +# Make sure to read all required files +design = Design(tech) +# Get PDNGen module +pdngen_obj = design.getPdnGen() +# Find the VDD net +VSS_net = design.getBlock().findNet(""VSS"") +# Rip up the VSS grids +pdn_obj.ripUp(VSS_net)",Rip up the VSS grids +"from openroad import Tech, Design + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(118) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M6 and M7 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M6"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M7"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode)",How can I place I/O pins of the design block on M6 and M7 layers? +"from openroad import Tech, Design + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset()",How can I perform global placement? +"from openroad import Tech, Design + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Global Placement +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 30 times +gpl.setInitialPlaceMaxIter(30) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement +# In OpenROAD, global placement should be performed before macro placement +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Place the macros using the entire core area + core = design.getBlock().getCoreArea() + units = design.getBlock().getDbUnitsPerMicron() + core_lx = core.xMin() / units + core_ly = core.yMin() / units + core_ux = core.xMax() / units + core_uy = core.yMax() / units + design.getMacroPlacer().setFenceRegion(core_lx, core_ly, core_ux, core_uy) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl()",Place the macros onto the design block +"from openroad import Tech, Design + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False)",Perform detailed placement in OpenROAD +"from openroad import Tech, Design +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Add Filler Cells +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix)",Add filler cells on the design block +"from openroad import Tech, Design +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power distribution network + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes()",Show me how I can construct power distribution network in OpenROAD +"from openroad import Tech, Design +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_spacing = [design.micronToDBU(5), design.micronToDBU(5)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(2) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for core +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top_pdn"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top_pdn"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +# Create power delivery network for macros +# Set the width of the PDN ring for macros and the spacing between VDD and VSS rings for macros +macro_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +macro_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +macro_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"" +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""Macro_core_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""Macro_core_grid_"" + str(i)) + for g in grid: + pdngen.makeRing(grid = g, layer0 = m5, width0 = macro_ring_width[0], spacing0 = macro_ring_spacing[0], + layer1 = m6, width1 = macro_ring_width[0], spacing1 = macro_ring_spacing[0], + starts_with = pdn.GRID, offset = macro_ring_core_offset, pad_offset = ring_pad_offset, extend = False, + pad_pin_layers = macro_ring_connect_to_pad_layers, nets = []) + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes()",Show me how I can build power distribution network if my design has macros +"from openroad import Tech, Design +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1""))",How can I perform IR drop analysis on the M1 layer where the pins are located? +"from openroad import Tech, Design +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +design.evalTclString(""report_power"")","Report the switching power, internal power and leakage power of the design" +"from openroad import Tech, Design +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Global Routing +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M6"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True)",Perform global routing in OpenROAD +"from openroad import Design, Tech +import openroad as ord + +tech = Tech() +# Read the files into Openroad +design = Design(tech) + +floorplan = design.getFloorplan() +# Set the floorplan utilization to 35% +floorplan_utilization = 35 +# Set the aspect ratio of the design (height/width) as 0.5 +floorplan_aspect_ratio = 0.5 +# Set the spacing between core and die as 12 +floorplan_core_spacing = [design.micronToDBU(12) for i in range(4)] +# Find the site in lef +db = ord.get_db() +libs = db.getLibs() +site_name = """" +for lib in libs: + sites = lib.getSites() + if len(sites) == 0: + continue + else: + site_name = sites[0].getName() + break +site = floorplan.findSite(site_name) +floorplan.initFloorplan(floorplan_utilization, floorplan_aspect_ratio, + floorplan_core_spacing[0], floorplan_core_spacing[1], + floorplan_core_spacing[2], floorplan_core_spacing[3], site) +floorplan.makeTracks()",How can I automatically search for the name of the site and use that for floorplanning? +"from openroad import Tech, Design +tech = Tech() +# Make sure you have .lef files read into OpenROAD DB +design = Design(tech) + +design.evalTclString(""create_clock -period 50 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"")","If the clock port is called clk_i, how can I set the design clock period to 50 nanoseconds?" +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name) + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk_i] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(45), design.micronToDBU(45)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(40), design.micronToDBU(40)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(5, 20, 5, 25) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMaxWl() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0) / site.getWidth()) +max_disp_y = int(design.micronToDBU(0) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +design.writeDef(""placement.def"") + +","Given a synthesized netlist with a clock port named ""clk_i"", read the library and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 45,45. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 40,40. After floorplanning, place the macros and the standard cells. Place the macros with a bounding box with the bottom-left corner as 5 um,5 um, and the top-right corner as 20 um,25 um. And place each macro at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 0 um, and the y-axis as0. After the placement stage, dump the def file and name it ""placement.def"". " +"from openroad import Tech, Design +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Clock Tree Synthesis +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.0435 -capacitance 0.0817"") +design.evalTclString(""set_wire_rc -signal -resistance 0.0435 -capacitance 0.0817"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X3"") +cts.setRootBuffer(""BUF_X3"") +cts.setSinkBuffer(""BUF_X3"") +cts.runTritonCts() + +# Detailed Placement +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(0.5) / site.getWidth()) +max_disp_y = int(design.micronToDBU(1) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False)",Show me how I can perform CTS in OpenROAD +"from openroad import Tech, Design +import openroad as ord + +tech = Tech() +# Make sure you have files read into OpenROAD DB +design = Design(tech) +design.readDb(""xxx.odb"") + +# Detailed Routing +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M6"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main()",Perform detailed routing in OpenROAD +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +libFiles = libDir.glob(""*.lib"") +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +design = Design(tech)",How can I read .lib files into OpenROAD? +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Set file path +lefDir = Path(""lef_path"") +lefFiles = lefDir.glob('*.lef') +# Modify the technology file postfix for other naming convention +techLefFiles = lefDir.glob(""*.tech.lef"") +# Read library files +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech)",How can I read .lef files into OpenROAD? +"from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have .lef files read into OpenROAD DB +design = Design(tech) + +designDir = Path(""design_path"") +design_file_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" +verilogFile = designDir/str(design_file_name + "".v"") +design.readVerilog(""verilogFile"") +design.link(design_top_module_name)",Show me the way to read the Verilog file into OpenROAD +"from openroad import Design, Tech + +tech = Tech() +# Make sure to read all required files +design = Design(tech) +# Get PDNGen module +pdngen_obj = design.getPdnGen() +# Find the VDD net +VDD_net = design.getBlock().findNet(""VDD"") +# Rip up the VDD grids +pdngen_obj.ripUp(VDD_net)",Rip up the VDD grids +"import openroad as ord +from openroad import Tech, Design +import os, odb, drt, pdn, re +from pathlib import Path + +# Read Files + +tech = Tech() +# Set file path +libDir = Path(""lib_path"") +lefDir = Path(""lef_path"") +techlefDir = Path(""techlef_path"") +designDir = Path(""design_path"") + +design_name = ""design_filename"" +design_top_module_name = ""design_top_module_name"" + +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') +# Read library files +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) +design = Design(tech) +# Read design files +defFile = designDir/str(design_name + "".def"") +design.readDef(""defFile"") + +# Set the clocks +design.evalTclString(""create_clock -period 20 [get_ports clk] -name core_clock"") +design.evalTclString(""set_propagated_clock [all_clocks]"") +# Floorplanning + +floorplan = design.getFloorplan() +# Set the core and die area +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(40)) +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(35)) +# Find the site in lef +site = floorplan.findSite(""site_name"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks() + +# Place Pins + +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place the pins on M8 and M9 +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""M8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""M9"")) +IOPlacer_random_mode = True +design.getIOPlacer().run(IOPlacer_random_mode) + +# Global Placement + +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Set the max iteration of global placement to 10 times +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace() +gpl.doNesterovPlace() +gpl.reset() + +# Macro Placement + +macros = [inst for inst in ord.get_db_block().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + # Set the halo around macros to 5 microns + mpl_halo_x, mpl_halo_y = 5, 5 + mpl.setHalo(mpl_halo_x, mpl_halo_y) + # Set the channel width between macros to 5 microns + mpl_channel_x, mpl_channel_y = 5, 5 + mpl.setChannel(mpl_channel_x, mpl_channel_y) + # Set the fence region as a user defined area in microns + design.getMacroPlacer().setFenceRegion(30, 55, 15, 35) + # Snap the macro to layer M4 (usually M4) + layer = design.getTech().getDB().getTech().findLayer(""M4"") + mpl.setSnapLayer(layer) + mpl.placeMacrosCornerMinWL() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Clock Tree Synthesis + +design.evalTclString(""set_propagated_clock [core_clock]"") +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") + +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Can choose different buffer cells for cts +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Detailed Placement + +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False) + +# Add Filler Cells + +db = ord.get_db() +filler_masters = list() +# Filler cell prefix may be different when using different library +filler_cells_prefix = ""filler_.*"" +for lib in db.getLibs(): + for master in lib.getMasters(): + master_name = master.getConstName() + if re.fullmatch(filler_cells_prefix, master_name) != None: + filler_masters.append(master) +if len(filler_masters) == 0: + print(""wrong filler cell prefix"") +else: + design.getOpendp().fillerPlacement(filler_masters, filler_cells_prefix) + +# Power Planning + +# Global Connect +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDD$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDPE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VDDCE$"", net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSS$"", net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, instPattern = "".*"", + pinPattern = ""^VSSE$"", net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() +# Voltage Domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, switched_power = switched_power, + ground = VSS_net, secondary = secondary) +# Set the width of the PDN ring and the spacing between VDD and VSS rings +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +# When the two layers are parallel, specify the distance between via cuts. +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Define power grid for std cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, name = ""top"", starts_with = pdn.GROUND, + pin_layers = [], generate_obstructions = [], powercell = None, + powercontrol = None, powercontrolnetwork = ""STAR"") +m1 = design.getTech().getDB().getTech().findLayer(""M1"") +m4 = design.getTech().getDB().getTech().findLayer(""M4"") +m7 = design.getTech().getDB().getTech().findLayer(""M7"") +m8 = design.getTech().getDB().getTech().findLayer(""M8"") +grid = pdngen.findGrid(""top"") +for g in grid: + # Make Ring for the core + pdngen.makeRing(grid = g, layer0 = m7, width0 = core_ring_width[0], spacing0 = core_ring_spacing[0], + layer1 = m8, width1 = core_ring_width[0], spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, offset = core_ring_core_offset, pad_offset = core_ring_pad_offset, extend = False, + pad_pin_layers = ring_connect_to_pad_layers, nets = []) + # Add power and ground grid on M1 and attach to cell/macro's VDD/VSS pin + pdngen.makeFollowpin(grid = g, layer = m1, + width = design.micronToDBU(0.07), extend = pdn.CORE) + # Create the rest of the power delivery network + pdngen.makeStrap(grid = g, layer = m4, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m7, width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), pitch = design.micronToDBU(10.8), offset = design.micronToDBU(0), + number_of_straps = 0, snap = False, starts_with = pdn.GRID, extend = pdn.RINGS, nets = []) + pdngen.makeConnect(grid = g, layer0 = m1, layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m7, layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) +# Create power delivery network for macros +m5 = design.getTech().getDB().getTech().findLayer(""M5"") +m6 = design.getTech().getDB().getTech().findLayer(""M6"") +for i in range(len(macros)): + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, inst = macros[i], halo = halo, + pg_pins_to_boundary = True, default_grid = False, + generate_obstructions = [], is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + pdngen.makeStrap(grid = g, layer = m5, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeStrap(grid = g, layer = m6, width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), pitch = design.micronToDBU(6), offset = design.micronToDBU(0), + number_of_straps = 0, snap = True, starts_with = pdn.GRID, extend = pdn.CORE, nets = []) + pdngen.makeConnect(grid = g, layer0 = m4, layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m5, layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + pdngen.makeConnect(grid = g, layer0 = m6, layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], cut_pitch_y = pdn_cut_pitch[1], vias = [], techvias = [], + max_rows = 0, max_columns = 0, ongrid = [], split_cuts = dict(), dont_use_vias = ) + +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes() + +# Global Routing + +signal_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""M1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""M7"").getRoutingLevel() +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True) + +# Detailed Routing + +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""M1"" +params.topRoutingLayer = ""M7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main() + +# Static IR drop Analysis + +psm_obj = design.getPDNSim() +psm_obj.setNet(ord.Tech().getDB().getChip().getBlock().findNet(""VDD"")) +design.evalTclString(f""psm::set_corner [sta::cmd_corner]"") +psm_obj.analyzePowerGrid('', False, '', '') +drops = psm_obj.getIRDropForLayer(tech.getDB().getTech().findLayer(""M1"")) + +design.writeDef(""final.def"") + +","Given a placed design with a clk port called ""clk"", read the technology file and cell libraries, and set the clock period as 20 ns. Perform floorplan and set the bottom-left location of the bounding box of the die as 0,0 and the top-right corner as 60,40. Set the bottom-left corner of the core's bounding box as 5,5 and the top-right corner as 55,35. After floorplanning, place the macros and the standard cells. Set a fence region to place macros inside the bounding box with the bottom-left corner as 30 um,15 um, and the top-right corner as 55 um,35 um. Meanwhile ensure each macro is at least 5 um to each other, and set a halo region around each macro as 5 um. Set the iteration of the global router as 10 times. In the detailed placement stage, set the maximum displacement at the x-axis as 1 um, and the y-axis as3. After the placement stage, perform clock tree synthesis with using BUF_X2 as clock buffers, and set the unit resistance and the unit capacitance value for clock and signal wires to 0.03574 and 0.07516, respectively. Then construct a power grid with power rings on M7 and M8, and have power grids on M1 and M4 for standard cells and macros respectively. Set the width of the M1 grid as 0.07 um, and the width of the M4 grid is 1.2 um. Set the spacing of the M4 grid as 1.2 um and the pitch of the M4 power grid as 6 um. Set the width of the power grids on M7 to 1.4 um and set the spacing and the pitch to 1.4 um and 10.8 um. For the power rings on M7, set the width and spacing to 2 and 2 um, and for the power rings on M8, set the width and spacing to 2 and 2 um as well. If the design has macros, build power grids for macros on M5 and M6 , set the width and spacing of both M5 and M6 grids to 1.2 um, and set the pitch to 6 um. And if there are parallel grids, set the pitch of the via between two grids to 0 um. Last, set the offset to 0 for all cases. In the routing stage, route the design from M1 to M7. In the end, perform IR drop analysis on M1 and dump the def file and name it ""final.def""." +"def check_annealing_debug_and_print_config(): + # Get the IO Placer object of the design + io_placer = design.getIOPlacer() + + # Print the configurations of the IO placer + io_placer.printConfig() + + # Return whether the annealing debug is on + return io_placer.isAnnealingDebugOn() + +# Call the function to check the annealing debug mode and print the config +annealing_debug_on = check_annealing_debug_and_print_config()",Check if the annealing debug mode is on for the IO pin placer and print the configs of the IO pin placer +"# Get the defined top layer of the IO pin placer + +# Get the IO Placer object of the design +iop = design.getIOPlacer() + +# Return the top layer +topLayer = iop.getTopLayer()",Get the defined top layer of the IO pin placer +"def set_min_distance_if_zero(min_distance_value): + # Get the IO Placer object of the design + iop = design.getIOPlacer() + + # Get the parameters of the IO Placer + parameters = iop.getParameters() + + # Get the minimum distance + min_dist = parameters.getMinDistance() + + # Set the minimum distance to 100 if it is 0 + if min_dist == 0: + parameters.setMinDistance(min_distance_value) + + # Set min distance in tracks + parameters.setMinDistanceInTracks(True) + + return min_dist + +# Call the function with the hard-coded min distance value 100 +min_distance = set_min_distance_if_zero(100)",Get the minimum distance setting of the IO pin placer and set it to 100 if it is 0 +"# Get the number of DRVs, cloud size and set the could size to 500 from the detailed router + +# Get the Triton Route object of the design +triton_route = design.getTritonRoute() + +# Get the number of DRVs +num_drvs = triton_route.getNumDRVs() + +def get_and_set_drv_and_cloud_size(cloud_size_value): + # Get the Triton Route object of the design + triton_route = design.getTritonRoute() + + # Get the number of DRVs + num_drvs = triton_route.getNumDRVs() + + # Set the cloud size to the specified value + cloud_size = triton_route.setCloudSize(cloud_size_value) + + # Return the number of DRVs and cloud size + return (num_drvs, cloud_size) + +# Call the function with the hard-coded cloud size value of 500 +drv_and_cloud_size = get_and_set_drv_and_cloud_size(500) + +# Return the number of DRVs and cloud size +return (num_drvs, cloud_size)","Get the number of DRVs, cloud size and set the could size to 500 from the detailed router" +"# Change the setting of horizontal and vertical length of thr IO pin placer to 100 + +# Get the IO Placer object of the design +iop = design.getIOPlacer() + +# Get the parameters of the IO Placer +parameters = iop.getParameters() + +# Set vertical and horizontal length to 100 +parameters.setVerticalLength(100) +parameters.setHorizontalLength(100)",Change the setting of horizontal and vertical length of thr IO pin placer to 100 +"# Adjust the setting of vertical length of the IO pin placer to 100 + +# Get the IO Placer object of the design +iop = design.getIOPlacer() + +# Get the parameters of the IO Placer +parameters = iop.getParameters() + +# Set vertical length to 100 +parameters.setVerticalLength(100)",Adjust the setting of vertical length of the IO pin placer to 100 \ No newline at end of file diff --git a/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/Flow_Dataset.xlsx b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/Flow_Dataset.xlsx new file mode 100644 index 0000000..f944253 Binary files /dev/null and b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/Flow_Dataset.xlsx differ diff --git a/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/README.md b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/README.md new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Prompt-Script/README.md @@ -0,0 +1 @@ + diff --git a/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Question-Answer/Question-Answer_Dataset.csv b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Question-Answer/Question-Answer_Dataset.csv new file mode 100644 index 0000000..c5e7beb --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Question-Answer/Question-Answer_Dataset.csv @@ -0,0 +1,1008 @@ +Prompts,Answers +What is PDNGEN?,"The PDNGEN module (pdn) in OpenROAD aims to simplify the process of adding a power grid into a floorplan. A user can specify a small set of power grid policies to be applied to the design, such as the layers to use, stripe width, and spacing, and then pdn will generate the actual metal straps. Power grid policies can be defined over both the standard cell area and areas occupied by macros." +What does the -switch_cell argument in PDN do while doing power switch insertion?,"During power switch insertion, the -switch_cell argument is used to specify the name of a coarse-grain power switch cell that is to be inserted wherever the standard cell rail connects to the rest of the power grid. The mesh layers are associated with the unswitched power net of the voltage domain, whereas the standard cell rail is associated with the switched power net of the voltage domain. The placement of a power switch cell connects the unswitched power mesh to the switched power rail through a power switch defined by the define_power_switch_cell command." +What does the par module do?,"The partitioning module (par) is based on TritonPart, an open-source constraints-driven partitioner. par can be used to partition a hypergraph or a gate-level netlist. TritonPart solves multi-way partitioning by 1) constraints-driven coarsening, 2) initial partitioning, 3) refinement, 4) cut-overlay clustering and partitioning (COCP), and 5) V-cycle refinement. The purpose of partitioning a netlist is to reduce the complexity of a circuit so that algorithms can operate on smaller chunks of the netlist at a time. Partitioning a netlist may slightly reduce the optimization opportunities compared to a non-partitioned approach, but it greatly benefits the runtime. Partitioning a netlist may be the only option to feasibly operate on very large circuits." +Is TritonRoute the foundation of drt?,"The Detailed Routing (drt) module in OpenROAD is based on the open-source detailed router TritonRoute. TritonRoute consists of several main building blocks, including pin access analysis, track assignment, initial detailed routing, search and repair, and a DRC engine. The initial development of the router is inspired by the ISPD-2018 initial detailed routing contest. However, the current drt framework differs and is built from scratch, aiming for an industrial-oriented, scalable, and flexible flow." +What is the structure of OpenDB?,The structure of OpenDB is based on the text file formats LEF (library) and DEF (design) formats version 5.6. OpenDB supports a binary file format to save and load the design much faster than using LEF and DEF. OpenDB is written in C++ 98 with standard library-style iterators. The classes are designed to be fast enough to base an application on without having to copy them into application-specific structures. +How is FastRoute better than previous routing frameworks?,"FastRoute innovates over prior routing frameworks because it integrates several novel techniques: fast congestion-driven via-aware Steiner tree construction, 3-bend routing, virtual capacity adjustment, multi-source multi-sink maze routing, and spiral layer assignment. These techniques not only address the routing congestion measured at the edges of global routing grids but also minimize the total wirelength and via usage, which is critical for subsequent detailed routing, yield, and manufacturability. Experimental results show that FastRoute is highly effective and efficient in solving ISPD07 and ISPD08 global routing benchmark suites. The results outperform recently published academic global routers in both routability and runtime. In particular, for ISPD07 and ISPD08 global routing benchmarks, FastRoute generates 12 congestion-free solutions out of 16 benchmarks with a speed significantly faster than other routers." +What does RTLMP do?,"A macro placer (MP) is an algorithm which specifically focuses on placing macros in the core area. RTL­MP is a novel macro placer that utilizes RTL information and tries to “mimic” the interaction between the frontend RTL designer and the back­ end physical design engineer to produce human­-quality floorplans. By exploiting the logical hierarchy and processing logical modules based on connection signatures, RTL­MP can capture the dataflow inherent in the RTL and use the dataflow information to guide macro placement." +What was the need to develop Hier-RTLMP?,"Recently, with the increasing complexity of IP blocks, and in particular with auto-generated RTL for machine learning (ML) accelerators, the number of macros in a single RTL block can easily run into several hundred. This makes the task of generating an automatic floorplan (.def) with IO pin and macro placements for front-end physical synthesis even more critical and challenging. The so-called peripheral approach of forcing macros to the periphery of the layout is no longer viable when the ratio of the sum of the macro perimeters to the floorplan perimeter is large since this increases the required stacking depth of macros. Thus, a novel multilevel physical planning approach that exploits the hierarchy and dataflow inherent in the design RTL, and describes its realization in a new hierarchical macro placer, Hier-RTLMP was developed. " +How is Hier-RTLMP different from RTL-MP?,"Hier-RTLMP consists of an auto-clustering engine that transforms the logical hierarchy into a physical hierarchy. Unlike RTL-MP where the physical hierarchy is a single level, Hier-RTLMP’s autoclustering engine creates a multilevel physical hierarchy of physical clusters. This enables the handling of large RTLs with hundreds of macros and allows for the placement of macros within the core area." +How does FastRoute work?,"The first part of the FastRoute framework is topology generation. Because FastRoute tries to avoid rip-up and reroute to reduce both wirelength and runtime, the initial tree topology has significant impacts. With the congestion-driven and via-aware topology, the next stage of FastRoute is actual routing. We find that there exists significant potential to improve traditional routing techniques in terms of via control and congestion reduction. The most commonly used routing techniques in global routing include L/Z/U pattern routing, monotonic routing, and maze routing. In addition to new topology and routing techniques, Fast Route integrates several performance enhancement techniques to further improve routing quality and reduce run time." +Why is RSMT used more?,"Traditionally, global routing just uses tree structures like RMST or RSMT while RSMT is becoming more popular due to its minimal wirelength to connect a multi-pin net." +"Tab completion does work in console mode but not in GUI mode, why?","The OpenROAD GUI is made from custom Qt code and does not apply to the console. OpenROAD relies on the tclreadline package, which doesn't work well with imported namespaces." +"What do these Debug output mean? +[INFO MPL-0024] [Multilevel Autoclustering] Creating clustered netlist. +[INFO MPL-0039] [Coarse Shaping] Determining shape functions for clusters. +[INFO MPL-0028] [Hierarchical Macro Placement] Placing clusters and macros. +[INFO MPL-0037] Updated location of 95 macros +Delete buffers for RTLMP flow... +[INFO RSZ-0026] Removed 0 buffers.","Messages with the MPL prefix are from the macro placement (mpl) module. These messages are progress messages, informing the user which step of the HierRTLMP flow is being executed." +What are the units of the -pad_right and -pad_left arguments of the global_placement function,"In global_placement, -pad_right and -pad_left add padding which is measured in cell sites to effectively make the cell appear wider. pad_left adds a pad to the left side, pad_right adds it to the right side. Wider cells during global placement can help reduce placement congestion and make finding a valid placement easier." +Does space padding influence the design utilization? I feel like it shouldn't.,"Cell padding only impacts the way the global placer (gpl) and detailed placer (dpl) sees the cells. Cell padding does not change the logic area of the cell from the user perspective. If you were to use the report_design_area command, you would see the unpadded design utilization reported." +"Wouldn't manually adding pads in the global_placement function reduce the maximum design utilization possible for a design? Especially since OpenROAD wants to be automatic, GPL will stop everything if it sees a DU >100% even if it could achieve a reasonable DU with equivalent padding","Cell padding can reduce the maximum possible design utilization. If you don't want padding in your design, you can reduce the default padding or turn it off. However, padding is usually necessary to achieve a cleanly routed design, because cells which are too close together may make routing impossible. If you want to optimize for very high-density designs, I believe you can also set padding on a master-by-master basis so that only the most difficult cells are padded. This process may take some trial and error." +Why did I encounter an issue with CORE_UTILIZATION when trying to aim for a DU of 70% on the ASAP7 PDK which should be possible and reasonable for any design?,"If you are using ORFS, the CORE_UTILIZATION variable only determines the core utilization after Yosys (synthesis) runs using the netlist data. The utilization can change dramatically as OpenROAD performs timing optimization, which will insert buffers, remove buffers, and resize cells. For example, if you set CORE_UTILIZATION to 70% utilization during the initialization step, you may end up with 90%+ utilization because of optimization to meet timing constraints. It is currently up to the designer to ensure that the CORE_UTILIZATION is set appropriately, which may require some trial and error." +"If I have a design for which the detailed placement fails for a few instances, if I relax my timing constraints will it result in a successful placement?","Relaxing timing constraints can usually reduce your design utilization because fewer buffers will need to be inserted. However, detailed placement can fail for several reasons, including 1) setting core utilization too high, 2) not having enough cell padding during global placement, 3) having too much cell padding during detailed placement, 4) having a poor macro placement which will block placement of some standard cells" +"The timing optimizations done by the synthesis tool are ""discarded"" as the buffers are removed?","Empiracally, the OpenROAD team has found that OpenROAD optimizes better when the buffers from Yosys are removed, because Yosys does not do physical synthesis." +Is there no need to re-synthesize with different timing constraints with Yosys? Or does it also use different/bigger non-buffer cells that also need to be resized?,"Empirically, applying timing constraints to Yosys for synthesis does not have much impact on the output netlist. However, the results may not be identical if the timing constraints are changed." +"What does this warning mean? +[WARNING ODB-0208] VIA: duplicate VIA (via5_6_120_288_1_2_58_322) ignored...","This warning likely occurs because of multiple block abstracts with the same via. To fix this problem, one should ensure that the block abstracts do not have duplicates via definitions." +"Upon attempting to read an invalid ODB file, OpenROAD doesn't attempt to validate it and instead crashes with a cryptic message of Error: read_db.tcl, 1 ios_base::clear: unspecified iostream_category error. Why is this happening?","I would advise against using low-level OBD APIs to interact with OpenROAD. User-facing APIs in OpenROAD have documentation and error checking to prevent improper usage, however low-level APIs may not have error checking for performance reasons. In this case, it appears the db you are creating does not have a logger and can't issue any messages." +What is IR Drop Analysis?,"The IR Drop Analysis module in OpenROAD (psm) is based on PDNSim, an open-source static IR analyzer. PDNSim will perform a simulation based on the estimated current draw of each instance to estimate what is the voltage drop seen at each cell. That is, it shows the voltage drop between the voltage source(s) of the chip and each instance." +What are the features of IR Drop analysis?,"The features of IR Drope analysis are: reporting the worst IR drop, reporting the worst current density over all nodes and wire segments in the power distribution network (given a placed and PDN-synthesized design), checking for floating PDN stripes on the power and ground nets, and spice netlist writer for power distribution network wire segments." +What is Flute3?,Flute3 is an open-source rectilinear Steiner minimum tree heuristic with improvements made by UFRGS students and James Cherry. This tool is used for the calculation of wirelength in grt and rsz. +What is OpenDB?,"OpenDB is a design database to support tools for physical chip design. It was originally developed by Athena Design Systems. Nefelus, Inc. acquired the rights to the code and open-sourced it with BSD-3 license in 2019 to support the DARPA OpenROAD project. The structure of OpenDB is based on the text file formats LEF (library) and DEF (design) formats version 5.6. OpenDB supports a binary file format to save and load the design much faster than using LEF and DEF. OpenDB is written in C++ 98 with standard library style iterators. The classes are designed to be fast enough to base an application on without having to copy them into application-specific structures." +What is Automatic Code Generator used for?,The automatic code generator in OpenROAD is used to generate code for OpenDB objects and Iterators. It uses JSON input and automatically generates corresponding C++ files +What commands are used to read and write design data in OpenROAD?,"OpenROAD is run using Tcl scripts. The following commands are used to read and write design data. +read_lef [-tech] [-library] filename +read_def filename +write_def [-version 5.8|5.7|5.6|5.5|5.4|5.3] filename +read_verilog filename +write_verilog filename +read_db filename +write_db filename +write_abstract_lef filename" +"What support does OpenROAD have for Abstract LEF? +",OpenROAD contains an abstract LEF writer that can take your current design and emit an abstract LEF representing the external pins of your design and metal obstructions. Use the write_abstract_lef command to generate the abstract LEF. +What does the global_connect command do?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The global_connect command is used to define logical connections between supply pins on design instances and their respective supply nets. Note that the global_connect command only creates a logical connection; it does not perform any routing for a physical connection. +What does the clear_global_connect command do?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The clear_global_connect command is used to clear previously declared connections between supply pins on design instances and their respective supply nets. Note that the clear_global_connect command only clears the logical connections; it does not remove any routing or physical connections. +What does the report_global_connect command do?,Global connections are typically used to define connections between a supply net (such as power/ground) and the supply pins on cells. The report_global_connect command is used to print out the currently defined global connection rules. +What does the report_cell_usage command do?,The report_cell_usage command is used to print out the number of instances of each type of cell (master) used in the design. +How does OpenROAD compute the die area when using the core_utilization argument in the initialize_floorplan?,"To compute the die area for the initialize_floorplan command, OpenROAD first calculates the core area by dividing the total logic area of the instances coming from synthesis and by the specified core_utilization. OpenROAD then shapes that core area based on the aspect_ratio parameter. Finally, OpenROAD expands the core area by adding a core margin on each edge of the core area. Altogether, this forms the die area." +I would like to know if there is any way to write the log output from OpenROAD into a file (using a report_ type command)?,"To capture output from OpenROAD, you can use standard Unix file operations and redirections. OpenROAD outputs all messages directly to the stdout I/O stream." +What is the minimum number of metal layers OpenROAD can route in?,"OpenROAD has the theoretical ability to route as few as two layers, but it has rarely been tried by the developers due to the lack of a specialized channel router. It is expected that OpenROAD will hit some issues and have to iterate. If you try this and run into issues, please kindly file an issue on GitHub. However, if the PDK is proprietary, it will be more difficult for the OpenROAD team to diagnose and debug." +"Can OpenROAD work with multi-VT cells (HVT, LVT, SVT) and swap between them in a single run?","OpenROAD supports using multi-VT cell libraries, and it can swap between VT cells during optimization." +Can OpenROAD work with Multi-Mode-Multi-Corner Files (mmmc) ?,"OpenROAD supports multi-corner Static Timing Analysis (STA), but it doesn't currently support multi-mode STA. ""MMMC"" files from proprietary tools are stored in proprietary formats, which OpenROAD cannot support. The OpenSTA manual will contain more information about how to run multi-corner analysis." +Is SystemVerilog support limited to the constructs that Yosys supports?,The OpenROAD Flow is limited to the RTL language support that the Yosys synthesizer provides. Yosys currently provides support for a limited subset of SystemVerilog and full support for Verilog. OpenROAD only supports structural Verilog netlists. +What is the job of Pin Placer?,"Place pins on the boundary of the die on the track grid to minimize net wirelengths. Pin placement also creates a metal shape for each pin using min-area rules. For designs with unplaced cells, the net wirelength is computed considering the center of the die area as the unplaced cells' position." +What does Antenna Rule Checker do?,"This tool checks antenna violations and generates a report to indicate violated nets. See LEF/DEF 5.8 Language Reference, Appendix C, ""Calculating and Fixing Process Antenna Violations"" (p.389) for a description of antenna violations." +What is Clock Tree Synthesis in OpenROAD?,"Clock tree synthesis (CTS) is the step of distributing a clock to all endpoints (such as flip-flops) while trying to minimize power and skew (the different in clock arrival times between two registers). The clock tree synthesis module in OpenROAD (cts) is based on TritonCTS 2.0, and can be run using the clock_tree_synthesis command. TritonCTS 2.0 features on-the-fly characterization, and therefore does not need to pre-generate characterization data. The on-the-fly characterization feature can be optionally controlled by parameters specified by the configure_cts_characterization command. You can use the set_wire_rc command to set the clock routing layer used when calculating parasitics in this step." +Tell me about Detailed Placement in OpenROAD?,"The detailed placement module in OpenROAD (dpl) is based on OpenDP or Open-Source Detailed Placement Engine. Its key features are +fence region and fragmented ROWs." +Describe the Restructure module in OpenROAD?,The restructure module in OpenROAD (rmp) is based on an interface to ABC for local resynthesis. The package allows logic restructuring that targets area or timing. It extracts a cloud of logic using the OpenSTA timing engine and passes it to ABC through the blif interface. Multiple recipes for area or timing are run to obtain multiple structures from ABC; the most desirable among these is used to improve the netlist. The ABC output is read back by a blif reader which is integrated into OpenDB. Blif writer and reader also support constants from and to OpenDB. Reading back of constants requires insertion of tie cells which should be provided by the user as per the interface described below. +What is RePlAce in OpenROAD?,"RePlAce is a tool for advancing solution quality and routability validation in Global Placement. Its features are analytic and nonlinear placement algorithms. it solves electrostatic force equations using Nesterov's method, verified with various commercial technologies and research enablements using OpenDB, verified deterministic solution generation with various compilers and OS, and supports Mixed-size placement mode." +What is Hierarchical Macro Placement/ Hier-RTLMP?,"""Hier-RTLMP"" is defined as a hierarchical automatic macro placer for large-scale complex IP blocks. This tool builds on the existing RTLMP (mpl) framework, adopting a multilevel physical planning approach that exploits the hierarchy and data flow inherent in the design RTL." +Describe Parallax Static Timing Analyzer or OpenSTA?,"OpenSTA is a gate-level static timing verifier. As a stand-alone executable, it can be used to verify the timing of a design using standard file formats. OpenSTA uses a TCL command interpreter to read the design, specify timing constraints, and print timing reports." +What file formats are supported by Parallax Static Timing Analyzer or OpenSTA?,"The Following standard file formats are supported by Parallax Static Timing Analyzer or OpenSTA: Verilog netlist, Liberty library, SDC timing constraints,SDF delay annotation, and SPEF parasitics." +"`auto_place_pins pin_layer` places pins on a single layer but It should be able to place vertical pins (sides of the die) and horizontal pins (top and bottom of the die) in separate layers, why is it not able to do this?","I currently recommend using `io_placer` instead of `auto_place_pins`. Here's an example:```io_placer -hor_layer 3 -ver_layer 2```Note that `io_placer` uses cell placement information to guide the I/O pin placement. If placement has not yet been run, the `-random` flag is required, which will distribute the pins evenly over the die boundary." +What dependencies are required for TritonPart?,TritonPart in OpenROAD uses Google OR-Tools as the ILP solver. Please install Google OR-Tools. +What is DFT?,This tool is an implementation of Design For Testing. New nets and logic are added to allow IC designs to be tested for errors in manufacturing. Physical imperfections can cause hard failures and variability can cause timing errors. +Tell me about the parts of DFT insertion?,"A simple DFT insertion consists of the following parts: a scan_in pin where the test patterns are shifted in, a scan_out pin where the test patterns are read from, scan cells that replace flops with registers that allow for testing, one or more scan chains (shift registers created from your scan cells), a scan_enable pin to allow your design to enter and leave the test mode." +What is Read UPF Utility?,"This module contains functionality to read, and modify information from Unified Power Format (UPF) files." +What is Metal fill?,"Metal filling is a common process in integrated circuit design to enhance manufacturability and yield by making the density of metal shapes more uniform across the design. In OpenROAD, the Finale module (fin) inserts floating metal fill shapes to meet metal density design rules while obeying DRC constraints. The rules for generating metal fill shapes are driven by a JSON configuration file, and the schema can be found in the OpenROAD documentation." +Explain Chip-level Connections in OpenROAD?,"The chip-level connections module in OpenROAD (pad) is based on the open-source tool ICeWall. In this utility, either place an IO ring around the boundary of the chip and connect with either wirebond pads or a bump array." +Brief me on the parasitics extraction module?,"The parasitics extraction module in OpenROAD (rcx) is based on the open-source OpenRCX, a Parasitic Extraction (PEX, or RCX) tool that works on OpenDB design APIs. It extracts routed designs based on the LEF/DEF layout model. +OpenRCX extracts both Resistance and Capacitance for wires, based on coupling distance to the nearest wire and the track density context over and/or under the wire of interest, as well as cell abstracts. The capacitance and resistance measurements are based on equations of coupling distance interpolated on exact measurements from a calibration file, called the Extraction Rules file. The Extraction Rules file (RC technology file) is generated once for every process node and corner, using a provided utility for DEF wire pattern generation and regression modeling. +OpenRCX stores resistance, coupling capacitance, and ground (i.e., grounded) capacitance on OpenDB objects with direct pointers to the associated wire and via db objects. Optionally, OpenRCX can generate a .spef file." +What are the Gate Resizer commands?,The resizer commands stop when the design area is -max_utilization util percent of the core area. util is between 0 and 100. The resizer stops and reports an error if the maximum utilization is exceeded. +What is macro placement?,"The macro placement module in OpenROAD (mpl) is based on TritonMacroPlacer, an open-source ParquetFP-based macro cell placer. The macro placer places macros/blocks honoring halos, channels, and cell row ""snapping"". Run global_placement before macro placement." +What is global routing?,"The global routing module in OpenROAD (grt) is based on FastRoute, an open-source global router originally derived from Iowa State University's FastRoute4.1 algorithm. Global routing is responsible for creating routing guides for each net to simplify the job of the detailed router. The purpose of global routing is mainly to avoid overcongestion when creating the guides." +Elaborate on FastRoute?,"FastRoute is a global routing tool for VLSI back-end design. It is based on sequential rip-up and re-route (RRR) and a lot of novel techniques. FastRoute 1.0 first uses FLUTE to construct congestion-driven Steiner trees, which will later undergo the edge-shifting process to optimize tree structure to reduce congestion. It then uses pattern routing and maze routing with a logistic function-based cost function to solve the congestion problem. FastRoute 2.0 proposed monotonic routing and multi-source multi-sink maze routing techniques to enhance the capability to reduce congestion. FastRoute 3.0 introduced the virtual capacity technique to adaptively change the capacity associated with each global edge to divert wire usage from highly congested regions to less congested regions. FastRoute 4.0 proposed via-aware Steiner tree, 3-bend routing, and a delicate layer assignment algorithm to effectively reduce via count while maintaining outstanding congestion reduction capability. FastRoute 4.1 simplifies the way the virtual capacities are updated and applies a single set of tuning parameters to all benchmark circuits" +Brief me on OpenROAD Flow?,"OpenROAD-flow-scripts (ORFS) is a fully autonomous, RTL-GDSII flow for rapid architecture and design space exploration, early prediction of QoR, and detailed physical design implementation. However, ORFS also enables manual intervention for finer user control of individual flow stages through Tcl commands and Python APIs." +"I'm trying to port ORFS to a TSMC process. During the detailed route step, I get a lot of DRT-0073 errors. Utilization is set to 20% at the beginning of the P&R flow and it is a pretty simple design. Give me some tips about what to look into? +I have tried to run the pin_access command directly but the -verbose parameter does not seem to work as I don't get any more information","You can try the developer debugs to get a sense of what is going on. Put detailed_route_debug -pa -pa_markers -pin _3504_:A1 before you call detailed_route and run it in the GUI. It will stop at the pin and show you how it is trying to access it and any associated drc markers. You click the continue button to see the various steps. Hopefully, that gives you an idea as to what is going on. The other option is a support contract with precisioninno.com where we can help under NDA. +" +"Is there any way I can use just the RTL-MP2 stand-alone on either an RTL design or a gate netlist? The issue is, that we use proprietary tools so do not have an OpenDB database for our designs.","OpenROAD supports interoperability with other EDA tools through the industry standard Verilog, LEF, and DEF formats. In this case, you can import a DEF file into OpenROAD from an external tool, run RTL-MP2, and then export the DEF file. The DEF file format should be supported by nearly all EDA physical design tools." +How do I check DRC?,"In OpenROAD, you can use the check_drc command to run the design rule check (DRC). It should be noted that check_drc is not a general-purpose checker and only verifies signal routing according to routing rules from the technology LEF file. check_drc also requires routing guides in order to run, so global routing must be performed first. DRC is also commonly performed by an external tool which will check all layers, not just the metal routing layers." +What does the argument -floorplan_initialize do in read_def?,"When using the read_def command with the -floorplan_initialize argument, OpenROAD will read only physical placement information such as pin locations and instance locations. It does not read or redefine the netlist." +What does the argument -skip_pin_swap & -skip_gate_cloning do in repair_timing?,"These flags disable optimizations in case of trouble or unexpected results. They are mainly included as a failsafe for users, rather than something that is expected to be used." +What does the detailed_placement command do in OpenROAD?,"The detailed_placement command moves instances to legal locations after global placement. While the global placer (gpl) may place cells in a roughly optimal position, gpl may not place the cells in legal locations because they may not be aligned to cell rows or sites. The detailed placer (dpl) will legalize the cell by shifting it to a nearby location which is aligned to the cell site grid. The detailed_placement command only performs basic legalization and does not attempt to optimize placement. The optimize_mirroring and improve_placement commands will perform optimization on the legalized cells." +"What does the argument -max_displacement disp|{disp_x disp_y} do in detailed_placement +Command?","Max distance that an instance can be moved (in microns) when finding a site where it can be placed. Either set one value for both directions or set {disp_x disp_y} for individual directions. The default values are {0, 0}, and the allowed values within are integers [0, MAX_INT]. This argument is useful because it limits the amount of searching and therefore amount of runtime that the detailed placer can use." +What does the argument -disallow_one_site_gaps do in the detailed_placement command?,"detailed_place -disallow_one_site_gaps will disallow the detailed placer from leaving gaps between cells that are exactly one cell sitewide. This feature is mainly useful for PDKs that do not have filler cells which are one site-wide. In this case, one-site-wide gaps are unfillable and will cause DRC violations." +What does the argument -report_file_name do in the detailed_placement command?,"The -report_file_name argument for the detailed_placement command specifies where the report for detailed placement should be saved. The report is saved in the JSON format and contains metrics related to detailed_placement. If this argument is not provided, no report will be saved for the detailed_placement command." +What does the Set Placement Padding command do?,"The set_placement_padding command sets left and right padding in multiples of the row site width. Use the set_placement_padding command before legalizing placement to leave room for routing. Use the -global flag for padding that applies to all instances. Use -instances for instance-specific padding. The instances insts can be a list of instance names, or an instance object returned by the SDC get_cells command. To specify padding for all instances of a common master, use the -filter ""ref_name == "" option to get_cells." +What is the significance of the filler_placement command?,"The filler_placement command fills gaps between detail-placed instances to connect the power and ground rails in the rows. filler_masters is a list of master/macro names to use for filling the gaps. Wildcard matching is supported, so FILL* will match, e.g., FILLCELL_X1 FILLCELL_X16 FILLCELL_X2 FILLCELL_X32 FILLCELL_X4 FILLCELL_X8. To specify a different naming prefix from FILLER_ use -prefix ." +What is the purpose of the remove_fillers command?,This command removes all filler cells. +What does the check_placement command do?,The check_placement command checks the placement legality. It returns 0 if the placement is legal. +What does the argument -verbose in the check_placement command do?,The -verbose argument enables verbose logging in the check_placement command. +What does the argument -disallow_one_site_gaps in the check_placement command do?,The argument -disallow_one_site_gaps disables one site gap during placement check. +What role does this argument -report_file_name play in the check_placement command?,The argument -report_file_name in check_placement command files name for saving the report (e.g. report.json). +What does the optimize_mirroring command do?,The optimize_mirroring command mirrors instances about the Y axis in a weak attempt to reduce the total half-perimeter wirelength (HPWL). No arguments are needed for this function. +What are some useful developer commands in the detailed placement module in OpenROAD (dpl)?,"If you are a developer, you might find the following commands useful, 1. detailed_placement_debug: debug detailed placement. 2. get_masters_arg: get masters from a design. 3. get_inst_bbox: get the bounding box of an instance. 4. get_inst_grid_bbox: get the grid bounding box of an instance. 5. format_grid: format grid (takes in length x and site width w as inputs). 6. get_row_site: get row site name." +What does the argument [-max_length ] do in the set_dft_config command of DFT- Design For Testing?,The argument [-max_length ] takes an integer as input for setting the maximum number of bits that can be in each scan chain. +What does the argument [-clock_mixing] do in the set_dft_config command of DFT?,The argument [-clock_mixing] dictates how the architect mixes the scan flops based on the clock driver. The value no_mix creates scan chains with only one type of clock and edge. This may create unbalanced chains. The value clock_mix creates scan chains mixing clocks and edges. Falling edge flops are going to be stitched before the rising edge. +What does the report_dft_config command do in DFT- Design For Testing?,The report_dft_config command prints the current DFT configuration to be used by preview_dft and insert_dft. +What does the preview_dft command do in DFT- Design For Testing?,This command prints a preview of the scan chains that will be stitched by insert_dft. Use this command to iterate and try different DFT configurations. This command does not perform any modification to the design. +What does the argument [-verbose] do in the preview_dft command of DFT- Design For Testing?,The preview_dft command shows more information about each one of the scan chains that will be created. +What does the insert_dft command do in DFT- Design For Testing?,"The insert_dft command implements the scan chains into the design by performing the following actions: Scan Replace, Scan Architect, Scan Stitch. The result is a design with scan flops connected to form the scan chains." +Can you give me an example of a basic Design for Testing command?,Here is an example that will create scan chains with a max length of 10 bits mixing all the scan flops in the scan chains: set_dft_config -max_length 10 -clock_mixing clock_mix report_dft_config preview_dft -verbose insert_dft. +What are the limitations of Design for Testing (DFT)?,"The limitations of DFT-Design for Testing are as follows: there are no optimizations for the scan chains, this is a WIP, there is no way to specify existing scan ports to be used by scan insertion, there is currently no way to define a user-defined scan path, and can only work with one-bit cells." +What is the report_cts command in Clock Tree Synthesis (cst) in OpenROAD used for?,"It is used to extract metrics after a successful clock_tree_synthesis run. These metrics are the number of Clock Roots, number of Buffers Inserted, number of Clock Subnets, and number of Sinks." +What does the argument -out_file in report_cts command in Clock Tree Synthesis (cst) in OpenROAD do?,"The file to save cts reports. If this parameter is omitted, the report is streamed to stdout and not saved." +What does the clock_tree_synthesis_debug command in Clock Tree Synthesis (cst) in OpenROAD do?,This command is an option to plot the CTS to GUI. +Which environment is required for setting up OpenROAD flow scripts?,You can use the bash shell to run commands and scripts. +What are the ways of installing OpenROAD flow scripts/ ORFS?,"These are the ways of installing OpenROAD flow scripts/ ORFS: Docker, Pre-built Binaries, Windows Subsystem for Linux (WSL), and Local Installation." +What is the basic build command for OpenROAD flow scripts/ ORFS?,The basic basic build command in ORFS is ./build_openroad.sh --help. +What does the following argument do in the build command of ORFS: -o or —local?,"The argument, o or —local, builds locally instead of building a Docker image." +What operation does the -l or --latest argument perform in the build command of ORFS?,The -l or --latest argument specifies to use of the head of branch –or_branch or ‘master’ by default for tools/OpenROAD. +How is this argument utilized in the build command of ORFS: --or_branch BRANCH_NAME?,The -or_branch BRANCH_NAME argument stipulates the use of the head of branch BRANCH for tools/OpenROAD. +What role does this argument play in the build command of ORFS: --or_repo REPO_URL?, This argument enumerates to use of a fork at REPO-URL (https/ssh) for tools/OpenROAD. +What does the following argument do in the build command of ORFS: --no_init?,The --no_init argument prescribes skipping initializing submodules. +How does the following argument function in the build command of ORFS: -t N or --threads N?,The -t N or --threads N argument stipulates the use of N cpus when compiling software. +What is the purpose of the following argument in the build command of ORFS: -n or --nice?,"The -n or --nice flag in the build script instructs the build script to set all jobs to the maximim Unix ""niceness"". Niceness determines how much the operating system prefers to schedule process. The purpose of setting this flag is to ensure that a system is not overwhelmed by using all available processing primarily of the build jobs. The build will use all CPUs by default unless --threads is also given, then N threads are used instead." +What does the following argument do in the build command of ORFS: —yosys-args-overwrite?,This argument states to not use default flags set by this scrip during Yosys compilation. +What is the purpose of the following argument in the build command of ORFS: —yosys-args STRING?,The '—yosys-args STRING' argument adds additional compilation flags for Yosys compilation. +What function does the following argument serve in the build command of ORFS: —openroad-args-overwrite?,The '—openroad-args-overwrite' argument specifies to not use default flags set by this script during OpenROAD app compilation. +What does the following argument do in the build command of ORFS: —openroad-args STRING?,The '—openroad-args STRING' argument adds aditional compilation flags for OpenROAD app compilation. +What is the purpose of the following argument in the build command of ORFS: —lsoracle-enable?,This argument initiates compiling LSOracle since it is disabled by default as it is not currently used on the flow. +What does the following argument do in the build command of ORFS: —lsoracle-args-overwrite?,The '—lsoracle-args-overwrite' argument stipulates not to use default flags set by this script during LSOracle compilation. +What does the following argument achieve in the build command of ORFS: —lsoracle-args STRING?,This argument adds aditional compilation flags for LSOracle compilation. +What function does the following argument serve in the build command of ORFS: —install-path PATH?,The '—install-path PATH' delineates the path to install tools. Default is ${INSTALL_PATH}. +What does the following argument do in the build command of ORFS: —clean?,The '—clean' argument calls the git clean command interactively before compiling. It is useful to remove old build files. +What does the following argument do in the build command of ORFS: —clean-force?,This '—clean-force' argument will call git clean before compiling but WARNING: this option will not ask for confirmation. It is useful to remove old build files. +What function does the following argument serve in the build command of ORFS: -c or --copy-platforms?,This argument is only applicable to docker builds. It is used to copy platforms inside the docker image. +What does the following argument do in the build command of ORFS: —docker-args-overwrite?,The ' —docker-args-overwrite' argument is only applicable for docker builds. They specify to not use default flags set by this script for Docker builds. +What does the following argument do in the build command of ORFS: —docker-args STRING?,This argument is only applicable to docker builds. It is used to add additional compilation flags for the Docker build. +What is OpenROAD?,"The OpenROAD (""Foundations and Realization of Open, Accessible Design"") Project was launched in June 2018 within the DARPA IDEA program. OpenROAD aims to bring down the barriers of cost, expertise, and unpredictability that currently block designers' access to hardware implementation in advanced technologies. The project team is developing a fully autonomous, open-source toolchain for digital SoC layout generation, focusing on the RTL-to-GDSII phase of system-on-chip design. Thus, OpenROAD holistically attacks the multiple facets of today's design cost crisis: engineering resources, design tool licenses, project schedule, and risk." +What is AutoTuner?,"AutoTuner is a ""no-human-in-loop"" parameter tuning framework for commercial and academic RTL-to-GDS flows. AutoTuner provides a generic interface where users can define parameter configuration as JSON objects. This enables AutoTuner to easily support various tools and flows. AutoTuner also utilizes METRICS2.1 to capture PPA of individual search trials. With the abundant features of METRICS2.1, users can explore various reward functions that steer the flow autotuning to different PPA goals." +WHat are the current supported search algorithms by AutoTuner?,"AutoTuner contains top-level Python script for ORFS, each of which implements a different search algorithm. Current supported search algorithms are as follows: +Random/Grid Search, Population Based Training (PBT), Tree Parzen Estimator (HyperOpt), Bayesian + Multi-Armed Bandit (AxSearch), Tree Parzen Estimator + Covariance Matrix Adaptation Evolution Strategy (Optuna), Evolutionary Algorithm (Nevergrad)" +How to set the direction of tuning in AutoTuner?,"User-defined coefficient values (coeff_perform, coeff_power, coeff_area) of three objectives to set the direction of tuning are written in the script. Each coefficient is expressed as a global variable at the get_ppa function in PPAImprov class in the script (coeff_perform, coeff_power, coeff_area). Efforts to optimize each of the objectives are proportional to the specified coefficients." +What environment is required for AutoTuner?,"To set up AutoTuner, make sure you have a virtual environment set up with Python 3.9.X. There are plenty of ways to do this, we recommend using Miniconda, which is a free minimal installer for the package manager conda." +Which parameters/variables can be used for tune or sweep?,Any variable that can be set from the command line can be used for tune or sweep. +How to add verilog designs to ORFS repository for a full RTL-GDS flow execution?,The following design example is based on the design spm that implements a Single-port memory using gf180 platform. This procedure applies to any design for a given platform you choose. Start from the base directory OpenROAD-flow-scripts/flow. Step 1: Create the Verilog source files directory based on the top module name. Step 2: Create config.mk to define design configuration. Step 3: Define key design parameters in config.mk. Step 4: Define SDC constraints. Step 5: Add the design name to Makefile to run the flow with the make command. +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export PLATFORM?","While designing spm that implements a Single-port memory using gf180 platform, the export PLATFORM value can be gf180." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export DESIGN_NAME?","While designing spm that implements a Single-port memory using gf180 platform, the value of the parameter, export DESIGN_NAME can be spm." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export VERILOG_FILES?","For the value of export VERILOG_FILES parameter while designing spm that implements a Single-port memory using gf180 platform, it can be $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))" +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export SDC_FILE?","The parameter, export SDC_FILE can have the value ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc while designing spm that implements a Single-port memory using gf180 platform" +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export CORE_UTILIZATION?", The value of CORE_UTILIZATION may be subjective but one value for CORE_UTILIZATION while designing spm that implements a Single-port memory using gf180 platform40 +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export PLACE_DENSITY ","The value of the parameter, export PLACE_DENSITY while designing spm that implements a Single-port memory can be 0.6." +"While designing spm that implements a Single-port memory using gf180 platform, what can be the value of the following parameter, export TNS_END_PERCENT?","The value of the parameter, export TNS_END_PERCENT while designing spm that implements a Single-port memory can be 100." +What is the function of the Environment Variables for the OpenROAD Flow Scripts?,"Environment variables are used in the OpenROAD flow to define various platform, design, and tool-specific variables to allow finer control and user overrides at various flow stages. These are defined in the config.mk file located in the platform and design-specific directories." +"What does the general variables for all stages, SKIP_REPORT_METRICS do?","The SKIP_REPORT_METRICS general variable if set to 1, then metrics, report_metrics does nothing. This is useful to speed up builds." +"Can you explain the usage of the Library Setup variable, PROCESS?","The variable, PROCESS signifies a technology node or process in use." +"What is the function of the Library Setup variable, CORNER?",This CORNER variable specifies the Library to select based on corner BC/TC/WC. +"What is the description of Library Setup variable, TECH_LEF","This variable, TECH_LEF, stipulates a technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements." +"What is the description of Library Setup variable, SC_LEF",SC_LEF is used to specify the path to the technology standard cell LEF file. +"What is the function of the Library Setup variable, GDS_FILES",GDS_FILES specifies the path to platform GDS files. +"What is the description of Library Setup variable, LIB_FILES","LIB_FILES enumerates a Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing, and power definitions for each cell." +"Can you explain the usage of the Library Setup variable, DONT_USE_CELLS?","In OpenROAD Flow Scripts, the DONT_USE_CELLS variable stores a list of cells to avoid when performing both synthesis and place & route. Basic wildcard patterns (*) are supported. You may want to mark a cell as dont_use for several reasons, including 1) some cells may have complicated pin access patterns which are more likely to cause design rule violations during detailed routing, 2) some cells may be more prone to manufacturing variation, and will cause difficulty to close timing constraints, 3) A designer may not want to use certain cells during the implementation flow." +"What does the following Synthesis variable, SYNTH_HIERARCHICAL do?","The variable SYNTH_HIERARCHICAL enables synthesis hierarchically, otherwise considered flat synthesis." +"What does the following Synthesis variable, LATCH_MAP_FILE do?",LATCH_MAP_FILE variable specifies the list of latches treated as a black box by Yosys. +"What does the following Synthesis variable, CLKGATE_MAP_FILE do?",This variable specifies a list of cells for the gating clock treated as a black box by Yosys. +"Can you explain the usage of this Synthesis variable, ADDER_MAP_FILE?",List of adders treated as a black box by Yosys. +"What does the following Synthesis variable, TIEHI_CELL_AND_PORT do?","The variable, TIEHI_CELL_AND_PORT is used to tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist." +"What does the following Synthesis variable, TIELO_CELL_AND_PORT do?",This variable is used to tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist. +"What does the following Synthesis variable, MIN_BUF_CELL_AND_PORTS do?",The MIN_BUF_CELL_AND_PORTS variable is used to insert a buffer cell to pass through wires. Used in synthesis. +"What does the following Synthesis variable, ABC_CLOCK_PERIOD_IN_PS do?","The variable, ABC_CLOCK_PERIOD_IN_PS is used to specify the clock period to be used by STA during synthesis. Default value read from constraint.sdc." +"What does the following Synthesis variable, ABC_DRIVER_CELL do?",Default driver cell used during ABC synthesis. +"What does the following Synthesis variable, ABC_LOAD_IN_FF do?","During synthesis, the set_load value specified by this, ABC_LOAD_IN_FF variable is used." +"What does the following Synthesis variable, MAX_UNGROUP_SIZE do?","For hierarchical synthesis, this variable ungroups modules of the size given by this variable." +"Tell me about the Floorplan variable, FLOORPLAN_DEF?",FLOORPLAN_DEF is used to specify the use of the DEF file to initialize floorplan. +"Elaborate on the Floorplan variable, PLACE_SITE?",Placement site for core cells defined in the technology LEF file. +"Describe the use this Floorplan variable, TAPCELL_TCL?",TAPCELL_TCL specifies the path to the Endcap and Welltie cells file. +"What is the function of the Floorplan variable, RTLMP_FLOW?","This variable, RTLMP_FLOW enables the Hierarchical RTLMP flow. By default it is disabled." +"Tell me about the Floorplan variable, MACRO_HALO?","MACRO_HALO specifies to keep out a distance from macro, in X and Y, to standard cell row." +"Tell me about the Floorplan variable, MACRO_PLACEMENT?",MACRO_PLACEMENT specifies the path of a file on how to place certain macros manually using read_macro_placement. +"Elaborate on the Floorplan variable, MACRO_PLACEMENT_TCL?",This variable specifies the path of a TCL file on how to place certain macros manually. +"Describe the Floorplan variable, MACRO_PLACE_HALO?",Horizontal /vertical halo around macros (microns). Used by automatic macro placement. +"Tell me about the Floorplan variable, MACRO_PLACE_CHANNEL?",Horizontal/vertical channel width between macros (microns). Used by automatic macro placement when RTLMP_FLOW is disabled. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro. +"Give me details on the Floorplan variable, MACRO_BLOCKAGE_HALO?",Blockage width overridden from default calculation. +"Inform me about the Floorplan variable, PDN_TCL?","This variable specifies the file path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps." +"Tell me about the Floorplan variable, MAKE_TRACKS.",MAKE_TRACKS variable outlines the Tcl file that defines adding routing tracks to a floorplan. +"What is the function of the Floorplan variable, IO_PLACER_H?",The metal layer on which to place the I/O pins horizontally (top and bottom of the die). +"Inform me about the Floorplan variable, IO_PLACER_V?",The metal layer on which to place the I/O pins vertically (sides of the die). +"Tell me about the Floorplan variable, GUI_NO_TIMING?",Skip loading timing for a faster GUI load. +"Give me a description for the following ‘Placement’ tool variable, HAS_IO_CONSTRAINTS?",Skip the initial non-IO based global placement if IO constraints are present. +"Tell me about the ‘Placement’ tool variable, CELL_PAD_IN_SITES_GLOBAL_PLACEMENT?",Cell padding on both sides in site widths to ease routability during global placement. +"What does this ‘Placement’ tool variable, CELL_PAD_IN_SITES_DETAIL_PLACEMENT do?",Cell padding on both sides in site widths to ease routability in detail placement. +"Give me a description for the following ‘Placement’ tool variable, PLACE_DENSITY?",The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread. +"What does this ‘Placement’ tool variable, PLACE_DENSITY_LB_ADDON do?",Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists. +"State the function of this OpenROAD ‘Placement’ tool variable, REPAIR_PDN_VIA_LAYER?",Remove power grid vias which generate DRC violations after detailed routing. +"Give me a description for the following OpenROAD ‘Placement’ tool variable, GLOBAL_PLACEMENT_ARGS?",Use additional tuning parameters during global placement other than default args defined in gloabl_place.tcl. +"What does this OpenROAD ‘Placement’ tool variable, ENABLE_DPO do?",Enable detail placement with improve_placement feature. +"Give me a description for the following OpenROAD ‘Placement’ tool variable, DPO_MAX_DISPLACEMENT?",Specifies how far an instance can be moved when optimizing. +"Give me a description for the following OpenROAD ‘Placement’ tool variable, GPL_TIMING_DRIVEN?","In OpenROAD Flow Scripts (ORFS), the GPL_TIMING_DRIVEN variable specifies whether the global placer (gpl) should use timing driven-placement. Timing-driven placement will cause gpl to ocassionally run static timing analysis (sta) during placement in order to determine the timing on each net. gpl will then reweight the nets based on how timing-critical they are. This process improves the timing of the netlist by decreasing the distance between timing-critical cells, but it also causes an increase in gpl runtime due to running timing analysis." +"Give me a description for the following OpenROAD ‘Placement’ tool variable, GPL_ROUTABILITY_DRIVEN?","In OpenROAD Flow Scripts (ORFS), the GPL_ROUTABILITY_DRIVEN variable specifies whether the global placer (gpl) should use routability driven-placement. Routability-driven placement will cause gpl to ocassionally run global routing (grt) during placement in order to determine routing congestion hotspots. gpl will then reweight the nets based on how congestion data. This process improves the routability of the netlist by spacing out cells in routing congested areas, but it also causes an increase in gpl runtime due to running global routing." +"Give me a description for the following OpenROAD ‘Placement’ tool variable, CAP_MARGIN?",Specifies a capacitance margin when fixing max capacitance violations. This option allow you to overfix. +"Give me a description for the following OpenROAD ‘Placement’ tool variable, SLEW_MARGIN?",Specifies a slew margin when fixing max slew violations. This option allow you to overfix. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, CTS_ARGS?",Override clock_tree_synthesis arguments +What does CTS_BUF_CELL do in ORFS?,The CTS_BUF_CELL variable sets the root buffer cell used in the clock tree during clock tree synthesis (CTS) +What is the use of the ORFS variable FILL_CELLS?,The FILL_CELLS variable holds a list of cell names to use as filler cells. Wildcard patterns (*) are supported. Fill cells are used to fill empty cell sites which aids in satisfying design rules and density rules. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, HOLD_SLACK_MARGIN?",Specifies a time margin for the slack when fixing hold violations. This option allow you to overfix. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SETUP_SLACK_MARGIN?",Specifies a time margin for the slack when fixing setup violations. +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SKIP_GATE_CLONING?",Do not use gate cloning transform to fix timing violations (default: use gate cloning) +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, SKIP_PIN_SWAP?",Do not use pin swapping as a transform to fix timing violations (default: use pin swapping) +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, TNS_END_PERCENT?","In OpenROAD Flow Scripts, the TNS_END_PERCENT variable specifies what percent of violating timing paths will be fixed during timing optimization. TNS_END_PERCENT must be a floating point value between 0-100. However, even if TNS_END_PERCENT is 0, the worst path will always be fixed. The purpose of this flag is to allow the user some control over how much runtime and logic area is spent on timing optimization, with a higher value leading to more runtime/area and a lower value leading to less runtime/area." +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, EQUIVALENCE_CHECK?","In OpenROAD Flow Scripts, the EQUIVALENCE_CHECK variable toggles whether a logical equivalence check is run after timing optimization to ensure logical correctness of the circuit. If EQUIVALENCE_CHECK is 1, the check is performed. If EQUIVALENCE_CHECK is any other value or unset, the check is not run. The default value is unset." +"What is the use of the following OpenROAD Clock Tree Synthesis (CTS) variable, REMOVE_CELLS_FOR_EQY?","In OpenROAD Flow Scripts, the REMOVE_CELLS_FOR_EQY variable sets the list of cells to remove from the verilog netlist file produced specifically for netlist equivalence checking. Netlist equivalence checking is performed with the Yosys EQY tool. Wildcard patterns (*) are supported. This variable is passed directly to write_verilog -remove_cells <>." +What does the create_power_domain command do in upf?,This command creates power domain for a group of modules. +What does the create_logic_port command do in upf?,"This command creates logic port. Direction must be specified from: in, out, inout." +What does restructuring do?,"Restructuring (the rst module) uses logic resynthesis to optimize combinational logic paths. Restructuring can be performed in either area or delay mode. Area mode will optimize the logic cell area of the paths, whereas delay mode will optimize for delay. An Area Mode Example: restructure -liberty_file ckt.lib -target area -tielo_pin ABC -tiehi_pin DEF. For Timing Mode Example: restructure -liberty_file ckt.lib -target delay -tielo_pin ABC -tiehi_pin DEF -slack_threshold 1 -depth_threshold 2." +What is the difference between Yosys and OpenROAD?,Yosys is a logic synthesis tool which is responsible for transforming register transfer-level (RTL) code into a gate-level netlist. OpenROAD is a place and route (P&R) tool which is responsible for implementing a gale-level netlist into a chip layout. Yosys is developed by the YosysHQ organization whereas OpenROAD is developed by The OpenROAD Project. OpenROAD Flow Scripts (ORFS) makes use of both of these tools (as well as KLayout) to form a full RTL-to-GDS flow. +Is there a way of knowing which instances were modified by resize command ?,"The Resizer module (rsz) can modify the netlist by inserting or removing buffers, as well as increasing or decreasing the drive strength of cells. rsz does not save a log of which instances were modified, because it would create an excessively long log file. A recommended workaround solution would be to save a layout file (such as DEF or ODB) before performing resizing, and then compare it to a layout file after resizing." +How can I improve runtime?,"In OpenROAD, the runtime of the software is directly related to 1) the modeling accuracy and 2) the circuit optimization effort. Improving runtime is usually a tradeoff of one of these two categories. If you are comfortable with reducing optimization effort, such as when performing design space exploration, you could try the following techniques: 1) Relaxing timing constraints in the SDC file, 2) skipping unnesessary optimization routines, such as setup and hold time fixing, 3) Stopping the design flow early, such as after the placement step or clock tree synthesis (CTS) step." +Why does my design take so long?,"In OpenROAD, the runtime of the design can be affected by several factors: 1) the size of the netlist. Designs with a large number of instances (100k or more) can take significantly longer than small designs. 2) the physical area of the design. Designs with large die areas (~1 mm^2 or larger) can take longer because of having to store the die size in memory. 3) improper timing constraints. Designs with excessive timing constaints can cause optimization algorithms, particularly Resizer (rsz) to take excessively long. 4) host machine constraints. Large designs can require a large amount of RAM to run. If the required memory exceeds your machine's available memory, the runtime will be significantly increased. Additionally, OpenROAD scales well with core count, so using a CPU with a greater number of cores can improve runtime." +What is DBU?,"In OpenROAD, database units (DBU) are an integer representation of distance on a chip. In the LEF/DEF format, each technology specifies a conversion factor in terms of DBU/micron. For example, if a technology used a conversion factor of 2000 DBU/micron, that would mean that each DBU represents 0.0005 micron or 0.5 nm. The purpose for using DBU is that it enables faster calculation and no loss of precision compared to floating point representations." +How do I convert from DBU?,"In OpenROAD, an integer DBU value can be converted to a floating point micron value by using the ord::dbu_to_microns function" +How to access GUI,OpenROAD's GUI can be started in two ways. One is to use the -gui flag when invoking OpenROAD from the command line (e.g. openroad -gui). The other option is to use the gui::show function from inside the openroad command interpreter. +Is there a simple way to open the GUI in ORFS?,"OpenROAD Flow Scripts (ORFS) includes Makefile targets to open the GUI after each step. You can use the command make gui_*, where * is the name of the flow step (e.g. make_floorplan)." +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, +, \ No newline at end of file diff --git a/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Question-Answer/Question-Answer_Dataset.xlsx b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Question-Answer/Question-Answer_Dataset.xlsx new file mode 100644 index 0000000..5c88adc Binary files /dev/null and b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Question-Answer/Question-Answer_Dataset.xlsx differ diff --git a/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Question-Answer/README.md b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Question-Answer/README.md new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/Question-Answer/README.md @@ -0,0 +1 @@ + diff --git a/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/README.md b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/README.md new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/Non-Augmented_Data/README.md @@ -0,0 +1 @@ + diff --git a/flow-Agent/EDA-Corpus-main/README.md b/flow-Agent/EDA-Corpus-main/README.md new file mode 100644 index 0000000..a08f7bc --- /dev/null +++ b/flow-Agent/EDA-Corpus-main/README.md @@ -0,0 +1,108 @@ +# EDA Corpus +EDA Corpus is a data corpus for Electronic Design Automation (EDA) Large Language Model (LLM) research. In particular, the datapoints are tailored to [OpenROAD](https://github.com/The-OpenROAD-Project/OpenROAD) and [OpenROAD-flow-scripts](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts). The corpus contains datasets for both question-answering and prompt-scripting for OpenROAD to improve user productivity. + +## Background +Recent works have shown that LLMs have tremendous potential in the chip design area in terms of writing code/script for hardware description language (HDL) or electronic design automation (EDA) flow. However, many of these works rely on data which are not publicly available and/or not permissively licensed for use in LLM training and distribution, especially in the EDA domain. To foster research in LLM-assisted physical design, we introduce EDA Corpus, a curated dataset for physical design automation tasks. EDA Corpus is based on OpenROAD, a widely utilized open-source EDA tool for automated place and route tasks. Leveraging OpenROAD mitigates obstacles associated with proprietary EDA tools, enabling the public release of our dataset and facilitating its use with LLMs without licensing constraints. + +## Dataset Description +EDA Corpus consists of two types of data: (1) question-answer (QA) pairs and (2) prompt-script (PS) pairs + +| **Dataset** | **Description** | **Non-augmented** | **Augmented**\* | +|--------------------|-----------------|-------------------|-----------------| +| `eda-corpus-qa-v1` | Question-answer | 198 data pairs | 590 data pairs | +| `eda-corpus-ps-v1` | Prompt-script | 395 data pairs | 943 data pairs | +| `eda-corpus-v1` | Combined QA/PS | 593 data pairs | 1533 data pairs | + +\* The augmented dataset is a superset of non-augmented + +### Question-answer (QA) dataset + - Contains pairs of question prompts and prose answers which are collected from The OpenROAD Project's GitHub issues, discussions, and documentation + - Datapoints are categorized into three categories: OpenROAD general, OpenROAD tool, and OpenROAD flow + - CSV file format and Microsoft Excel file format provided + +An example question-answer pair: +**Question:** + +***What does the SKIP_PIN_SWAP variable in Clock Tree Synthesis indicate?*** + +**Answer:** + +***Do not use pin swapping as a transform to fix timing violations (default: use pin swapping)*** + +#### Augmentation +The augmented dataset includes data pairs formed through paraphrasing questions and answers in order to enhance semantic diversity. + +### Prompt-script (PS) dataset + - Contains pairs of scripting prompts and OpenROAD Python scripts + - Data points are categorized into two three categories: flow scripts and database (DB) scripts + - CSV file format and Microsoft Excel file format provided + +While Tcl is the normal interface for OpenROAD, leveraging Python allows the reuse of pretrained LLMs for Python code generation. It is worth noting that Python code examples are significantly more prevalent, hence the focus on Python-based scripts. + +An example prompt-script pair: +**Prompt:** + +***Show me how I can read a Verilog file into OpenROAD.*** + +**Script:** + +#### Augmentation +While each augmented datapoint is distinct, the augmented points may perform similar functions with script parameter variations. For instance, the augmented set has a few instances of gate sizing, and the sizing is different between datapoints. The data is augmented through two methods: + +1. **Paraphrasing prompts**: prompts are paraphrased to increase semantic diversity. +2. **Variable and parameter changes**: pairs are duplicated with changes to the prompt parameters and script variable names. + +```python +from openroad import Tech, Design +from pathlib import Path + +tech = Tech() +# Make sure you have .lef files read into OpenROAD DB +design = Design(tech) + +designDir = Path("design_path") +design_file_name = "design_filename" +design_top_module_name = "design_top_module_name" +verilogFile = designDir/str(design_file_name + ".v") +design.readVerilog("verilogFile") +design.link(design_top_module_name) +``` + +# Citing This Work + +If you use this corpus in your work, please use the following citation: +``` +@inproceedingsV{wu2024eda, + title = {EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD}, + author = {Wu, Bing-Yue and Sharma, Utsav and Kankipati, Sai Rahul Dhanvi and Yadav, Ajay and George, Bintu Kappil and Guntupalli, Sai Ritish and Rovinski, Austin and Chhabria, Vidya A.}, + booktitle = {The First IEEE International Workshop on LLM-Aided Design (LAD'24)}, + month = {June}, + year = {2024}, + organization = {IEEE}, + address = {New York, NY} +} +``` + +## Taxonomy +The question-answer and prompt-script data should be individually referred to as "datasets". The two dataset combined should be referred to as a "corpus". + +Citations to this work can be mentioned by `corpusName-datasetName-version`: + +| **Data** | **Name** | +|------------------------------|--------------------| +| All of EDA Corpus | `eda-corpus-v1` | +| Only question-answer dataset | `eda-corpus-qa-v1` | +| Only prompt-script dataset | `eda-corpus-ps-v1` | + +Additionally, you can mention whether you use the **augmented** or **non-augmented** versions. For example, "We train on the augmented eda-corpus-ps-v1 dataset." + +## License +[![CC BY 4.0][cc-by-shield]][cc-by] + +EDA Corpus is licensed under a [Creative Commons Attribution 4.0 International License][cc-by]. If you use EDA Corpus in a published scholarly work, please use the above citation. If you use EDA Corpus in another publication such as an article or blog post, please include a link to this repository. + +[![CC BY 4.0][cc-by-image]][cc-by] + +[cc-by]: http://creativecommons.org/licenses/by/4.0/ +[cc-by-image]: https://i.creativecommons.org/l/by/4.0/88x31.png +[cc-by-shield]: https://img.shields.io/badge/License-CC%20BY%204.0-lightgrey.svg diff --git a/flow-Agent/Makefile b/flow-Agent/Makefile index c22726e..dc4ab69 100644 --- a/flow-Agent/Makefile +++ b/flow-Agent/Makefile @@ -2,31 +2,27 @@ # file to avoid having to adding the to the make command line. -include settings.mk INT_PARAM=1 +# PYTHON_EXE ?= $(shell command -v python3 || command -v python) # ============================================================================== # Uncomment or add the design to run # ============================================================================== -DESIGN_CONFIG=./designs/sky130hd/aes/config_$(INT_PARAM).mk +#DESIGN_CONFIG=./designs/sky130hd/aes/config_$(INT_PARAM).mk #DESIGN_CONFIG=./designs/sky130hd/ibex/config_$(INT_PARAM).mk #DESIGN_CONFIG=./designs/sky130hd/jpeg/config_$(INT_PARAM).mk -#DESIGN_CONFIG=./designs/asap7/aes/config_$(INT_PARAM).mk +DESIGN_CONFIG=./designs/asap7/aes/config_$(INT_PARAM).mk #DESIGN_CONFIG=./designs/asap7/ibex/config_$(INT_PARAM).mk #DESIGN_CONFIG=./designs/asap7/jpeg/config_$(INT_PARAM).mk - - +$(info Using config.mk from $(DESIGN_CONFIG)) # Default design # DESIGN_CONFIG ?= ./designs/nangate45/gcd/config.mk # Include design and platform configuration before setting default options # in this file. This allows the DESIGN_CONFIG to set different defaults than # this file. -include $(DESIGN_CONFIG) -# If we are running headless use offscreen rendering for save_image -ifeq ($(DISPLAY),) -export QT_QPA_PLATFORM ?= offscreen -endif +include $(DESIGN_CONFIG) # ============================================================================== # ____ _____ _____ _ _ ____ @@ -43,7 +39,7 @@ MAKEFLAGS += --no-builtin-rules #------------------------------------------------------------------------------- # Default target when invoking without specific target. -.DEFAULT_GOAL := finish +.DEFAULT_GOAL := all #------------------------------------------------------------------------------- # Proper way to initiate SHELL for make @@ -56,16 +52,10 @@ SHELL := /usr/bin/env bash # location # - default is current install / clone directory ifeq ($(origin FLOW_HOME), undefined) -FLOW_HOME := $(shell pwd) + FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST)))) endif export FLOW_HOME -#------------------------------------------------------------------------------- -# Setup variables to point to other location for the following sub directory -# - designs - default is under current directory -# - platforms - default is under current directory -# - work home - default is current directory -# - utils, scripts, test - default is under current directory export DESIGN_HOME ?= $(FLOW_HOME)/designs export PLATFORM_HOME ?= $(FLOW_HOME)/platforms export WORK_HOME ?= . @@ -74,170 +64,46 @@ export UTILS_DIR ?= $(FLOW_HOME)/util export SCRIPTS_DIR ?= $(FLOW_HOME)/scripts export TEST_DIR ?= $(FLOW_HOME)/test -$(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(line))) - -PUBLIC=nangate45 sky130hd sky130hs asap7 ihp-sg13g2 gf180 - -ifneq ($(wildcard $(PLATFORM_HOME)/$(PLATFORM)),) - export PLATFORM_DIR = $(PLATFORM_HOME)/$(PLATFORM) -else ifneq ($(findstring $(PLATFORM),$(PUBLIC)),) - export PLATFORM_DIR = ./platforms/$(PLATFORM) -else ifneq ($(wildcard ../../$(PLATFORM)),) - export PLATFORM_DIR = ../../$(PLATFORM) -else - $(error [ERROR][FLOW] Platform '$(PLATFORM)' not found.) -endif - -include $(PLATFORM_DIR)/config.mk - -# Enables hierarchical yosys -export SYNTH_HIERARCHICAL ?= 0 -export SYNTH_STOP_MODULE_SCRIPT = $(RESULTS_DIR)/keep_hierarchy.tcl -export HIER_REPORT_SCRIPT = $(SCRIPTS_DIR)/synth_hier_report.tcl -export MAX_UNGROUP_SIZE ?= 0 +export FLOW_VARIANT ?=base -# Enables Re-synthesis for area reclaim -export RESYNTH_AREA_RECOVER ?= 0 -export RESYNTH_TIMING_RECOVER ?= 0 -export ABC_AREA ?= 0 +include $(FLOW_HOME)/scripts/variables.mk -# User adjustable synthesis arguments -export SYNTH_ARGS ?= -flatten -# Not normally adjusted by user -export SYNTH_OPERATIONS_ARGS ?= -extra-map $(FLOW_HOME)/platforms/common/lcu_kogge_stone.v -export SYNTH_FULL_ARGS ?= $(SYNTH_ARGS) $(SYNTH_OPERATIONS_ARGS) - -# Global setting for Floorplan -export PLACE_PINS_ARGS - -export FLOW_VARIANT ?= base - -export GPL_TIMING_DRIVEN ?= 1 -export GPL_ROUTABILITY_DRIVEN ?= 1 - -# Cell padding in SITE widths to ease rout-ability. Applied to both sides -export CELL_PAD_IN_SITES_GLOBAL_PLACEMENT ?= 0 -export CELL_PAD_IN_SITES_DETAIL_PLACEMENT ?= 0 - -export ENABLE_DPO ?= 1 -export DPO_MAX_DISPLACEMENT ?= 5 1 - -# Setup working directories export DESIGN_NICKNAME ?= $(DESIGN_NAME) - export DESIGN_CONFIG + export DESIGN_DIR = $(dir $(DESIGN_CONFIG)) export LOG_DIR = $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)_$(INT_PARAM) export OBJECTS_DIR = $(WORK_HOME)/objects/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)_$(INT_PARAM) export REPORTS_DIR = $(WORK_HOME)/reports/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)_$(INT_PARAM) export RESULTS_DIR = $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)_$(INT_PARAM) +# default value "base" for FLOW_VARIANT and "." for WORK_HOME are duplicated +# from variables.yaml and variables.mk because we need it +# earlier in the flow for BLOCKS. BLOCKS is a feature specific to the +# ORFS Makefile. + +# BLOCKS is a ORFS make flow specific feature. ifneq ($(BLOCKS),) - $(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) - $(foreach block,$(BLOCKS),$(eval BLOCK_LIBS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib)) - $(foreach block,$(BLOCKS),$(eval BLOCK_GDS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds)) - $(foreach block,$(BLOCKS),$(eval BLOCK_CDL += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.cdl)) - $(foreach block,$(BLOCKS),$(eval BLOCK_LOG_FOLDERS += ./logs/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/)) + # Normally this comes from variables.yaml, but we need it here to set up these variables + # which are part of the DESIGN_CONFIG. BLOCKS is a Makefile specific concept. + $(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) + $(foreach block,$(BLOCKS),$(eval BLOCK_TYP_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_typ.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_FAST_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_fast.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_SLOW_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_slow.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_GDS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds)) + $(foreach block,$(BLOCKS),$(eval BLOCK_CDL += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.cdl)) + $(foreach block,$(BLOCKS),$(eval BLOCK_LOG_FOLDERS += $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/)) export ADDITIONAL_LEFS += $(BLOCK_LEFS) - export ADDITIONAL_LIBS += $(BLOCK_LIBS) + export ADDITIONAL_LIBS += $(BLOCK_TYP_LIBS) + export ADDITIONAL_TYP_LIBS += $(BLOCK_TYP_LIBS) + export ADDITIONAL_FAST_LIBS += $(BLOCK_FAST_LIBS) + export ADDITIONAL_SLOW_LIBS += $(BLOCK_SLOW_LIBS) export ADDITIONAL_GDS += $(BLOCK_GDS) - export GDS_FILES += $(BLOCK_GDS) ifneq ($(CDL_FILES),) export CDL_FILES += $(BLOCK_CDL) endif endif -export RTLMP_FLOW ?= 1 -export RTLMP_RPT_DIR ?= $(OBJECTS_DIR)/rtlmp -export RTLMP_RPT_FILE ?= partition.txt -export RTLMP_BLOCKAGE_FILE ?= $(OBJECTS_DIR)/rtlmp/partition.txt.blockage - -#------------------------------------------------------------------------------- -ifeq (,$(strip $(NUM_CORES))) - # Linux (utility program) - NUM_CORES := $(shell nproc 2>/dev/null) - - ifeq (,$(strip $(NUM_CORES))) - # Linux (generic) - NUM_CORES := $(shell grep -c ^processor /proc/cpuinfo 2>/dev/null) - endif - ifeq (,$(strip $(NUM_CORES))) - # BSD (at least FreeBSD and Mac OSX) - NUM_CORES := $(shell sysctl -n hw.ncpu 2>/dev/null) - endif - ifeq (,$(strip $(NUM_CORES))) - # Fallback - NUM_CORES := 1 - endif -endif -export NUM_CORES - -YOSYS_FLAGS += -v 3 - -#------------------------------------------------------------------------------- -# setup all commands used within this flow -export TIME_BIN ?= /usr/bin/time -TIME_CMD = $(TIME_BIN) -f 'Elapsed time: %E[h:]min:sec. CPU time: user %U sys %S (%P). Peak memory: %MKB.' -TIME_TEST = $(shell $(TIME_CMD) echo foo 2>/dev/null) -ifeq (,$(strip $(TIME_TEST))) - TIME_CMD = $(TIME_BIN) -endif - -# The following determine the executable location for each tool used by this flow. -# Priority is given to -# 1 user explicit set with variable in Makefile or command line, for instance setting OPENROAD_EXE -# 2 ORFS compiled tools: openroad, yosys -export OPENROAD_EXE ?= $(abspath $(FLOW_HOME)/../tools/install/OpenROAD/bin/openroad) -export OPENSTA_EXE ?= $(abspath $(FLOW_HOME)/../tools/install/OpenROAD/bin/sta) - -OPENROAD_ARGS = -no_init -threads $(NUM_CORES) $(OR_ARGS) -OPENROAD_CMD = $(OPENROAD_EXE) -exit $(OPENROAD_ARGS) -OPENROAD_NO_EXIT_CMD = $(OPENROAD_EXE) $(OPENROAD_ARGS) -OPENROAD_GUI_CMD = $(OPENROAD_EXE) -gui $(OR_ARGS) - -YOSYS_EXE ?= $(abspath $(FLOW_HOME)/../tools/install/yosys/bin/yosys) - -# Use locally installed and built klayout if it exists, otherwise use klayout in path -KLAYOUT_DIR = $(abspath $(FLOW_HOME)/../tools/install/klayout/) -KLAYOUT_BIN_FROM_DIR = $(KLAYOUT_DIR)/klayout - -ifeq ($(wildcard $(KLAYOUT_BIN_FROM_DIR)), $(KLAYOUT_BIN_FROM_DIR)) -KLAYOUT_CMD ?= sh -c 'LD_LIBRARY_PATH=$(dir $(KLAYOUT_BIN_FROM_DIR)) $$0 "$$@"' $(KLAYOUT_BIN_FROM_DIR) -else -ifeq ($(KLAYOUT_CMD),) -KLAYOUT_CMD := $(shell command -v klayout) -endif -endif -KLAYOUT_FOUND = $(if $(KLAYOUT_CMD),,$(error KLayout not found in PATH)) - -ifneq ($(shell command -v stdbuf),) - STDBUF_CMD ?= stdbuf -o L -endif - -#------------------------------------------------------------------------------- -WRAPPED_LEFS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/lef/$(lef:.lef=_mod.lef)) -WRAPPED_LIBS = $(foreach lib,$(notdir $(WRAP_LIBS)),$(OBJECTS_DIR)/$(lib:.lib=_mod.lib)) -export ADDITIONAL_LEFS += $(WRAPPED_LEFS) $(WRAP_LEFS) -export LIB_FILES += $(WRAP_LIBS) $(WRAPPED_LIBS) - -export DONT_USE_LIBS = $(patsubst %.lib.gz, %.lib, $(addprefix $(OBJECTS_DIR)/lib/, $(notdir $(LIB_FILES)))) -export DONT_USE_SC_LIB ?= $(firstword $(DONT_USE_LIBS)) - -# Stream system used for final result (GDS is default): GDS, GSDII, GDS2, OASIS, or OAS -STREAM_SYSTEM ?= GDS -ifneq ($(findstring GDS,$(shell echo $(STREAM_SYSTEM) | tr '[:lower:]' '[:upper:]')),) - export STREAM_SYSTEM_EXT := gds - GDSOAS_FILES = $(GDS_FILES) - ADDITIONAL_GDSOAS = $(ADDITIONAL_GDS) - SEAL_GDSOAS = $(SEAL_GDS) -else - export STREAM_SYSTEM_EXT := oas - GDSOAS_FILES = $(OAS_FILES) - ADDITIONAL_GDSOAS = $(ADDITIONAL_OAS) - SEAL_GDSOAS = $(SEAL_OAS) -endif -export WRAPPED_GDSOAS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/$(lef:.lef=_mod.$(STREAM_SYSTEM_EXT))) - define GENERATE_ABSTRACT_RULE ifeq ($(wildcard $(3)),) # There is no unique config.mk for this module, use the shared @@ -260,40 +126,10 @@ endef # Targets to harden Blocks in case of hierarchical flow is triggered .PHONY: build_macros -build_macros: $(BLOCK_LEFS) $(BLOCK_LIBS) - -$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk))) -$(foreach block,$(BLOCKS),$(eval ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds: ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) - -# Utility to print tool version information -#------------------------------------------------------------------------------- -.PHONY: versions.txt -versions.txt: - mkdir -p $(OBJECTS_DIR) - @if [ -z "$(YOSYS_EXE)" ]; then \ - echo >> $(OBJECTS_DIR)/$@ "yosys not installed"; \ - else \ - $(YOSYS_EXE) -V > $(OBJECTS_DIR)/$@; \ - fi - @echo openroad `$(OPENROAD_EXE) -version` >> $(OBJECTS_DIR)/$@ - @if [ -z "$(KLAYOUT_CMD)" ]; then \ - echo >> $(OBJECTS_DIR)/$@ "klayout not installed"; \ - else \ - $(KLAYOUT_CMD) -zz -v >> $(OBJECTS_DIR)/$@; \ - fi - -# Pre-process libraries -# ============================================================================== - -# Create temporary Liberty files which have the proper dont_use properties set -# For use with Yosys and ABC -.SECONDEXPANSION: -$(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES)) - @mkdir -p $(OBJECTS_DIR)/lib - $(UTILS_DIR)/preprocessLib.py -i $^ -o $@ +build_macros: $(BLOCK_LEFS) $(BLOCK_TYP_LIBS) -$(OBJECTS_DIR)/lib/merged.lib: - $(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@ +$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_typ.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk))) +$(foreach block,$(BLOCKS),$(eval $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds: $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) # Pre-process KLayout tech # ============================================================================== @@ -305,25 +141,13 @@ do-klayout_tech: @mkdir -p $(OBJECTS_DIR) cp $(TECH_LEF) $(OBJECTS_DIR)/klayout_tech.lef -KLAYOUT_ENV_VAR_IN_PATH_VERSION = 0.28.11 -KLAYOUT_VERSION := $(if $(KLAYOUT_CMD),$(shell $(KLAYOUT_CMD) -v 2>/dev/null | grep 'KLayout' | cut -d ' ' -f2),) - -KLAYOUT_ENV_VAR_IN_PATH = $(shell \ - if [ -z "$(KLAYOUT_VERSION)" ]; then \ - echo "not_found"; \ - elif [ "$$(echo -e "$(KLAYOUT_VERSION)\n$(KLAYOUT_ENV_VAR_IN_PATH_VERSION)" | sort -V | head -n1)" = "$(KLAYOUT_VERSION)" ] && [ "$(KLAYOUT_VERSION)" != "$(KLAYOUT_ENV_VAR_IN_PATH_VERSION)" ]; then \ - echo "invalid"; \ - else \ - echo "valid"; \ - fi) - $(OBJECTS_DIR)/klayout.lyt: $(KLAYOUT_TECH_FILE) $(OBJECTS_DIR)/klayout_tech.lef $(UNSET_AND_MAKE) do-klayout .PHONY: do-klayout do-klayout: ifeq ($(KLAYOUT_ENV_VAR_IN_PATH),valid) - SC_LEF_RELATIVE_PATH="$$\(env('FLOW_HOME')\)/$(shell realpath --relative-to=$(FLOW_HOME) $(SC_LEF))"; \ + SC_LEF_RELATIVE_PATH="$(shell realpath --relative-to=$(RESULTS_DIR) $(SC_LEF))"; \ OTHER_LEFS_RELATIVE_PATHS=$$(echo "$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(ADDITIONAL_LEFS),$$(realpath --relative-to=$(RESULTS_DIR) $(file)))"); \ sed 's,.*,'"$$SC_LEF_RELATIVE_PATH"''"$$OTHER_LEFS_RELATIVE_PATHS"',g' $(KLAYOUT_TECH_FILE) > $(OBJECTS_DIR)/klayout.lyt else @@ -338,12 +162,6 @@ $(OBJECTS_DIR)/klayout_wrap.lyt: $(KLAYOUT_TECH_FILE) $(OBJECTS_DIR)/klayout_tec do-klayout_wrap: sed 's,.*,$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(WRAP_LEFS),$(shell realpath --relative-to=$(OBJECTS_DIR)/def $(file))),g' $(KLAYOUT_TECH_FILE) > $(OBJECTS_DIR)/klayout_wrap.lyt -# Create Macro wrappers (if necessary) -# ============================================================================== -WRAP_CFG = $(PLATFORM_DIR)/wrapper.cfg - - -export TCLLIBPATH := util/cell-veneer $(TCLLIBPATH) $(WRAPPED_LEFS): mkdir -p $(OBJECTS_DIR)/lef $(OBJECTS_DIR)/def util/cell-veneer/wrap.tcl -cfg $(WRAP_CFG) -macro $(filter %$(notdir $(@:_mod.lef=.lef)),$(WRAP_LEFS)) @@ -362,8 +180,7 @@ $(WRAPPED_LIBS): # |____/ |_| |_| \_| |_| |_| |_|_____|____/___|____/ # .PHONY: synth -synth: $(RESULTS_DIR)/1_synth.v \ - $(RESULTS_DIR)/1_synth.sdc +synth: $(RESULTS_DIR)/1_synth.v .PHONY: synth-report synth-report: synth @@ -371,11 +188,14 @@ synth-report: synth .PHONY: do-synth-report do-synth-report: - ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/synth_metrics.tcl) 2>&1 | tee $(LOG_DIR)/1_1_yosys_metrics.log + ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/synth_metrics.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/1_2_yosys_metrics.log) .PHONY: memory memory: - python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem.json + if [ -f $(RESULTS_DIR)/mem_hierarchical.json ]; then \ + $(PYTHON_EXE) $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem_hierarchical.json; \ + fi + $(PYTHON_EXE) $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem.json # ============================================================================== @@ -383,65 +203,42 @@ memory: # Run Synthesis using yosys #------------------------------------------------------------------------------- -export SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl -export SYNTH_MEMORY_MAX_BITS ?= 4096 - -.PHONY: do-yosys-keep-hierarchy -do-yosys-keep-hierarchy: - mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) - (export VERILOG_FILES=$(RESULTS_DIR)/1_synth.rtlil; \ - $(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(HIER_REPORT_SCRIPT)) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_hier_report.log) - -export SDC_FILE_CLOCK_PERIOD = $(RESULTS_DIR)/clock_period.txt - $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE) mkdir -p $(dir $@) echo $(ABC_CLOCK_PERIOD_IN_PS) > $@ -YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(DFF_LIB_FILE) $(VERILOG_FILES) $(CACHED_NETLIST) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD) - .PHONY: yosys-dependencies yosys-dependencies: $(YOSYS_DEPENDENCIES) .PHONY: do-yosys -do-yosys: - mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR) - (export VERILOG_FILES=$(RESULTS_DIR)/1_synth.rtlil; \ - $(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SYNTH_SCRIPT)) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys.log) +do-yosys: yosys-dependencies + $(SCRIPTS_DIR)/synth.sh $(SYNTH_SCRIPT) $(LOG_DIR)/1_2_yosys.log .PHONY: do-yosys-canonicalize do-yosys-canonicalize: yosys-dependencies - mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR) - # NOTE! YOSYS_FLAGS is omitted here because "-v 3" silences helpful error messages - ($(TIME_CMD) $(YOSYS_EXE) -c $(SCRIPTS_DIR)/synth_canonicalize.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_canonicalize.log) + $(SCRIPTS_DIR)/synth.sh $(SCRIPTS_DIR)/synth_canonicalize.tcl $(LOG_DIR)/1_1_yosys_canonicalize.log -$(RESULTS_DIR)/1_synth.rtlil: $(YOSYS_DEPENDENCIES) +$(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil: $(YOSYS_DEPENDENCIES) $(UNSET_AND_MAKE) do-yosys-canonicalize -$(RESULTS_DIR)/1_1_yosys.v: $(RESULTS_DIR)/1_synth.rtlil - $(UNSET_AND_MAKE) do-yosys-keep-hierarchy do-yosys - -$(RESULTS_DIR)/1_synth.sdc: $(SDC_FILE) - mkdir -p $(RESULTS_DIR) - cp $(SDC_FILE) $(RESULTS_DIR)/1_synth.sdc +$(RESULTS_DIR)/1_2_yosys.v: $(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil + $(UNSET_AND_MAKE) do-yosys .PHONY: do-synth do-synth: mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) - cp $(RESULTS_DIR)/1_1_yosys.v $(RESULTS_DIR)/1_synth.v + cp $(RESULTS_DIR)/1_2_yosys.v $(RESULTS_DIR)/1_synth.v -$(RESULTS_DIR)/1_synth.v: $(RESULTS_DIR)/1_1_yosys.v +$(RESULTS_DIR)/1_synth.v: $(RESULTS_DIR)/1_2_yosys.v $(UNSET_AND_MAKE) do-synth .PHONY: clean_synth clean_synth: - rm -f $(RESULTS_DIR)/1_* $(RESULTS_DIR)/mem.json + rm -f $(RESULTS_DIR)/1_* $(RESULTS_DIR)/mem*.json rm -f $(REPORTS_DIR)/synth_* rm -f $(LOG_DIR)/1_* - rm -f $(SYNTH_STOP_MODULE_SCRIPT) + rm -f $(SYNTH_STATS) rm -f $(SDC_FILE_CLOCK_PERIOD) - rm -rf _tmp_yosys-abc-* - # ============================================================================== # _____ _ ___ ___ ____ ____ _ _ _ _ @@ -456,12 +253,6 @@ floorplan: $(RESULTS_DIR)/2_floorplan.odb \ # ============================================================================== -ifneq ($(FOOTPRINT),) -IS_CHIP = 1 -else ifneq ($(FOOTPRINT_TCL),) -IS_CHIP = 1 -endif - UNSET_VARS = for var in $(UNSET_VARIABLES_NAMES); do unset $$var; done # FILE_MAKEFILE is needed when ORFS is invoked with @@ -485,11 +276,16 @@ open_$(1): open_$(2) endef define OPEN_GUI -.PHONY: $(1)_$(2) -$(1)_$(2): - $(3)=$(RESULTS_DIR)/$(2) $(4) $(SCRIPTS_DIR)/gui.tcl +.PHONY: open_$(1) gui_$(1) +open_$(1): + $(2)=$(RESULTS_DIR)/$(1) $(OPENROAD_NO_EXIT_CMD) $(SCRIPTS_DIR)/open.tcl +gui_$(1): + $(2)=$(RESULTS_DIR)/$(1) $(OPENROAD_GUI_CMD) $(SCRIPTS_DIR)/open.tcl endef +# Enables "make gui_5_1_grt-failed" +$(eval $(call OPEN_GUI_SHORTCUT,5_1_grt-failed,5_1_grt-failed.odb)) + # Separate dependency checking and doing a step. This can # be useful to retest a stage without having to delete the # target, or when building a wafer thin layer on top of @@ -528,6 +324,7 @@ endif .PHONY: do-$(1) do-$(1): $(OBJECTS_DIR)/copyright.txt + $(SCRIPTS_DIR)/flow.sh $(1) $(3) @mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR) @echo Running $(3).tcl, stage $(1) @(set -eo pipefail; \ @@ -542,7 +339,7 @@ endef # # The file is copied within the $(RESULTS_DIR) # -# $(1) stem of target, e.g. 2_2_floorplan_io +# $(1) stem of target, e.g. 2_1_floorplan # $(2) basename of file to be copied # $(3) further dependencies # $(4) target extension, default .odb @@ -555,36 +352,31 @@ do-$(1)$(if $(4),$(4),): cp $(RESULTS_DIR)/$(2) $(RESULTS_DIR)/$(1)$(if $(4),$(4),.odb) endef +$(eval $(call do-step,1_3_synth,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc,synth_odb)) -# STEP 1: Translate verilog to odb -#------------------------------------------------------------------------------- -$(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL),floorplan)) +$(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL) $(LIB_FILES) $(IO_CONSTRAINTS),floorplan)) -$(eval $(call do-step,2_2_floorplan_io,$(RESULTS_DIR)/2_1_floorplan.odb $(IO_CONSTRAINTS),io_placement_random)) +$(eval $(call do-copy,2_floorplan,2_1_floorplan.sdc,,.sdc)) -# STEP 3: Timing Driven Mixed Sized Placement +# STEP 2: Macro Placement #------------------------------------------------------------------------------- -$(eval $(call do-step,2_3_floorplan_tdms,$(RESULTS_DIR)/2_2_floorplan_io.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(LIB_FILES),tdms_place)) +$(eval $(call do-step,2_2_floorplan_macro,$(RESULTS_DIR)/2_1_floorplan.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(MACRO_PLACEMENT) $(MACRO_PLACEMENT_TCL),macro_place)) -# STEP 4: Macro Placement +# STEP 3: Tapcell and Welltie insertion #------------------------------------------------------------------------------- -$(eval $(call do-step,2_4_floorplan_macro,$(RESULTS_DIR)/2_3_floorplan_tdms.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(MACRO_PLACEMENT) $(MACRO_PLACEMENT_TCL),macro_place)) +$(eval $(call do-step,2_3_floorplan_tapcell,$(RESULTS_DIR)/2_2_floorplan_macro.odb $(TAPCELL_TCL),tapcell)) -# STEP 5: Tapcell and Welltie insertion +# STEP 4: PDN generation #------------------------------------------------------------------------------- -$(eval $(call do-step,2_5_floorplan_tapcell,$(RESULTS_DIR)/2_4_floorplan_macro.odb $(TAPCELL_TCL),tapcell)) +$(eval $(call do-step,2_4_floorplan_pdn,$(RESULTS_DIR)/2_3_floorplan_tapcell.odb $(PDN_TCL),pdn)) -# STEP 6: PDN generation -#------------------------------------------------------------------------------- -$(eval $(call do-step,2_6_floorplan_pdn,$(RESULTS_DIR)/2_5_floorplan_tapcell.odb $(PDN_TCL),pdn)) - -$(eval $(call do-copy,2_floorplan,2_6_floorplan_pdn.odb,)) +$(eval $(call do-copy,2_floorplan,2_4_floorplan_pdn.odb,)) $(RESULTS_DIR)/2_floorplan.sdc: $(RESULTS_DIR)/2_1_floorplan.odb .PHONY: do-floorplan do-floorplan: - $(UNSET_AND_MAKE) do-2_1_floorplan do-2_2_floorplan_io do-2_3_floorplan_tdms do-2_4_floorplan_macro do-2_5_floorplan_tapcell do-2_6_floorplan_pdn do-2_floorplan + $(UNSET_AND_MAKE) do-2_1_floorplan do-2_2_floorplan_macro do-2_3_floorplan_tapcell do-2_4_floorplan_pdn do-2_floorplan do-2_floorplan.sdc .PHONY: clean_floorplan clean_floorplan: @@ -607,7 +399,7 @@ place: $(RESULTS_DIR)/3_place.odb \ #------------------------------------------------------------------------------- $(eval $(call do-step,3_1_place_gp_skip_io,$(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/2_floorplan.sdc $(LIB_FILES),global_place_skip_io)) -$(eval $(call do-step,3_2_place_iop,$(RESULTS_DIR)/3_1_place_gp_skip_io.odb $(IO_CONSTRAINTS),io_placement)) +$(eval $(call do-step,3_2_place_iop,$(RESULTS_DIR)/3_1_place_gp_skip_io.odb,io_placement)) # STEP 3: Global placement with placed IOs, timing-driven, and routability-driven. #------------------------------------------------------------------------------- @@ -633,6 +425,12 @@ $(eval $(call do-copy,3_place,2_floorplan.sdc,,.sdc)) do-place: $(UNSET_AND_MAKE) do-3_1_place_gp_skip_io do-3_2_place_iop do-3_3_place_gp do-3_4_place_resized do-3_5_place_dp do-3_place do-3_place.sdc +# Custom repair_timing target after placement +$(eval $(call do-step,3_6_place_repair_timing,$(RESULTS_DIR)/3_5_place_dp.odb $(RESULTS_DIR)/3_place.sdc,repair_timing_post_place)) + +.PHONY: place_repair_timing +place_repair_timing: $(RESULTS_DIR)/3_6_place_repair_timing.odb + # Clean Targets #------------------------------------------------------------------------------- .PHONY: clean_place @@ -686,7 +484,8 @@ clean_cts: route: $(RESULTS_DIR)/5_route.odb \ $(RESULTS_DIR)/5_route.sdc -.PHONY: grt +.PHONY: grt globalroute +globalroute: grt grt: $(RESULTS_DIR)/5_1_grt.odb # ============================================================================== @@ -694,7 +493,7 @@ grt: $(RESULTS_DIR)/5_1_grt.odb # STEP 1: Run global route #------------------------------------------------------------------------------- -$(eval $(call do-step,5_1_grt,$(RESULTS_DIR)/4_cts.odb $(FASTROUTE_TCL) $(PRE_GLOBAL_ROUTE),global_route)) +$(eval $(call do-step,5_1_grt,$(RESULTS_DIR)/4_cts.odb $(FASTROUTE_TCL) $(PRE_GLOBAL_ROUTE_TCL),global_route)) # STEP 2: Run detailed route #------------------------------------------------------------------------------- @@ -704,16 +503,18 @@ $(eval $(call do-step,5_3_fillcell,$(RESULTS_DIR)/5_2_route.odb,fillcell)) $(eval $(call do-copy,5_route,5_3_fillcell.odb)) -$(eval $(call do-copy,5_route,4_cts.sdc,,.sdc)) +$(eval $(call do-copy,5_route,5_1_grt.sdc,,.sdc)) .PHONY: do-route do-route: $(UNSET_AND_MAKE) do-5_1_grt do-5_2_route do-5_3_fillcell do-5_route do-5_route.sdc +.PHONY: do-grt +do-grt: + $(UNSET_AND_MAKE) do-5_1_grt + .PHONY: clean_route clean_route: - rm -rf output*/ results*.out.dmp layer_*.mps - rm -rf *.gdid *.log *.met *.sav *.res.dmp rm -rf $(RESULTS_DIR)/route.guide $(RESULTS_DIR)/output_guide.mod $(RESULTS_DIR)/updated_clks.sdc rm -rf $(RESULTS_DIR)/5_*.odb $(RESULTS_DIR)/5_route.sdc $(RESULTS_DIR)/5_*.def $(RESULTS_DIR)/5_*.v rm -f $(REPORTS_DIR)/5_* @@ -721,16 +522,14 @@ clean_route: .PHONY: klayout_tr_rpt klayout_tr_rpt: $(RESULTS_DIR)/5_route.def $(OBJECTS_DIR)/klayout.lyt - $(call KLAYOUT_FOUND) - $(KLAYOUT_CMD) -rd in_drc="$(REPORTS_DIR)/5_route_drc.rpt" \ + $(SCRIPTS_DIR)/klayout.sh -rd in_drc="$(REPORTS_DIR)/5_route_drc.rpt" \ -rd in_def="$<" \ -rd tech_file=$(OBJECTS_DIR)/klayout.lyt \ -rm $(UTILS_DIR)/viewDrc.py .PHONY: klayout_guides klayout_guides: $(RESULTS_DIR)/5_route.def $(OBJECTS_DIR)/klayout.lyt - $(call KLAYOUT_FOUND) - $(KLAYOUT_CMD) -rd in_guide="$(RESULTS_DIR)/route.guide" \ + $(SCRIPTS_DIR)/klayout.sh -rd in_guide="$(RESULTS_DIR)/route.guide" \ -rd in_def="$<" \ -rd net_name=$(GUIDE_NET) \ -rd tech_file=$(OBJECTS_DIR)/klayout.lyt \ @@ -743,7 +542,7 @@ klayout_guides: $(RESULTS_DIR)/5_route.def $(OBJECTS_DIR)/klayout.lyt # | _| | || |\ || | ___) | _ || || |\ | |_| | # |_| |___|_| \_|___|____/|_| |_|___|_| \_|\____| # -GDS_FINAL_FILE = $(RESULTS_DIR)/6_final.$(STREAM_SYSTEM_EXT) + .PHONY: finish finish: $(LOG_DIR)/6_report.log \ $(RESULTS_DIR)/6_final.v \ @@ -758,12 +557,12 @@ tunereport: $(LOG_DIR)/6_report.log \ .PHONY: elapsed elapsed: - -@$(UTILS_DIR)/genElapsedTime.py -d $(BLOCK_LOG_FOLDERS) $(LOG_DIR) + -@$(PYTHON_EXE) $(UTILS_DIR)/genElapsedTime.py -d $(BLOCK_LOG_FOLDERS) $(LOG_DIR) # Useful when working with macros, see elapsed time for all macros in platform .PHONY: elapsed-all elapsed-all: - @$(UTILS_DIR)/genElapsedTime.py -d $(shell find $(WORK_HOME)/logs/$(PLATFORM)/*/*/ -type d) + @$(PYTHON_EXE) $(UTILS_DIR)/genElapsedTime.py -d $(shell find $(WORK_HOME)/logs/$(PLATFORM)/*/*/ -type d) $(eval $(call do-step,6_1_fill,$(RESULTS_DIR)/5_route.odb $(RESULTS_DIR)/5_route.sdc $(FILL_CONFIG),density_fill)) @@ -795,7 +594,7 @@ generate_abstract: $(RESULTS_DIR)/6_final.gds $(RESULTS_DIR)/6_final.def $(RESU .PHONY: do-generate_abstract do-generate_abstract: mkdir -p $(LOG_DIR) $(REPORTS_DIR) - ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/generate_abstract.tcl -metrics $(LOG_DIR)/generate_abstract.json) 2>&1 | tee $(LOG_DIR)/generate_abstract.log + ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/generate_abstract.tcl -metrics $(LOG_DIR)/generate_abstract.json) 2>&1 | tee $(abspath $(LOG_DIR)/generate_abstract.log) .PHONY: clean_abstract clean_abstract: @@ -804,8 +603,7 @@ clean_abstract: # Merge wrapped macros using Klayout #------------------------------------------------------------------------------- $(WRAPPED_GDSOAS): $(OBJECTS_DIR)/klayout_wrap.lyt $(WRAPPED_LEFS) - $(call KLAYOUT_FOUND) - ($(TIME_CMD) $(KLAYOUT_CMD) -zz -rd design_name=$(basename $(notdir $@)) \ + ($(TIME_CMD) $(SCRIPTS_DIR)/klayout.sh -zz -rd design_name=$(basename $(notdir $@)) \ -rd in_def=$(OBJECTS_DIR)/def/$(notdir $(@:$(STREAM_SYSTEM_EXT)=def)) \ -rd in_files="$(ADDITIONAL_GDSOAS)" \ -rd config_file=$(FILL_CONFIG) \ @@ -813,25 +611,23 @@ $(WRAPPED_GDSOAS): $(OBJECTS_DIR)/klayout_wrap.lyt $(WRAPPED_LEFS) -rd out_file=$@ \ -rd tech_file=$(OBJECTS_DIR)/klayout_wrap.lyt \ -rd layer_map=$(GDS_LAYER_MAP) \ - -r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(LOG_DIR)/6_merge_$(basename $(notdir $@)).log + -r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(abspath $(LOG_DIR)/6_merge_$(basename $(notdir $@)).log) # Merge GDS using Klayout #------------------------------------------------------------------------------- -GDS_MERGED_FILE = $(RESULTS_DIR)/6_1_merged.$(STREAM_SYSTEM_EXT) $(GDS_MERGED_FILE): $(RESULTS_DIR)/6_final.def $(OBJECTS_DIR)/klayout.lyt $(GDSOAS_FILES) $(WRAPPED_GDSOAS) $(SEAL_GDSOAS) $(UNSET_AND_MAKE) do-gds-merged .PHONY: do-gds-merged do-gds-merged: - $(call KLAYOUT_FOUND) - ($(TIME_CMD) $(STDBUF_CMD) $(KLAYOUT_CMD) -zz -rd design_name=$(DESIGN_NAME) \ + ($(TIME_CMD) $(STDBUF_CMD) $(SCRIPTS_DIR)/klayout.sh -zz -rd design_name=$(DESIGN_NAME) \ -rd in_def=$(RESULTS_DIR)/6_final.def \ -rd in_files="$(GDSOAS_FILES) $(WRAPPED_GDSOAS)" \ -rd seal_file="$(SEAL_GDSOAS)" \ -rd out_file=$(GDS_MERGED_FILE) \ -rd tech_file=$(OBJECTS_DIR)/klayout.lyt \ -rd layer_map=$(GDS_LAYER_MAP) \ - -r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(LOG_DIR)/6_1_merge.log + -r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(abspath $(LOG_DIR)/6_1_merge.log) $(RESULTS_DIR)/6_final.v: $(LOG_DIR)/6_report.log @@ -848,10 +644,9 @@ drc: $(REPORTS_DIR)/6_drc.lyrdb $(REPORTS_DIR)/6_drc.lyrdb: $(GDS_FINAL_FILE) $(KLAYOUT_DRC_FILE) ifneq ($(KLAYOUT_DRC_FILE),) - $(call KLAYOUT_FOUND) - ($(TIME_CMD) $(KLAYOUT_CMD) -zz -rd in_gds="$<" \ + ($(TIME_CMD) $(SCRIPTS_DIR)/klayout.sh -zz -rd in_gds="$<" \ -rd report_file=$(abspath $@) \ - -r $(KLAYOUT_DRC_FILE)) 2>&1 | tee $(LOG_DIR)/6_drc.log + -r $(KLAYOUT_DRC_FILE)) 2>&1 | tee $(abspath $(LOG_DIR)/6_drc.log) # Hacky way of getting DRV count (don't error on no matches) grep -c "" $@ > $(REPORTS_DIR)/6_drc_count.rpt || [[ $$? == 1 ]] else @@ -859,7 +654,7 @@ else endif $(RESULTS_DIR)/6_final.cdl: $(RESULTS_DIR)/6_final.v - ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/cdl.tcl) 2>&1 | tee $(LOG_DIR)/6_cdl.log + ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/cdl.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/6_cdl.log) $(OBJECTS_DIR)/6_final_concat.cdl: $(RESULTS_DIR)/6_final.cdl $(CDL_FILE) cat $^ > $@ @@ -869,11 +664,10 @@ lvs: $(RESULTS_DIR)/6_lvs.lvsdb $(RESULTS_DIR)/6_lvs.lvsdb: $(GDS_FINAL_FILE) $(KLAYOUT_LVS_FILE) $(OBJECTS_DIR)/6_final_concat.cdl ifneq ($(KLAYOUT_LVS_FILE),) - $(call KLAYOUT_FOUND) - ($(TIME_CMD) $(KLAYOUT_CMD) -b -rd in_gds="$<" \ + ($(TIME_CMD) $(SCRIPTS_DIR)/klayout.sh -b -rd in_gds="$<" \ -rd cdl_file=$(abspath $(OBJECTS_DIR)/6_final_concat.cdl) \ -rd report_file=$(abspath $@) \ - -r $(KLAYOUT_LVS_FILE)) 2>&1 | tee $(LOG_DIR)/6_lvs.log + -r $(KLAYOUT_LVS_FILE)) 2>&1 | tee $(abspath $(LOG_DIR)/6_lvs.log) else echo "LVS not supported on this platform" > $@ endif @@ -894,8 +688,22 @@ clean_finish: # # ============================================================================== +.PHONY: check-openroad +check-openroad: + @if [ "$(strip $(OPENROAD_IS_VALID))" != "true" ]; then \ + echo "OPENROAD_EXE is set to '$(OPENROAD_EXE)', but it is either not found or not executable."; \ + exit 1; \ + fi + +.PHONY: check-yosys +check-yosys: + @if [ "$(strip $(YOSYS_IS_VALID))" != "true" ]; then \ + echo "YOSYS_EXE is set to '$(YOSYS_EXE)', but it is either not found or not executable."; \ + exit 1; \ + fi + .PHONY: all -all: synth floorplan place cts route finish +all: check-yosys check-openroad synth floorplan place cts route finish .PHONY: clean clean: @@ -909,34 +717,21 @@ clean: clean_all: clean_synth clean_floorplan clean_place clean_cts clean_route clean_finish clean_metadata clean_abstract rm -rf $(OBJECTS_DIR) +clean_metadata: + @echo "clean_metadata: nothing to clean." + .PHONY: nuke nuke: clean_test clean_issues - rm -rf ./results ./logs ./reports ./objects - rm -rf layer_*.mps macrocell.list *best.plt *_pdn.def - rm -rf *.rpt *.rpt.old *.def.v pin_dumper.log - rm -f $(OBJECTS_DIR)/versions.txt $(OBJECTS_DIR)/copyright.txt dummy.guide - -.PHONY: vars -vars: - $(UTILS_DIR)/generate-vars.sh vars + rm -rf $(WORK_HOME)/results $(WORK_HOME)/logs $(WORK_HOME)/reports $(WORK_HOME)/objects + rm -f $(OBJECTS_DIR)/copyright.txt # DEF/GDS/OAS viewer shortcuts #------------------------------------------------------------------------------- -RESULTS_ODB = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.odb))) -RESULTS_DEF = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.def))) -RESULTS_GDS = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.gds))) -RESULTS_OAS = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.oas))) .PHONY: $(foreach file,$(RESULTS_DEF) $(RESULTS_GDS) $(RESULTS_OAS),klayout_$(file)) $(foreach file,$(RESULTS_DEF) $(RESULTS_GDS) $(RESULTS_OAS),klayout_$(file)): klayout_%: $(OBJECTS_DIR)/klayout.lyt - $(KLAYOUT_CMD) -nn $(OBJECTS_DIR)/klayout.lyt $(RESULTS_DIR)/$* - -.PHONY: gui_synth -gui_synth: - $(OPENROAD_GUI_CMD) $(SCRIPTS_DIR)/sta-synth.tcl -.PHONY: open_synth -open_synth: - $(OPENROAD_NO_EXIT_CMD) $(SCRIPTS_DIR)/sta-synth.tcl + $(SCRIPTS_DIR)/klayout.sh -nn $(OBJECTS_DIR)/klayout.lyt $(RESULTS_DIR)/$* +$(eval $(call OPEN_GUI_SHORTCUT,synth,1_synth.odb)) $(eval $(call OPEN_GUI_SHORTCUT,floorplan,2_floorplan.odb)) $(eval $(call OPEN_GUI_SHORTCUT,place,3_place.odb)) $(eval $(call OPEN_GUI_SHORTCUT,cts,4_cts.odb)) @@ -944,10 +739,8 @@ $(eval $(call OPEN_GUI_SHORTCUT,route,5_route.odb)) $(eval $(call OPEN_GUI_SHORTCUT,grt,5_1_grt.odb)) $(eval $(call OPEN_GUI_SHORTCUT,final,6_final.odb)) -$(foreach file,$(RESULTS_DEF),$(eval $(call OPEN_GUI,gui,$(file),DEF_FILE,$(OPENROAD_GUI_CMD)))) -$(foreach file,$(RESULTS_ODB),$(eval $(call OPEN_GUI,gui,$(file),ODB_FILE,$(OPENROAD_GUI_CMD)))) -$(foreach file,$(RESULTS_DEF),$(eval $(call OPEN_GUI,open,$(file),DEF_FILE,$(OPENROAD_NO_EXIT_CMD)))) -$(foreach file,$(RESULTS_ODB),$(eval $(call OPEN_GUI,open,$(file),ODB_FILE,$(OPENROAD_NO_EXIT_CMD)))) +$(foreach file,$(RESULTS_DEF),$(eval $(call OPEN_GUI,$(file),DEF_FILE))) +$(foreach file,$(RESULTS_ODB),$(eval $(call OPEN_GUI,$(file),ODB_FILE))) # Write a def for the corresponding odb $(foreach file,$(RESULTS_ODB),$(file).def): %.def: @@ -977,23 +770,14 @@ all_verilog : $(foreach file,$(RESULTS_ODB),$(file).v) .PHONY: handoff handoff : all_defs all_verilog -.PHONY: print-% -# Print any variable, for instance: make print-DIE_AREA -print-% : ; @echo "$* = $($*)" - .PHONY: test-unset-and-make-% test-unset-and-make-%: ; $(UNSET_AND_MAKE) $* .phony: klayout klayout: - $(KLAYOUT_CMD) + $(SCRIPTS_DIR)/klayout.sh .phony: run run: - $(OPENROAD_CMD) -no_splash $(RUN_SCRIPT) - -# Utilities -#------------------------------------------------------------------------------- -include $(UTILS_DIR)/utils.mk -export PRIVATE_DIR ?= ../../private_tool_scripts --include $(PRIVATE_DIR)/private.mk + @mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR) + ($(OPENROAD_CMD) -no_splash $(if $(filter %.py,$(RUN_SCRIPT)),-pyth diff --git a/flow-Agent/README.md b/flow-Agent/README.md index 4b67310..15edd1a 100644 --- a/flow-Agent/README.md +++ b/flow-Agent/README.md @@ -1,34 +1,77 @@ -# ORFS-Agent: Tool-Using Agents for Chip Design Optimization +# A2-ORFO: Autonomous Agent for Intelligent OpenROAD Flow Optimization ## Overview - -ORFS-Agent is an LLM-based iterative optimization agent for automating parameter tuning in open-source hardware design flows. This implementation integrates with OpenROAD-flow-scripts (ORFS) to optimize chip design parameters using large language models that adaptively explore and refine parameter configurations. - -The agent demonstrates improvements in wirelength and effective clock period by over 13% while using 40% fewer optimization iterations compared to baseline Bayesian optimization approaches. The framework is modular and model-agnostic, working with different LLMs without requiring fine-tuning. - +We expand ([ORFS-Agent](https://github.com/ABKGroup/ORFS-Agent#)) into a complete intelligent agent system, namely A2-ORFO (Autonomous Agent for Intelligent OpenROAD Flow Optimization), so that it can retrieve and invoke the information of the knowledge base in a specific domain to tell us how to fix errors. And combine the global search capability of Large Language Models(LLMs) and the efficient sampling Bayesian Optimization (BO) algorithm to conduct hybrid parameter tuning optimization. Combine LLMs agents with BO and use LLMs agents to replace the three basic capabilities of human engineers, including: The ability to retrieve existing knowledge, analyze and think about planning (debugging and comparing historical data), and the ability to use tools (BO, Genetic Algorithm, MCTS), endowing them with stronger perception ability, transfer memory and interpretability. + +The agent demonstrates improvements in wirelength and effective clock period by over XX% while using XX% fewer optimization iterations compared to baseline Bayesian optimization approaches and over XX% while using XX% fewer optimization iterations compared to ORFS-Agent. The framework is modular and model-agnostic, working with different LLMs without requiring fine-tuning. + +

+ expanding figure +

+ +## Contents +- [Framework of A2-ORFO](#Framework-of-A2-ORFO) +- [Project Structure](#Project-Structure) + - [Core Modules](#Core-Modules) + - [Relevant Execution Scripts](#Relevant-Execution-Scripts) + - [Parameter Constraints Files](#Parameter-Constraints-Files) + - [Helper Utilities](#Helper-Utilities) +- [Key Features](#Key-Features) +- [Environment Setup](#Environment-Setup) + - [Prerequisites](#Prerequisites) + - [Environment Setup](#Environment-Setup) + - [Python Environment Setup](#Python-Environment-Setup) + - [Python Dependencies](#Python-Dependencies) + - [System Environment Setup](#System-Environment-Setup) + - [System Dependencies](#System-Dependencies) +- [Operating Instructions](#Operating-Instructions) + - [Parameter Configuration](#Parameter-Configuration) + - [Design-Specific Configuration](#Design-Specific-Configuration) + - [Resource Planning](#Resource-Planning) + - [API Key Setup](#API-Key-Setup) + - [Running the Optimization](#Running-the-Optimization) + - [Basic Usage](#Basic-Usage) + - [Command Line Options](#Command-Line-Options) + - [Example Runs](#Example-Runs) + - [Output Structure](#Output-Structure) +- [Experimental Results](#Experimental-Results) + +## Framework of A2-ORFO + +The framework of A2-ORFO Agent is shown in the left figure below , and the relevant details are introduced on the right below. + +

+ framework figure +

## Project Structure The ORFS-Agent consists of several key components: -### Core Python Modules +### Core Modules -- **`optimize.py`**: Main optimization script that processes OpenROAD log files and coordinates the optimization workflow +- **`optimize.py`**: Main optimization script using RAG and ReAct techniques to process OpenROAD log files, error messages and optimize the RTL-GDSII flow. Including call the LLM to retrieve existing knowledge to assist optimization and analyze and think about planning to improve the accuracy of the output results under the ReAct framework - **`inspectfuncs.py`**: Data analysis and inspection tools for understanding parameter space and design metrics - **`modelfuncs.py`**: Machine learning utilities including Gaussian Process modeling, kernel selection, and preprocessing - **`agglomfuncs.py`**: Data aggregation and synthesis functions for combining results across multiple runs - **`constraint_optimizer.py`**: Constraint handling and parameter space definition -- **`prompts.py`**: LLM prompt templates and interaction management +- **`AutoTuner-integration`**：The code file integrates the internal Bayesian parameter optimizer Auto-Tuner of ORFS +- **`EDA-Corpus-main/`**：Stores knowledge bases and corpus resources related to design optimization. +- **`rag/`**：Contains the relevant code and configuration files of the RAG framework and is used to implement the +- **`rag_data/`**：Stores retrieval databases, design logs, error samples, and knowledge index files. +- **`models/`**：Stores trained models, vectorized weights, and embedding files to support model inference and knowledge retrieval. +- **`comparison/`**：Contains baseline code to be compared. -### Execution Scripts +### Relevant Execution Scripts - **`maindriver.sh`**: Primary execution script that orchestrates the entire optimization workflow - **`run_sequential.sh`**: Handles sequential optimization phases and parameter generation - **`run_parallel.sh`**: Manages parallel execution of multiple design runs - **`Makefile`**: Modified OpenROAD Makefile supporting parallel runs with INT_PARAM configuration +- **`opt_config.json`**: Parameter constraints, ranges, and optimization settings for different design-PDK combinations +- **`INSTRUCTIONS.md`**: Setup and execution instructions -### Configuration Files - +### Parameter Constraints Files - **`opt_config.json`**: Parameter constraints, ranges, and optimization settings for different design-PDK combinations - **`INSTRUCTIONS.md`**: Setup and execution instructions @@ -40,6 +83,8 @@ The ORFS-Agent consists of several key components: ## Key Features +- **RAG**: Retrieve existing knowledge to assist optimization. +- **ReAct Framework**: Analyze and think about planning to improve the accuracy of the output results with local and global optimization - **Multi-objective Optimization**: Supports optimization of Effective Clock Period (ECP), wirelength (WL), or weighted combinations - **Parallel Execution**: Efficient parallel processing of multiple design configurations - **Adaptive Parameter Exploration**: LLM-guided parameter space exploration with constraint handling @@ -50,54 +95,49 @@ The ORFS-Agent consists of several key components: ### Prerequisites -1. **OpenROAD-flow-scripts**: Install and configure OpenROAD-flow-scripts from the specific commit ([ce8d36a](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/ce8d36a)) referenced in the paper. -2. **Operating System**: Ubuntu/Debian-based system (required) -3. **Hardware Resources**: +1. **OpenROAD-flow-scripts**: Install and configure ORFS-Research. In order to support the parallel execution of multiple tasks, the Makefile of OpenROAD-flow-scripts needs to be adjusted appropriately: the original single configuration file mechanism is changed to the parametric form, that is, from a single config.mk to config_{INT_PARAM}.mk; Add the INT_PARAM variable in the Makefile to distinguish parallel task instances; Use the provided Makefile as a reference for the required changes. +2. **ORFS-Agent**: Install and configure ORFS-Agent from the address ([ORFS-Agent](https://github.com/ABKGroup/ORFS-Agent#)). In order to unify and optimize logic and interfaces, we need to replace the original identical files in the ORFS-Agent library with the files in the current library. Different files in the ORFS-Agent library will be retained. +3. **Operating System**: Ubuntu/Debian-based system +4. **Hardware Resources**: - Minimum 8 vCPUs per parallel run - 8+ GB RAM per parallel run (20-25GB for larger circuits like JPEG) - For default configuration: 110 vCPUs and 220GB RAM total -### Python Environment Setup +### Environment Setup +#### Python Environment Setup ```bash # Create virtual environment python3 -m venv .venv_orfs_agent source .venv_orfs_agent/bin/activate # Install required packages -pip install numpy pandas scikit-learn scipy anthropic python-dotenv scikit-optimize +pip install numpy pandas scikit-learn scipy python-dotenv scikit-optimize openai torch ``` -### Required Dependencies - -The system requires the following Python packages: +#### Python Dependencies - `numpy` - Numerical computing - `pandas` - Data manipulation and analysis - `scikit-learn` - Machine learning utilities - `scipy` - Scientific computing -- `anthropic` - LLM API integration (if using Anthropic models) +- `openai` - LLM API integration (if using openai models) - `python-dotenv` - Environment variable management - `scikit-optimize` - Bayesian optimization +- `torch (pytorch)` - Numerical computing -### Additional System Dependencies - +#### System Environment Setup ```bash # Install required system tools sudo apt-get update sudo apt-get install jq bc timeout ``` +#### System Dependencies +- `jq` - used for parsing and processing JSON data in the command line +- `bc` - Command-line Calculator, used for precise numerical operations +- `timeout` - Used to limit the execution time of a command or script -## Configuration - -### 1. OpenROAD-flow-scripts Setup - -First, modify your OpenROAD Makefile to support parallel runs: - -- Replace single `DESIGN_CONFIG` with multiple parametrized configurations. Instead of a single `config.mk`, the flow uses `config_{INT_PARAM}.mk` to enable parallel runs. -- Add `INT_PARAM` support for parallel execution. -- Use the provided [Makefile](./Makefile) as a reference for required changes. - -### 2. Parameter Configuration +## Operating Instructions +### Parameter Configuration Edit `opt_config.json` to define: @@ -123,7 +163,7 @@ Example configuration structure: } ``` -### 3. Design-Specific Configuration +### Design-Specific Configuration Before running an optimization, you may need to adjust the `config.mk` file for your chosen design, as the default files may not define all tunable parameters. @@ -137,7 +177,7 @@ Before running an optimization, you may need to adjust the `config.mk` file for - **TCL Scripts**: Ensure you are using the provided custom TCL scripts (`fastasap.tcl`, `fastsky.tcl`). You must link these in the `config.mk` file for your design. Refer to the example configuration changes in `exampleaes/configchanges.mk` for guidance. -### 4. Resource Planning +### Resource Planning Configure resource allocation in `maindriver.sh`: @@ -153,18 +193,19 @@ ECP_WEIGHT_SURROGATE=0.5 # Weight for post-CTS ECP in the surrogate model WL_WEIGHT_SURROGATE=0.5 # Weight for post-CTS WL in the surrogate model ``` -### 5. API Key Setup +### API Key Setup The agent requires API keys for LLM providers. You will need to add them directly into the source code: -- **Anthropic API Key**: In `optimize.py`, find the placeholder for the Anthropic API key and insert your key. -- **OpenAI API Key**: In `prompts.py`, find the placeholder for the OpenAI API key and insert your key. This is required for prompt generation functionalities. +- **OpenAI API Key**: In `optimize.py`, find the placeholder for the OpenAI API key and insert your key. This is required for prompt generation functionalities. **Note**: For improved security, consider modifying the scripts to load keys from environment variables using the `python-dotenv` package. -## Running the Optimization +### Running the Optimization -### Basic Usage +Although our internal optimization framework processes are different, the usage is the same as that of ORFS-Agent + +#### Basic Usage ```bash # Make scripts executable @@ -174,7 +215,7 @@ chmod +x maindriver.sh run_parallel.sh run_sequential.sh ./maindriver.sh -p -d [options] ``` -### Command Line Options +#### Command Line Options - **`-p, --platform`**: Target PDK (`asap7` or `sky130hd`) - **`-d, --design`**: Circuit design (`aes`, `ibex`, or `jpeg`) @@ -183,7 +224,7 @@ chmod +x maindriver.sh run_parallel.sh run_sequential.sh - **`-t, --timeout`**: Timeout per run (default: 45m) - **`-o, --objective`**: Optimization goal (`ECP`, `DWL`, or `COMBO`) -### Example Runs +#### Example Runs ```bash # Optimize AES circuit on ASAP7 for ECP @@ -194,9 +235,16 @@ chmod +x maindriver.sh run_parallel.sh run_sequential.sh # Large circuit optimization (JPEG) ./maindriver.sh -p asap7 -d jpeg -o DWL -r 20 -t 90m + +# Directly run 6 examples of DWL optimization in full sequence +chmod +x run_all.sh +./run_all.sh + +# Optimize AES circuit on ASAP7 for ECP with sub-stage and dual supervision framework +./maindriver_stage.sh -p asap7 -d aes -o ECP ``` -## Output Structure +#### Output Structure Each optimization run generates: @@ -209,25 +257,76 @@ Each optimization run generates: - **`logs/`**: Real-time execution logs organized by platform/design - **CSV files**: Parameter configurations and results tracking +Note that the results of the original paper were obtained with Claude-3.5 Sonnet and you *must* ensure that your key for replication and/or running of the tool can support frequent tool calls to the model. -## License - -This project is licensed under the BSD 3-Clause License. See the `LICENSE` file for details. - -## Citation - -This work is based on the research paper: - -**ORFS-agent: Tool-Using Agents for Chip Design Optimization** -*Amur Ghose, Andrew B. Kahng, Sayak Kundu, and Zhiang Wang* -University of California San Diego -arXiv:2506.08332v1 [cs.AI] 12 Jun 2025 | MLCAD 2025 -Available at: https://arxiv.org/pdf/2506.08332 - -## PLEASE READ CAREFULLY FOR REPLICATION, REPRODUCTION AND USAGE ! - -For the purposes of replication or usage, you may be interested in using this as a flow within OR-AutoTuner, OpenROAD's official BO tool. - -Look within the AutoTuner-integration folder for an example of this. Within the ORFS-with-AutoTuner subdirectory, a more streamlined version of ORFS-agent appears in orfs_agent.py, which can be useful if you wish to run your experiments with a restrictive time and/or token budget. +## Experimental Results +Iterate for 20 rounds, parallelize 4 tasks, 12 optimization params, api=deepseek-V3, and only optimize DWL: + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TechCircuitORFS default flow
(no agent)		ORFS-Agent with
deepseek api (baseline)		RAG onlyReAct onlyBoth RAG and ReAct
WLECP*WLECP*WLECP*WLECP*WLECP*
SKY
130HD		JPEG20815298.022793116.9522903307.9023033718.3922290248.63
IBEX108283710.011803768.67112165711.65104441811.4010442879.49
AES8061894.58442904.697744975.568735813.638316084.69
ASAP7IBEX1492531260138616922.43172498891.37140398925.901486241314.52
AES113447400117369389.09101258312.08103820484.8596012465.68
-Note that the results of the original paper were obtained with Claude-3.5 Sonnet and you *must* ensure that your key for replication and/or running of the tool can support frequent tool calls to the model. diff --git a/flow-Agent/comparison/optimize_orfs-agent_claude+llm.py b/flow-Agent/comparison/optimize_orfs-agent_claude+llm.py new file mode 100644 index 0000000..60dcee8 --- /dev/null +++ b/flow-Agent/comparison/optimize_orfs-agent_claude+llm.py @@ -0,0 +1,1273 @@ +#!/usr/bin/env python3 + +import json +import os +import sys +import re +import numpy as np +from typing import Dict, List, Any, Tuple, Optional +import anthropic +import csv +import random + +from inspectfuncs import * +from modelfuncs import * +from agglomfuncs import * + +def process_log_file(log_path: str) -> Dict[str, Any]: + """Process a single log file to extract relevant metrics""" + run_data = { + 'file': os.path.basename(log_path), + 'success': False, + 'metrics': {}, + 'errors': [] + } + + with open(log_path, 'r') as f: + content = f.read() + + # Extract timing information + timing_metrics = extract_timing_metrics(content) + run_data['metrics'].update(timing_metrics) + + # Extract wirelength information + wl_metrics = extract_wirelength_metrics(content) + run_data['metrics'].update(wl_metrics) + + # Extract any errors + errors = extract_errors(content) + run_data['errors'].extend(errors) + + # Determine success based on completion markers and errors + run_data['success'] = is_run_successful(content, errors) + + return run_data + +def extract_timing_metrics(log_content: str) -> Dict[str, float]: + """Extract timing-related metrics from log content""" + metrics = {} + + # Extract worst slack (final) + slack_match = re.search(r'(?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + if slack_match: + metrics['worst_slack'] = float(slack_match.group(1)) + + # Extract CTS worst slack + # cts_slack_match = re.search(r'(?:CTS|Clock Tree) (?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + cts_slack_match = re.search(r'Timing-driven:\s*(?:worst slack|WNS)\s+([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_slack_match: + metrics['cts_ws'] = float(cts_slack_match.group(1)) + + # Extract clock period + # period_match = re.search(r'[Cc]lock period:\s*([\d.]+)', log_content) + period_match = re.search(r'clock period to\s*([\d.]+)', log_content) + if period_match: + metrics['clock_period'] = float(period_match.group(1)) + + # Extract TNS + # tns_match = re.search(r'(?:Total negative slack|TNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + tns_match = re.search(r'"finish__timing__setup__tns"\s*:\s*([-\d.eE]+)', log_content) + if tns_match: + metrics['tns'] = float(tns_match.group(1)) + + return metrics + +def extract_wirelength_metrics(log_content: str) -> Dict[str, float]: + """Extract wirelength-related metrics from log content""" + metrics = {} + + # Extract total wirelength + wl_match = re.search(r'Total wirelength: ([\d.]+)', log_content) + if wl_match: + metrics['total_wirelength'] = float(wl_match.group(1)) + + # Extract estimated wirelength after CTS + # cts_wl_match = re.search(r'Estimated wirelength: ([\d.]+)', log_content) + cts_wl_match = re.search(r'"?cts__route__wirelength__estimated"?\s*[:=]\s*([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_wl_match: + metrics['cts_wirelength'] = float(cts_wl_match.group(1)) + + return metrics +# def extract_timing_metrics(log_content: str) -> Dict[str, float]: +# """Extract timing-related metrics from log content""" +# metrics = {} + +# # Extract worst slack (final) +# slack_match = re.search(r'(?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) +# if slack_match: +# metrics['worst_slack'] = float(slack_match.group(1)) + +# # Extract CTS worst slack +# cts_slack_match = re.search(r'(?:CTS|Clock Tree) (?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) +# if cts_slack_match: +# metrics['cts_ws'] = float(cts_slack_match.group(1)) + +# # Extract clock period +# period_match = re.search(r'[Cc]lock period:\s*([\d.]+)', log_content) +# if period_match: +# metrics['clock_period'] = float(period_match.group(1)) + +# # Extract TNS +# tns_match = re.search(r'(?:Total negative slack|TNS):\s*([-\d.]+)', log_content, re.IGNORECASE) +# if tns_match: +# metrics['tns'] = float(tns_match.group(1)) + +# return metrics + +# def extract_wirelength_metrics(log_content: str) -> Dict[str, float]: +# """Extract wirelength-related metrics from log content""" +# metrics = {} + +# # Extract total wirelength +# wl_match = re.search(r'Total wirelength: ([\d.]+)', log_content) +# if wl_match: +# metrics['total_wirelength'] = float(wl_match.group(1)) + +# # Extract estimated wirelength after CTS +# cts_wl_match = re.search(r'Estimated wirelength: ([\d.]+)', log_content) +# if cts_wl_match: +# metrics['cts_wirelength'] = float(cts_wl_match.group(1)) + +# return metrics + +def extract_errors(log_content: str) -> List[str]: + """Extract error messages from log content""" + errors = [] + + # Look for common error patterns + error_patterns = [ + r'Error: .*', + r'ERROR: .*', + r'FATAL: .*', + r'Failed: .*' + ] + + for pattern in error_patterns: + matches = re.finditer(pattern, log_content, re.MULTILINE) + errors.extend(match.group(0) for match in matches) + + return errors + +def is_run_successful(log_content: str, errors: List[str]) -> bool: + """Determine if a run was successful based on log content and errors""" + if errors: + return False + + # Look for completion markers + completion_markers = [ + 'Flow complete', + 'Finished successfully', + 'Writing out GDS/OAS', + '6_report' + ] + + return any(marker in log_content for marker in completion_markers) + +class OptimizationWorkflow: + def __init__(self, platform: str, design: str, objective: str): + self.platform = platform + self.design = design + self.objective = objective.upper() # Convert to uppercase + + # Load configuration + self.config = self._load_config() + + # Find the design configuration + configurations = self.config.get('configurations', []) + for config in configurations: + if ( + config['platform'].lower() == self.platform.lower() + and config['design'].lower() == self.design.lower() + and config['goal'].upper() == self.objective + ): + self.design_config = config + break + else: + raise ValueError( + f"No configuration found for platform={self.platform}, design={self.design}, objective={self.objective}" + ) + + # Define initial clock periods for each design and platform + initial_clock_periods = { + ('asap7', 'aes'): 400, # in picoseconds + ('asap7', 'ibex'): 1260, # in picoseconds + ('asap7', 'jpeg'): 1100, # in picoseconds + ('sky130hd', 'aes'): 4.5, # in nanoseconds + ('sky130hd', 'ibex'): 10.0,# in nanoseconds + ('sky130hd', 'jpeg'): 8.0, # in nanoseconds + } + + # Get the initial clock period for the current platform and design + key = (self.platform.lower(), self.design.lower()) + if key in initial_clock_periods: + self.initial_clk_period = initial_clock_periods[key] + else: + raise ValueError(f"Initial clock period not defined for platform={self.platform}, design={self.design}") + + # Calculate clock period range + min_clk = self.initial_clk_period * 0.7 + max_clk = self.initial_clk_period * 1.3 + + # Define parameter names in the expected order + self.parameter_names = [ + 'core_util', + 'cell_pad_global', + 'cell_pad_detail', + 'synth_flatten', + 'pin_layer', + 'above_layer', + 'tns', + 'lb_addon', + 'cts_size', + 'cts_diameter', + 'enable_dpo', + 'clk_period' + ] + + # Set all parameter constraints including clock period range + self.param_constraints = { + 'core_util': {'type': 'int', 'range': [20, 99]}, + 'cell_pad_global': {'type': 'int', 'range': [0, 4]}, + 'cell_pad_detail': {'type': 'int', 'range': [0, 4]}, + 'synth_flatten': {'type': 'int', 'range': [0, 1]}, + 'pin_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'above_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'tns': {'type': 'int', 'range': [70, 100]}, + 'lb_addon': {'type': 'float', 'range': [0.00, 0.99]}, + 'cts_size': {'type': 'int', 'range': [10, 40]}, + 'cts_diameter': {'type': 'int', 'range': [80, 120]}, + 'enable_dpo': {'type': 'int', 'range': [0, 1]}, + 'clk_period': {'type': 'float', 'range': [min_clk, max_clk]} + } + + # Load initial parameters and SDC context + self.initial_params = self._load_initial_params() + self.sdc_context = self._load_sdc_context() + + def _load_config(self) -> Dict[str, Any]: + """Load the configuration from 'opt_config.json'.""" + with open('opt_config.json', 'r') as f: + config = json.load(f) + return config + + def _load_initial_params(self) -> Dict[str, Any]: + """Load initial parameters from the design's config.mk file""" + config_path = f"designs/{self.platform}/{self.design}/config.mk" + params = {} + with open(config_path, 'r') as f: + for line in f: + if line.startswith('export'): + parts = line.strip().split('=', 1) + if len(parts) == 2: + key = parts[0].replace('export', '').strip() + value = parts[1].strip() + params[key] = value + return params + + def _load_sdc_context(self) -> Dict[str, Any]: + """Load SDC context including special case for JPEG""" + sdc_context = {} + + # Determine SDC filename based on platform/design + if self.platform.lower() == 'asap7' and self.design.lower() == 'jpeg': + sdc_file = 'jpeg_encoder15_7nm.sdc' + else: + sdc_file = 'constraint.sdc' + + sdc_path = f"designs/{self.platform}/{self.design}/{sdc_file}" + + # Read SDC file + try: + with open(sdc_path, 'r') as f: + sdc_content = f.read() + + # Extract clock period + clock_period_match = re.search(r'set clk_period\s+([\d.]+)', sdc_content) + if clock_period_match: + sdc_context['clock_period'] = float(clock_period_match.group(1)) + + # Store full content for context + sdc_context['content'] = sdc_content + sdc_context['filename'] = sdc_file + + except Exception as e: + print(f"Warning: Could not load SDC file {sdc_path}: {str(e)}") + sdc_context['error'] = str(e) + + return sdc_context + + def _build_error_context(self, data: Dict[str, Any]) -> str: + """Summarize errors across runs so the LLM can diagnose failures""" + log_data = data.get('log_data') or {} + runs = log_data.get('runs') or [] + if not runs: + return "No run history available for diagnostics yet." + + summary = log_data.get('summary') or {} + total_runs = summary.get('total_runs', len(runs)) + failed_runs = summary.get('failed_runs', sum(1 for run in runs if not run.get('success', True))) + successful_runs = summary.get('successful_runs', total_runs - failed_runs) + runs_with_errors = sum(1 for run in runs if run.get('errors')) + + error_buckets: Dict[str, Dict[str, Any]] = {} + failure_examples = [] + + for run in runs: + run_label = run.get('run_id') or run.get('file') or (run.get('files') or ["unknown"])[0] + run_files = [os.path.basename(f) for f in run.get('files', [])] + run_errors = [" ".join(err.split()) for err in run.get('errors', [])] + + if not run.get('success', True) or run_errors: + failure_examples.append({ + 'run': run_label, + 'files': run_files[:2], + 'errors': run_errors[:3], + 'metrics': { + key: run.get('metrics', {}).get(key) + for key in ['worst_slack', 'tns', 'cts_ws', 'total_wirelength'] + if key in run.get('metrics', {}) + } + }) + + for err in run_errors: + bucket = error_buckets.setdefault(err, {'count': 0, 'runs': set(), 'files': set()}) + bucket['count'] += 1 + bucket['runs'].add(run_label) + bucket['files'].update(run_files) + + summary_lines = [ + f"Total runs analyzed: {total_runs}", + f"Successful: {successful_runs}, Failed: {failed_runs}, Runs with explicit errors: {runs_with_errors}" + ] + + if error_buckets: + summary_lines.append("Top recurring error signatures (max 5):") + sorted_errors = sorted(error_buckets.items(), key=lambda kv: kv[1]['count'], reverse=True) + for idx, (msg, info) in enumerate(sorted_errors[:5], start=1): + runs_list = ", ".join(sorted(info['runs'])) or "unknown" + files_list = ", ".join(sorted(info['files'])) or "unknown" + summary_lines.append( + f" {idx}. '{msg}' | count={info['count']} | runs={runs_list} | files={files_list}" + ) + else: + summary_lines.append("No explicit error strings were found in the available logs.") + + if failure_examples: + summary_lines.append("Sample failing runs with metric snapshots:") + for example in failure_examples[:3]: + file_info = ", ".join(example['files']) if example['files'] else "unknown file" + error_info = "; ".join(example['errors']) if example['errors'] else "No explicit errors logged" + metric_info = ", ".join(f"{k}={v}" for k, v in example['metrics'].items()) or "metrics unavailable" + summary_lines.append( + f" - Run {example['run']} ({file_info}): errors={error_info}; metrics={metric_info}" + ) + + return "\n".join(summary_lines) + + def _generate_llm_prompt(self, stage: str, data: Dict[str, Any]) -> str: + """Generate LLM prompt for different stages""" + + # Include parameter constraints in the prompt + constraints_text = "Parameter Constraints:\n" + for param, info in self.param_constraints.items(): + param_type = info['type'] + param_range = info['range'] + constraints_text += f"- {param} ({param_type}, range: {param_range})\n" + + error_context = self._build_error_context(data) + error_prompt_prefix = ( + "Error and failure diagnostics extracted from logs:\n" + f"{error_context}\n\n" + "Use the above diagnostics to reason about likely failure modes, " + "root causes, and mitigation strategies while answering the following tasks.\n\n" + ) + print(f"[DEBUG] error_prompt_prefix:\n{error_prompt_prefix}") + + # Construct the prompt based on the stage + if stage == 'inspect': + prompt = ( + f"**Stage: Inspect**\n" + "In this stage, we analyze the data from previous optimization runs to identify patterns, trends, and insights.\n\n" + f"Data to analyze:\n{json.dumps(data, indent=2, default=str)}\n\n" + f"{error_prompt_prefix}" + "Please analyze the data and provide insights on:\n" + "1. Key patterns in successful vs unsuccessful runs.\n" + "2. Parameter ranges that appear promising.\n" + "3. Any timing or wirelength trends.\n" + "4. Recommendations for subsequent runs.\n" + "5. A prioritized error diagnosis report: group recurring errors, map them to probable flow stages, " + "highlight missing metrics/log anomalies, and propose concrete debugging or mitigation actions.\n" + ) + elif stage == 'model': + prompt = ( + f"**Stage: Model**\n" + "In this stage, we decide how to model the optimization problem based on the data analysis.\n\n" + f"Data for modeling:\n{json.dumps(data, indent=2, default=str)}\n\n" + f"{error_prompt_prefix}" + "Please suggest:\n" + "1. Appropriate modeling techniques.\n" + "2. Key parameters to focus on.\n" + "3. Surrogate model recommendations.\n" + "4. Acquisition function choices.\n" + "5. Ways the model can help detect or avoid the diagnosed failure modes (e.g., additional features, " + "constraints, or uncertainty thresholds that flag risky configurations).\n" + ) + elif stage == 'agglomerate': + prompt = ( + f"**Stage: Agglomerate**\n" + "In this stage, we generate new parameter combinations to explore in the next optimization runs.\n\n" + f"{error_prompt_prefix}" + "Please provide a list of new parameter sets to try, ensuring they respect the domain constraints below.\n\n" + f"{constraints_text}\n" + "Each parameter set should be a dictionary with parameter names and their suggested values.\n" + "**Important:** Make sure all parameter sets satisfy the domain constraints before suggesting them.\n" + "Also explain how each recommended parameter direction mitigates the recurring errors or failures identified above.\n" + ) + else: + prompt = ( + f"**Stage: {stage.capitalize()}**\n" + f"Data:\n{json.dumps(data, indent=2, default=str)}\n\n" + f"{error_prompt_prefix}" + "Please provide guidance based on the above data.\n" + ) + + print(f"[DEBUG] Prompt for stage={stage}:\n{prompt}\n") + return prompt + + def _call_llm(self, stage: str, data: Dict[str, Any]) -> Dict[str, Any]: + """Call Claude to get recommendations for optimization parameters""" + print(f"\n=== Calling LLM for {stage} stage ===") + + # Hardcode API key + # anthropic_api_key=" " + client = anthropic.Anthropic(api_key=os.environ.get("ANTHROPIC_API_KEY")) + + tools = [ + { + "name": "configure_inspection", + "description": "Configure data inspection parameters", + "input_schema": { + "type": "object", + "properties": { + "n_clusters": { + "type": "integer", + "description": "Number of clusters for structure analysis", + "minimum": 2, + "maximum": 10 + }, + "correlation_threshold": { + "type": "number", + "description": "Threshold for considering correlations significant", + "minimum": 0, + "maximum": 1 + } + }, + "required": ["n_clusters", "correlation_threshold"] + } + }, + { + "name": "configure_model", + "description": "Configure modeling approach", + "input_schema": { + "type": "object", + "properties": { + "kernel_type": { + "type": "string", + "enum": ["rbf", "matern", "rational"], + "description": "Type of kernel to use" + }, + "preprocessing": { + "type": "string", + "enum": ["standard", "robust", "none"], + "description": "Type of preprocessing to apply" + }, + "acquisition": { + "type": "string", + "enum": ["ei", "ucb", "pi"], + "description": "Acquisition function to use" + }, + "surrogate_weight": { + "type": "number", + "description": "Weight to give surrogate values", + "minimum": 0, + "maximum": 1 + } + }, + "required": ["kernel_type", "preprocessing", "acquisition", "surrogate_weight"] + } + }, + { + "name": "configure_selection", + "description": "Configure point selection strategy", + "input_schema": { + "type": "object", + "properties": { + "method": { + "type": "string", + "enum": ["entropy", "kmeans", "hybrid", "graph"], + "description": "Selection method to use" + }, + "quality_weight": { + "type": "number", + "description": "Weight between quality and diversity", + "minimum": 0, + "maximum": 1 + }, + "uncertainty_bonus": { + "type": "number", + "description": "Weight for uncertainty in quality scores", + "minimum": 0, + "maximum": 1 + } + }, + "required": ["method", "quality_weight", "uncertainty_bonus"] + } + } + ] + + # Get data summaries + if stage == 'inspect': + print("Generating data distribution and structure summaries...") + # Extract X and Y from successful runs if available + X = [] + Y = [] + if 'log_data' in data and 'runs' in data['log_data']: + for run in data['log_data']['runs']: + if run['success'] and 'metrics' in run: + obj = self._calculate_objective(run) + if obj['value'] is not None or obj['surrogate'] is not None: + # Use parameters as X + params = [] + for param in self.param_constraints.keys(): + params.append(float(run.get('parameters', {}).get(param, 0))) + X.append(params) + # Use objective as Y + Y.append(obj['value'] if obj['value'] is not None else obj['surrogate']) + + if X and Y: + dist_summary = inspect_data_distribution(np.array(X), np.array(Y)) + struct_summary = inspect_data_structure(np.array(X), np.array(Y)) + else: + print("No successful runs found, using empty summaries") + dist_summary = {} + struct_summary = {} + else: + dist_summary = {} + struct_summary = {} + + # Generate context message + context_message = self._generate_llm_prompt(stage, data) + print(f"[DEBUG] Context message for {stage}:\n{context_message}\n") + print(f"Generated prompt with context for {stage}") + + print("Making LLM API call...") + response = client.messages.create( + model="claude-sonnet-4-5", + max_tokens=2048, + tools=tools, + messages=[{ + "role": "user", + "content": context_message + }] + ) + + # Extract configurations + configs = {} + narrative_notes: List[str] = [] + print("\nReceived tool calls from LLM:") + for block in response.content: + if block.type == 'tool_use': + print(f"- {block.name}: {block.input}") + if block.name == 'configure_inspection': + configs['inspection'] = block.input + elif block.name == 'configure_model': + configs['model'] = block.input + elif block.name == 'configure_selection': + configs['selection'] = block.input + elif block.type == 'text': + # Capture any free-form reasoning so users can read root-cause analysis + note = getattr(block, 'text', '') + if note: + narrative_notes.append(note.strip()) + + if narrative_notes: + print("\nLLM diagnostic notes (non-tool response):") + for idx, note in enumerate(narrative_notes, start=1): + print(f"{idx}. {note}") + + # Add default configs if missing + for key, default in [ + ('inspection', {"n_clusters": 5, "correlation_threshold": 0.5}), + ('model', {"kernel_type": "matern", "preprocessing": "robust", + "acquisition": "ei", "surrogate_weight": 0.8}), + ('selection', {"method": "hybrid", "quality_weight": 0.7, + "uncertainty_bonus": 0.2}) + ]: + if key not in configs: + print(f"Warning: No {key} config from LLM, using defaults: {default}") + configs[key] = default + + return configs + + def run_iteration(self, num_runs: int) -> None: + """Run a complete iteration of the optimization workflow""" + print(f"\n=== Starting optimization iteration for {self.platform}/{self.design} ===") + print(f"Objective: {self.objective}") + print(f"Number of runs requested: {num_runs}") + + # Step 1: Inspect logs + print("\nStep 1: Inspecting logs...") + log_data = self.inspect_logs() + print(f"Found {log_data['summary']['total_runs']} total runs, " + f"{log_data['summary']['successful_runs']} successful") + + # Get LLM recommendations for inspection and analysis + print("\nGetting LLM recommendations for inspection...") + inspect_configs = self._call_llm('inspect', { + 'log_data': log_data, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context + }) + print(f"LLM inspection config: {inspect_configs['inspection']}") + + # Step 2: Analyze metrics with LLM config + print("\nStep 2: Analyzing metrics...") + metrics = self.analyze_metrics( + log_data, + n_clusters=inspect_configs['inspection']['n_clusters'], + correlation_threshold=inspect_configs['inspection']['correlation_threshold'] + ) + print(f"Processed metrics for {len(metrics.get('objectives', []))} successful runs") + + # Get LLM recommendations for modeling based on inspection results + print("\nGetting LLM recommendations for modeling...") + model_configs = self._call_llm('model', { + 'log_data': log_data, + 'metrics': metrics, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs + }) + print(f"LLM model config: {model_configs['model']}") + + # Step 3: Evaluate models with LLM config + print("\nStep 3: Evaluating models...") + model_results = self.evaluate_models( + log_data, metrics, + kernel_type=model_configs['model']['kernel_type'], + preprocessing=model_configs['model']['preprocessing'], + acquisition=model_configs['model']['acquisition'], + surrogate_weight=model_configs['model']['surrogate_weight'] + ) + + # Get LLM recommendations for parameter selection based on all previous results + print("\nGetting LLM recommendations for parameter selection...") + selection_configs = self._call_llm('agglomerate', { + 'log_data': log_data, + 'metrics': metrics, + 'model_results': model_results, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs, + 'model_configs': model_configs + }) + print(f"LLM selection config: {selection_configs['selection']}") + + # Step 4: Generate parameters with LLM config + print("\nStep 4: Generating parameters...") + self.generate_parameters( + log_data, metrics, model_results, num_runs, + selection_method=selection_configs['selection']['method'], + quality_weight=selection_configs['selection']['quality_weight'], + uncertainty_bonus=selection_configs['selection']['uncertainty_bonus'] + ) + + def inspect_logs(self) -> Dict[str, Any]: + """Step 1: Inspect all .log and .json logs recursively""" + log_dir = "logs" + pattern = f"{self.platform}_{self.design}_run" + + log_data = { + 'runs': [], + 'summary': { + 'total_runs': 0, + 'successful_runs': 0, + 'failed_runs': 0 + } + } + + if not os.path.exists(log_dir): + return log_data + + run_groups = {} + + for root, _, files in os.walk(log_dir): + for log_file in files: + if log_file.endswith(('.log', '.json')): + log_path = os.path.join(root, log_file) + + if log_file.startswith(pattern) or (self.platform in root and self.design in root): + + run_id = "main" + # case1：eg. logs/asap7_aes_run1.log + m = re.search(r'_run(\d+)\.log$', log_file) + if m: + run_id = f"base_{m.group(1)}" + # case2：path includes base_* + elif 'base_' in root: + run_id = os.path.basename(root) + + run_data = process_log_file(log_path) + + # initialize run + if run_id not in run_groups: + run_groups[run_id] = { + 'run_id': run_id, + 'success': True, + 'metrics': {}, + 'errors': [], + 'files': [] + } + + # clustering + run_groups[run_id]['success'] &= run_data.get('success', True) + run_groups[run_id]['files'].append(log_path) + + if 'metrics' in run_data and run_data['metrics']: + run_groups[run_id]['metrics'].update(run_data['metrics']) + + if 'errors' in run_data and run_data['errors']: + run_groups[run_id]['errors'].extend(run_data['errors']) + + for run_id, run_data in run_groups.items(): + print(f"DEBUG: Run {run_id} success: {run_data['success']}") + print(f"DEBUG: Run {run_id} metrics: {run_data['metrics']}") + print(f"DEBUG: Run {run_id} errors: {run_data['errors']}") + print(f"DEBUG: Run {run_id} files: {run_data['files']}") + + log_data['runs'].append(run_data) + log_data['summary']['total_runs'] += 1 + if run_data['success']: + log_data['summary']['successful_runs'] += 1 + else: + log_data['summary']['failed_runs'] += 1 + + return log_data + + # def inspect_logs(self) -> Dict[str, Any]: + # """Step 1: Inspect all logs so far""" + # log_dir = f"logs/{self.platform}/{self.design}" + # log_data = { + # 'runs': [], + # 'summary': { + # 'total_runs': 0, + # 'successful_runs': 0, + # 'failed_runs': 0 + # } + # } + + # # Ensure log directory exists + # if not os.path.exists(log_dir): + # return log_data + + # # Process each log file + # for log_file in os.listdir(log_dir): + # if log_file.endswith('.log'): + # run_data = process_log_file(os.path.join(log_dir, log_file)) + # log_data['runs'].append(run_data) + + # # Update summary + # log_data['summary']['total_runs'] += 1 + # if run_data['success']: + # log_data['summary']['successful_runs'] += 1 + # else: + # log_data['summary']['failed_runs'] += 1 + + # return log_data + + def analyze_metrics(self, log_data: Dict[str, Any], n_clusters: int, correlation_threshold: float) -> Dict[str, Any]: + """Step 2: Analyze metrics from log data with improved analysis""" + metrics = { + 'objectives': [], + 'surrogates': [], + 'correlations': {}, + 'structure_analysis': {} + } + + # Extract feature vectors and objectives + feature_vectors = [] + objective_values = [] + surrogate_values = [] + + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + run_metrics = run['metrics'] + obj_values = self._calculate_objective(run) + + if obj_values['value'] is not None or obj_values['surrogate'] is not None: + # Extract parameter values as features + params = [] + for param in self.parameter_names: + params.append(float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0)))) + feature_vectors.append(params) + + objective_values.append(obj_values['value'] if obj_values['value'] is not None else np.nan) + surrogate_values.append(obj_values['surrogate'] if obj_values['surrogate'] is not None else np.nan) + + # Track correlations and other metrics + if obj_values['value'] is not None: + metrics['objectives'].append(obj_values['value']) + if obj_values['surrogate'] is not None: + metrics['surrogates'].append(obj_values['surrogate']) + + if obj_values['value'] is not None and obj_values['surrogate'] is not None: + if 'real_vs_surrogate' not in metrics['correlations']: + metrics['correlations']['real_vs_surrogate'] = [] + metrics['correlations']['real_vs_surrogate'].append({ + 'real': obj_values['value'], + 'surrogate': obj_values['surrogate'] + }) + + if feature_vectors: + X = np.array(feature_vectors) + Y = np.array(objective_values) + Y_surrogate = np.array(surrogate_values) + + # Use improved inspection functions + metrics['distribution_analysis'] = inspect_data_distribution(X, Y, Y_surrogate) + metrics['structure_analysis'] = inspect_data_structure(X, Y, { + 'n_clusters': n_clusters, + 'correlation_threshold': correlation_threshold + }) + + # Extract model recommendations if available (from new functions) + if 'model_recommendations' in metrics['structure_analysis']: + metrics['model_recommendations'] = metrics['structure_analysis']['model_recommendations'] + + # Add objective-specific metrics + if self.objective == 'ECP': + metrics['clock_period_impact'] = {} + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + period = float(run['metrics'].get('clock_period', 0)) + if period > 0: + if period not in metrics['clock_period_impact']: + metrics['clock_period_impact'][period] = { + 'final_slack': [], + 'cts_slack': [] + } + if 'worst_slack' in run['metrics']: + metrics['clock_period_impact'][period]['final_slack'].append( + float(run['metrics']['worst_slack'])) + if 'cts_ws' in run['metrics']: + metrics['clock_period_impact'][period]['cts_slack'].append( + float(run['metrics']['cts_ws'])) + + elif self.objective == 'DWL': + metrics['wirelength_progression'] = [] + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + if 'cts_wirelength' in run['metrics'] and 'total_wirelength' in run['metrics']: + metrics['wirelength_progression'].append({ + 'cts': float(run['metrics']['cts_wirelength']), + 'final': float(run['metrics']['total_wirelength']) + }) + + return metrics + + def evaluate_models(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + kernel_type: str, preprocessing: str, acquisition: str, surrogate_weight: float) -> Dict[str, Any]: + """Step 3: Use improved model functions to evaluate parameter quality""" + model_results = {} + + # Build context from log data and metrics + context = { + 'log_data': log_data, + 'metrics': metrics, + 'design_config': self.design_config, + 'initial_params': self.initial_params, + 'model_recommendations': metrics.get('model_recommendations', {}) + } + + # Use model recommendations if available (from new functions) + if 'model_recommendations' in metrics: + kernel_type = metrics['model_recommendations'].get('kernel_type', kernel_type) + preprocessing = 'robust' if metrics['model_recommendations'].get('needs_feature_scaling', True) else 'none' + + # Call appropriate model functions with improved modeling + if self.objective == 'ECP': + model_results = evaluate_timing_model(context) + elif self.objective == 'DWL': + model_results = evaluate_wirelength_model(context) + + # Add model configuration used + model_results['configuration'] = { + 'kernel_type': kernel_type, + 'preprocessing': preprocessing, + 'acquisition': acquisition, + 'surrogate_weight': surrogate_weight + } + + return model_results + + def generate_parameters(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + model_results: Dict[str, Any], num_runs: int, + selection_method: str = 'hybrid', quality_weight: float = 0.7, + uncertainty_bonus: float = 0.2, model_config: Dict[str, Any] = None) -> None: + """Step 4: Generate parameter combinations and write to CSV""" + # Get list of parameters to optimize from constraints + param_names = list(self.param_constraints.keys()) + print(f"\nGenerating parameters for {len(param_names)} variables:") + for name in param_names: + print(f" - {name}: {self.param_constraints[name]}") + + # Extract successful runs for training data + successful_params = [] + successful_objectives = [] + for run in log_data.get('runs', []): + if run.get('success', False) and 'metrics' in run: + params = {} + for param in param_names: + params[param] = float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0))) + successful_params.append(params) + + obj = self._calculate_objective(run) + successful_objectives.append(obj['value'] if obj['value'] is not None else obj['surrogate']) + + print(f"Using {len(successful_params)} successful runs as training data") + + # Convert to numpy arrays + if successful_params: + X = np.array([[params[name] for name in param_names] for params in successful_params]) + y = np.array(successful_objectives) + else: + print("Warning: No successful runs, using initial parameters as base") + X = np.array([[float(self.initial_params.get(name, 0)) for name in param_names]]) + y = np.array([0.0]) + + # Get kernel type from model config + kernel_type = model_config.get('kernel_type', 'matern') if model_config else 'matern' + print(f"\nCreating surrogate model with {kernel_type} kernel") + model = create_model(X, y, kernel_type=kernel_type) + + # Generate candidates + n_candidates = num_runs * 10 + print(f"Generating {n_candidates} candidate points") + candidates = latin_hypercube(n_candidates, len(param_names)) + + # Scale candidates to parameter ranges + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + candidates[:, i] = candidates[:, i] * (max_val - min_val) + min_val + + # Get predictions + predictions, uncertainties = model.predict(candidates, return_std=True) + + # Select points + print(f"\nSelecting points using {selection_method} method") + print(f"Quality weight: {quality_weight}, Uncertainty bonus: {uncertainty_bonus}") + quality_scores = create_quality_scores(candidates, y, predictions, uncertainties) + selected_indices = select_points( + candidates, quality_scores, + method=selection_method, + n_points=num_runs, + config={"quality_weight": quality_weight, + "uncertainty_bonus": uncertainty_bonus} + ) + + selected_params = candidates[selected_indices] + + # Validate domain constraints + print("\nValidating domain constraints...") + valid_params = [] + for params in selected_params: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + else: + print("Warning: Parameter set failed domain constraints") + + print(f"Found {len(valid_params)} valid parameter sets out of {len(selected_params)}") + + # Generate more if needed + while len(valid_params) < num_runs: + needed = num_runs - len(valid_params) + print(f"Generating {needed} additional parameter sets...") + new_candidates = latin_hypercube(needed, len(param_names)) + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + new_candidates[:, i] = new_candidates[:, i] * (max_val - min_val) + min_val + + for params in new_candidates: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + if len(valid_params) >= num_runs: + break + + # Write to CSV + print(f"\nWriting {num_runs} parameter sets to CSV...") + self._write_params_to_csv(valid_params[:num_runs]) + + def _calculate_objective(self, run: Dict[str, Any]) -> Dict[str, float]: + """Calculate objective value and surrogate from run metrics""" + metrics = run.get('metrics', {}) + result = {'value': None, 'surrogate': None} + + if self.objective == 'ECP': + if 'clock_period' in metrics: + period = float(metrics['clock_period']) + # Real ECP from final worst slack + if 'worst_slack' in metrics: + result['value'] = period - float(metrics['worst_slack']) + # Surrogate ECP from CTS worst slack + if 'cts_ws' in metrics: + result['surrogate'] = period - float(metrics['cts_ws']) + + elif self.objective == 'DWL': + # Real wirelength from detailed route + if 'total_wirelength' in metrics: + result['value'] = float(metrics['total_wirelength']) + # Surrogate wirelength from CTS + if 'cts_wirelength' in metrics: + result['surrogate'] = float(metrics['cts_wirelength']) + + elif self.objective == 'COMBO': + # Get weights from environment variables + try: + ecp_weight = float(os.environ.get('ECP_WEIGHT')) + wl_weight = float(os.environ.get('WL_WEIGHT')) + ecp_weight_surrogate = float(os.environ.get('ECP_WEIGHT_SURROGATE')) + wl_weight_surrogate = float(os.environ.get('WL_WEIGHT_SURROGATE')) + except (ValueError, TypeError): + raise ValueError("Weights not properly set in environment variables.") + + # Calculate real ECP and WL values + ecp_value = None + wl_value = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'worst_slack' in metrics: + ecp_value = clock_period - float(metrics['worst_slack']) + if 'total_wirelength' in metrics: + wl_value = float(metrics['total_wirelength']) + + # Calculate surrogate ECP and WL values + ecp_surrogate = None + wl_surrogate = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'cts_ws' in metrics: + ecp_surrogate = clock_period - float(metrics['cts_ws']) + if 'cts_wirelength' in metrics: + wl_surrogate = float(metrics['cts_wirelength']) + + # Calculate weighted objective for real values + if ecp_value is not None and wl_value is not None: + result['value'] = ecp_weight * ecp_value + wl_weight * wl_value + elif ecp_value is not None: + result['value'] = ecp_weight * ecp_value + elif wl_value is not None: + result['value'] = wl_weight * wl_value + + # Calculate weighted surrogate objective + if ecp_surrogate is not None and wl_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + wl_weight_surrogate * wl_surrogate + elif ecp_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + elif wl_surrogate is not None: + result['surrogate'] = wl_weight_surrogate * wl_surrogate + + return result + + def _validate_domain_constraints(self, params: Dict[str, Any]) -> bool: + """Validate parameter combinations against domain constraints""" + # 1. Core utilization vs cell padding + core_util = float(params.get('core_util', 0)) + gp_pad = float(params.get('cell_pad_global', 0)) + dp_pad = float(params.get('cell_pad_detail', 0)) + + if core_util > 80 and (gp_pad > 2 or dp_pad > 2): + print(f"Domain constraint failed: core_util > 80 and gp_pad > 2 or dp_pad > 2") + return False + + # 2. TNS end percent vs place density + tns_end = float(params.get('tns', 0)) + place_density = float(params.get('lb_addon', 0)) + + if tns_end < 70 and place_density > 0.7: + print(f"Domain constraint failed: tns_end < 70 and place_density > 0.7") + return False + + # 3. CTS cluster constraints + cts_size = float(params.get('cts_size', 0)) + cts_diameter = float(params.get('cts_diameter', 0)) + + if cts_size > 30 and cts_diameter < 100: + print(f"Domain constraint failed: cts_size > 30 and cts_diameter < 100") + return False + + return True + + def _write_params_to_csv(self, params_list: List[Dict[str, Any]]) -> None: + """Write the new parameter sets to the expected CSV file for the next iteration""" + csv_file = f"designs/{self.platform}/{self.design}/{self.platform}_{self.design}.csv" + + # Ensure parameters are in correct order and properly typed + with open(csv_file, 'w', newline='\n') as f: # Explicitly use Unix line endings + writer = csv.writer(f) + # Write header in correct order + writer.writerow(self.parameter_names) + + # Write parameter rows + for params in params_list: + row = [] + for param_name in self.parameter_names: + value = params.get(param_name) + if value is None: + print(f"Warning: Missing value for parameter {param_name}") + continue + + # Apply type constraints + constraint = self.param_constraints[param_name] + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param_name} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + + except (ValueError, TypeError) as e: + print(f"Error converting {param_name} value '{value}' to {param_type}: {e}") + continue + + row.append(value) + + if len(row) == len(self.parameter_names): + writer.writerow(row) + else: + print(f"Warning: Skipping incomplete parameter set") + + print(f"New parameter sets written to {csv_file}") + + def _parse_llm_output(self, llm_response: str) -> List[Dict[str, Any]]: + """Parse the LLM's response and enforce parameter constraints""" + try: + param_sets = json.loads(llm_response) + except json.JSONDecodeError as e: + print(f"Error parsing LLM response: {e}") + return [] + + constrained_params = [] + for param_set in param_sets: + ordered_params = {} + valid = True + for param in self.parameter_names: + value = param_set.get(param) + if value is None: + print(f"Parameter '{param}' is missing in the LLM output.") + valid = False + break + + constraint = self.param_constraints.get(param) + if constraint: + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + elif param_type != 'float': + raise ValueError(f"Unsupported parameter type: {param_type}") + + ordered_params[param] = value + except (ValueError, TypeError) as e: + print(f"Parameter '{param}' has invalid value '{value}': {e}") + valid = False + break + else: + print(f"Unknown parameter '{param}' in parameter set.") + valid = False + break + + if valid and self._validate_domain_constraints(ordered_params): + constrained_params.append(ordered_params) + else: + print(f"Parameter set {ordered_params} failed validation and will be discarded.") + + return constrained_params + + def generate_initial_parameters(self, num_runs: int) -> None: + """Generate initial random parameters and write them to CSV using the same method as subsequent iterations""" + params_list = [] + for _ in range(num_runs): + params = {} + for param in self.parameter_names: + info = self.param_constraints[param] + param_type = info['type'] + min_value, max_value = info['range'] + if param_type == 'int': + value = random.randint(int(min_value), int(max_value)) + elif param_type == 'float': + value = random.uniform(min_value, max_value) + else: + continue # Skip unsupported types + params[param] = value + params_list.append(params) + + # Use the same method to write parameters to CSV + self._write_params_to_csv(params_list) + +def main(): + if len(sys.argv) != 5: + print("Usage: optimize.py ") + sys.exit(1) + + platform = sys.argv[1] + design = sys.argv[2] + objective = sys.argv[3] + num_runs = int(sys.argv[4]) + + workflow = OptimizationWorkflow(platform, design, objective) + workflow.run_iteration(num_runs) # Use the run_iteration method instead of individual steps + +if __name__ == "__main__": + main() diff --git a/flow-Agent/comparison/optimize_orfs-agent_claude.py b/flow-Agent/comparison/optimize_orfs-agent_claude.py new file mode 100644 index 0000000..bd03d1d --- /dev/null +++ b/flow-Agent/comparison/optimize_orfs-agent_claude.py @@ -0,0 +1,1177 @@ +#!/usr/bin/env python3 + +import json +import os +import sys +import re +import numpy as np +from typing import Dict, List, Any, Tuple, Optional +import anthropic +import csv +import random + +from inspectfuncs import * +from modelfuncs import * +from agglomfuncs import * + +def process_log_file(log_path: str) -> Dict[str, Any]: + """Process a single log file to extract relevant metrics""" + run_data = { + 'file': os.path.basename(log_path), + 'success': False, + 'metrics': {}, + 'errors': [] + } + + with open(log_path, 'r') as f: + content = f.read() + + # Extract timing information + timing_metrics = extract_timing_metrics(content) + run_data['metrics'].update(timing_metrics) + + # Extract wirelength information + wl_metrics = extract_wirelength_metrics(content) + run_data['metrics'].update(wl_metrics) + + # Extract any errors + errors = extract_errors(content) + run_data['errors'].extend(errors) + + # Determine success based on completion markers and errors + run_data['success'] = is_run_successful(content, errors) + + return run_data + +def extract_timing_metrics(log_content: str) -> Dict[str, float]: + """Extract timing-related metrics from log content""" + metrics = {} + + # Extract worst slack (final) + slack_match = re.search(r'(?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + if slack_match: + metrics['worst_slack'] = float(slack_match.group(1)) + + # Extract CTS worst slack + # cts_slack_match = re.search(r'(?:CTS|Clock Tree) (?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + cts_slack_match = re.search(r'Timing-driven:\s*(?:worst slack|WNS)\s+([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_slack_match: + metrics['cts_ws'] = float(cts_slack_match.group(1)) + + # Extract clock period + # period_match = re.search(r'[Cc]lock period:\s*([\d.]+)', log_content) + period_match = re.search(r'clock period to\s*([\d.]+)', log_content) + if period_match: + metrics['clock_period'] = float(period_match.group(1)) + + # Extract TNS + # tns_match = re.search(r'(?:Total negative slack|TNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + tns_match = re.search(r'"finish__timing__setup__tns"\s*:\s*([-\d.eE]+)', log_content) + if tns_match: + metrics['tns'] = float(tns_match.group(1)) + + return metrics + +def extract_wirelength_metrics(log_content: str) -> Dict[str, float]: + """Extract wirelength-related metrics from log content""" + metrics = {} + + # Extract total wirelength + wl_match = re.search(r'Total wirelength: ([\d.]+)', log_content) + if wl_match: + metrics['total_wirelength'] = float(wl_match.group(1)) + + # Extract estimated wirelength after CTS + # cts_wl_match = re.search(r'Estimated wirelength: ([\d.]+)', log_content) + cts_wl_match = re.search(r'"?cts__route__wirelength__estimated"?\s*[:=]\s*([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_wl_match: + metrics['cts_wirelength'] = float(cts_wl_match.group(1)) + + return metrics +# def extract_timing_metrics(log_content: str) -> Dict[str, float]: +# """Extract timing-related metrics from log content""" +# metrics = {} + +# # Extract worst slack (final) +# slack_match = re.search(r'(?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) +# if slack_match: +# metrics['worst_slack'] = float(slack_match.group(1)) + +# # Extract CTS worst slack +# cts_slack_match = re.search(r'(?:CTS|Clock Tree) (?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) +# if cts_slack_match: +# metrics['cts_ws'] = float(cts_slack_match.group(1)) + +# # Extract clock period +# period_match = re.search(r'[Cc]lock period:\s*([\d.]+)', log_content) +# if period_match: +# metrics['clock_period'] = float(period_match.group(1)) + +# # Extract TNS +# tns_match = re.search(r'(?:Total negative slack|TNS):\s*([-\d.]+)', log_content, re.IGNORECASE) +# if tns_match: +# metrics['tns'] = float(tns_match.group(1)) + +# return metrics + +# def extract_wirelength_metrics(log_content: str) -> Dict[str, float]: +# """Extract wirelength-related metrics from log content""" +# metrics = {} + +# # Extract total wirelength +# wl_match = re.search(r'Total wirelength: ([\d.]+)', log_content) +# if wl_match: +# metrics['total_wirelength'] = float(wl_match.group(1)) + +# # Extract estimated wirelength after CTS +# cts_wl_match = re.search(r'Estimated wirelength: ([\d.]+)', log_content) +# if cts_wl_match: +# metrics['cts_wirelength'] = float(cts_wl_match.group(1)) + +# return metrics + +def extract_errors(log_content: str) -> List[str]: + """Extract error messages from log content""" + errors = [] + + # Look for common error patterns + error_patterns = [ + r'Error: .*', + r'ERROR: .*', + r'FATAL: .*', + r'Failed: .*' + ] + + for pattern in error_patterns: + matches = re.finditer(pattern, log_content, re.MULTILINE) + errors.extend(match.group(0) for match in matches) + + return errors + +def is_run_successful(log_content: str, errors: List[str]) -> bool: + """Determine if a run was successful based on log content and errors""" + if errors: + return False + + # Look for completion markers + completion_markers = [ + 'Flow complete', + 'Finished successfully', + 'Writing out GDS/OAS', + '6_report' + ] + + return any(marker in log_content for marker in completion_markers) + +class OptimizationWorkflow: + def __init__(self, platform: str, design: str, objective: str): + self.platform = platform + self.design = design + self.objective = objective.upper() # Convert to uppercase + + # Load configuration + self.config = self._load_config() + + # Find the design configuration + configurations = self.config.get('configurations', []) + for config in configurations: + if ( + config['platform'].lower() == self.platform.lower() + and config['design'].lower() == self.design.lower() + and config['goal'].upper() == self.objective + ): + self.design_config = config + break + else: + raise ValueError( + f"No configuration found for platform={self.platform}, design={self.design}, objective={self.objective}" + ) + + # Define initial clock periods for each design and platform + initial_clock_periods = { + ('asap7', 'aes'): 400, # in picoseconds + ('asap7', 'ibex'): 1260, # in picoseconds + ('asap7', 'jpeg'): 1100, # in picoseconds + ('sky130hd', 'aes'): 4.5, # in nanoseconds + ('sky130hd', 'ibex'): 10.0,# in nanoseconds + ('sky130hd', 'jpeg'): 8.0, # in nanoseconds + } + + # Get the initial clock period for the current platform and design + key = (self.platform.lower(), self.design.lower()) + if key in initial_clock_periods: + self.initial_clk_period = initial_clock_periods[key] + else: + raise ValueError(f"Initial clock period not defined for platform={self.platform}, design={self.design}") + + # Calculate clock period range + min_clk = self.initial_clk_period * 0.7 + max_clk = self.initial_clk_period * 1.3 + + # Define parameter names in the expected order + self.parameter_names = [ + 'core_util', + 'cell_pad_global', + 'cell_pad_detail', + 'synth_flatten', + 'pin_layer', + 'above_layer', + 'tns', + 'lb_addon', + 'cts_size', + 'cts_diameter', + 'enable_dpo', + 'clk_period' + ] + + # Set all parameter constraints including clock period range + self.param_constraints = { + 'core_util': {'type': 'int', 'range': [20, 99]}, + 'cell_pad_global': {'type': 'int', 'range': [0, 4]}, + 'cell_pad_detail': {'type': 'int', 'range': [0, 4]}, + 'synth_flatten': {'type': 'int', 'range': [0, 1]}, + 'pin_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'above_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'tns': {'type': 'int', 'range': [70, 100]}, + 'lb_addon': {'type': 'float', 'range': [0.00, 0.99]}, + 'cts_size': {'type': 'int', 'range': [10, 40]}, + 'cts_diameter': {'type': 'int', 'range': [80, 120]}, + 'enable_dpo': {'type': 'int', 'range': [0, 1]}, + 'clk_period': {'type': 'float', 'range': [min_clk, max_clk]} + } + + # Load initial parameters and SDC context + self.initial_params = self._load_initial_params() + self.sdc_context = self._load_sdc_context() + + def _load_config(self) -> Dict[str, Any]: + """Load the configuration from 'opt_config.json'.""" + with open('opt_config.json', 'r') as f: + config = json.load(f) + return config + + def _load_initial_params(self) -> Dict[str, Any]: + """Load initial parameters from the design's config.mk file""" + config_path = f"designs/{self.platform}/{self.design}/config.mk" + params = {} + with open(config_path, 'r') as f: + for line in f: + if line.startswith('export'): + parts = line.strip().split('=', 1) + if len(parts) == 2: + key = parts[0].replace('export', '').strip() + value = parts[1].strip() + params[key] = value + return params + + def _load_sdc_context(self) -> Dict[str, Any]: + """Load SDC context including special case for JPEG""" + sdc_context = {} + + # Determine SDC filename based on platform/design + if self.platform.lower() == 'asap7' and self.design.lower() == 'jpeg': + sdc_file = 'jpeg_encoder15_7nm.sdc' + else: + sdc_file = 'constraint.sdc' + + sdc_path = f"designs/{self.platform}/{self.design}/{sdc_file}" + + # Read SDC file + try: + with open(sdc_path, 'r') as f: + sdc_content = f.read() + + # Extract clock period + clock_period_match = re.search(r'set clk_period\s+([\d.]+)', sdc_content) + if clock_period_match: + sdc_context['clock_period'] = float(clock_period_match.group(1)) + + # Store full content for context + sdc_context['content'] = sdc_content + sdc_context['filename'] = sdc_file + + except Exception as e: + print(f"Warning: Could not load SDC file {sdc_path}: {str(e)}") + sdc_context['error'] = str(e) + + return sdc_context + + def _generate_llm_prompt(self, stage: str, data: Dict[str, Any]) -> str: + """Generate LLM prompt for different stages""" + + # Include parameter constraints in the prompt + constraints_text = "Parameter Constraints:\n" + for param, info in self.param_constraints.items(): + param_type = info['type'] + param_range = info['range'] + constraints_text += f"- {param} ({param_type}, range: {param_range})\n" + + # Construct the prompt based on the stage + if stage == 'inspect': + prompt = ( + f"**Stage: Inspect**\n" + "In this stage, we analyze the data from previous optimization runs to identify patterns, trends, and insights.\n\n" + f"Data to analyze:\n{json.dumps(data, indent=2, default=str)}\n\n" + "Please analyze the data and provide insights on:\n" + "1. Key patterns in successful vs unsuccessful runs.\n" + "2. Parameter ranges that appear promising.\n" + "3. Any timing or wirelength trends.\n" + "4. Recommendations for subsequent runs.\n" + ) + elif stage == 'model': + prompt = ( + f"**Stage: Model**\n" + "In this stage, we decide how to model the optimization problem based on the data analysis.\n\n" + f"Data for modeling:\n{json.dumps(data, indent=2, default=str)}\n\n" + "Please suggest:\n" + "1. Appropriate modeling techniques.\n" + "2. Key parameters to focus on.\n" + "3. Surrogate model recommendations.\n" + "4. Acquisition function choices.\n" + ) + elif stage == 'agglomerate': + prompt = ( + f"**Stage: Agglomerate**\n" + "In this stage, we generate new parameter combinations to explore in the next optimization runs.\n\n" + "Please provide a list of new parameter sets to try, ensuring they respect the domain constraints below.\n\n" + f"{constraints_text}\n" + "Each parameter set should be a dictionary with parameter names and their suggested values.\n" + "**Important:** Make sure all parameter sets satisfy the domain constraints before suggesting them.\n" + ) + else: + prompt = ( + f"**Stage: {stage.capitalize()}**\n" + f"Data:\n{json.dumps(data, indent=2, default=str)}\n\n" + "Please provide guidance based on the above data. Please be sure to call the tool to return the structured configuration.\n" + ) + + return prompt + + def _call_llm(self, stage: str, data: Dict[str, Any]) -> Dict[str, Any]: + """Call Claude to get recommendations for optimization parameters""" + print(f"\n=== Calling LLM for {stage} stage ===") + + # Hardcode API key + # anthropic_api_key=" " + client = anthropic.Anthropic(api_key=os.environ.get("ANTHROPIC_API_KEY")) + + tools = [ + { + "name": "configure_inspection", + "description": "Configure data inspection parameters", + "input_schema": { + "type": "object", + "properties": { + "n_clusters": { + "type": "integer", + "description": "Number of clusters for structure analysis", + "minimum": 2, + "maximum": 10 + }, + "correlation_threshold": { + "type": "number", + "description": "Threshold for considering correlations significant", + "minimum": 0, + "maximum": 1 + } + }, + "required": ["n_clusters", "correlation_threshold"] + } + }, + { + "name": "configure_model", + "description": "Configure modeling approach", + "input_schema": { + "type": "object", + "properties": { + "kernel_type": { + "type": "string", + "enum": ["rbf", "matern", "rational"], + "description": "Type of kernel to use" + }, + "preprocessing": { + "type": "string", + "enum": ["standard", "robust", "none"], + "description": "Type of preprocessing to apply" + }, + "acquisition": { + "type": "string", + "enum": ["ei", "ucb", "pi"], + "description": "Acquisition function to use" + }, + "surrogate_weight": { + "type": "number", + "description": "Weight to give surrogate values", + "minimum": 0, + "maximum": 1 + } + }, + "required": ["kernel_type", "preprocessing", "acquisition", "surrogate_weight"] + } + }, + { + "name": "configure_selection", + "description": "Configure point selection strategy", + "input_schema": { + "type": "object", + "properties": { + "method": { + "type": "string", + "enum": ["entropy", "kmeans", "hybrid", "graph"], + "description": "Selection method to use" + }, + "quality_weight": { + "type": "number", + "description": "Weight between quality and diversity", + "minimum": 0, + "maximum": 1 + }, + "uncertainty_bonus": { + "type": "number", + "description": "Weight for uncertainty in quality scores", + "minimum": 0, + "maximum": 1 + } + }, + "required": ["method", "quality_weight", "uncertainty_bonus"] + } + } + ] + + # Get data summaries + if stage == 'inspect': + print("Generating data distribution and structure summaries...") + # Extract X and Y from successful runs if available + X = [] + Y = [] + if 'log_data' in data and 'runs' in data['log_data']: + for run in data['log_data']['runs']: + if run['success'] and 'metrics' in run: + obj = self._calculate_objective(run) + if obj['value'] is not None or obj['surrogate'] is not None: + # Use parameters as X + params = [] + for param in self.param_constraints.keys(): + params.append(float(run.get('parameters', {}).get(param, 0))) + X.append(params) + # Use objective as Y + Y.append(obj['value'] if obj['value'] is not None else obj['surrogate']) + + if X and Y: + dist_summary = inspect_data_distribution(np.array(X), np.array(Y)) + struct_summary = inspect_data_structure(np.array(X), np.array(Y)) + else: + print("No successful runs found, using empty summaries") + dist_summary = {} + struct_summary = {} + else: + dist_summary = {} + struct_summary = {} + + # Generate context message + context_message = self._generate_llm_prompt(stage, data) + print(f"Generated prompt with context for {stage}") + + print("Making LLM API call...") + response = client.messages.create( + model="claude-sonnet-4-5", + # max_tokens=2048, + max_tokens=4096, + tools=tools, + messages=[{ + "role": "user", + "content": context_message + }] + ) + + # Extract configurations + configs = {} + print("\nReceived tool calls from LLM:") + for block in response.content: + if block.type == 'tool_use': + print(f"- {block.name}: {block.input}") + if block.name == 'configure_inspection': + configs['inspection'] = block.input + elif block.name == 'configure_model': + configs['model'] = block.input + elif block.name == 'configure_selection': + configs['selection'] = block.input + elif block.type == 'text': + print(f"LLM text reply: {block.text}") + + # Add default configs if missing + for key, default in [ + ('inspection', {"n_clusters": 5, "correlation_threshold": 0.5}), + ('model', {"kernel_type": "matern", "preprocessing": "robust", + "acquisition": "ei", "surrogate_weight": 0.8}), + ('selection', {"method": "hybrid", "quality_weight": 0.7, + "uncertainty_bonus": 0.2}) + ]: + if key not in configs: + print(f"Warning: No {key} config from LLM, using defaults: {default}") + configs[key] = default + + return configs + + def run_iteration(self, num_runs: int) -> None: + """Run a complete iteration of the optimization workflow""" + print(f"\n=== Starting optimization iteration for {self.platform}/{self.design} ===") + print(f"Objective: {self.objective}") + print(f"Number of runs requested: {num_runs}") + + # Step 1: Inspect logs + print("\nStep 1: Inspecting logs...") + log_data = self.inspect_logs() + print(f"Found {log_data['summary']['total_runs']} total runs, " + f"{log_data['summary']['successful_runs']} successful") + + # Get LLM recommendations for inspection and analysis + print("\nGetting LLM recommendations for inspection...") + inspect_configs = self._call_llm('inspect', { + 'log_data': log_data, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context + }) + print(f"LLM inspection config: {inspect_configs['inspection']}") + + # Step 2: Analyze metrics with LLM config + print("\nStep 2: Analyzing metrics...") + metrics = self.analyze_metrics( + log_data, + n_clusters=inspect_configs['inspection']['n_clusters'], + correlation_threshold=inspect_configs['inspection']['correlation_threshold'] + ) + print(f"Processed metrics for {len(metrics.get('objectives', []))} successful runs") + + # Get LLM recommendations for modeling based on inspection results + print("\nGetting LLM recommendations for modeling...") + model_configs = self._call_llm('model', { + 'log_data': log_data, + 'metrics': metrics, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs + }) + print(f"LLM model config: {model_configs['model']}") + + # Step 3: Evaluate models with LLM config + print("\nStep 3: Evaluating models...") + model_results = self.evaluate_models( + log_data, metrics, + kernel_type=model_configs['model']['kernel_type'], + preprocessing=model_configs['model']['preprocessing'], + acquisition=model_configs['model']['acquisition'], + surrogate_weight=model_configs['model']['surrogate_weight'] + ) + + # Get LLM recommendations for parameter selection based on all previous results + print("\nGetting LLM recommendations for parameter selection...") + selection_configs = self._call_llm('agglomerate', { + 'log_data': log_data, + 'metrics': metrics, + 'model_results': model_results, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs, + 'model_configs': model_configs + }) + print(f"LLM selection config: {selection_configs['selection']}") + + # Step 4: Generate parameters with LLM config + print("\nStep 4: Generating parameters...") + self.generate_parameters( + log_data, metrics, model_results, num_runs, + selection_method=selection_configs['selection']['method'], + quality_weight=selection_configs['selection']['quality_weight'], + uncertainty_bonus=selection_configs['selection']['uncertainty_bonus'] + ) + + def inspect_logs(self) -> Dict[str, Any]: + """Step 1: Inspect all .log and .json logs recursively""" + log_dir = "logs" + pattern = f"{self.platform}_{self.design}_run" + + log_data = { + 'runs': [], + 'summary': { + 'total_runs': 0, + 'successful_runs': 0, + 'failed_runs': 0 + } + } + + if not os.path.exists(log_dir): + return log_data + + run_groups = {} + + for root, _, files in os.walk(log_dir): + for log_file in files: + if log_file.endswith(('.log', '.json')): + log_path = os.path.join(root, log_file) + + if log_file.startswith(pattern) or (self.platform in root and self.design in root): + + run_id = "main" + # case1：eg. logs/asap7_aes_run1.log + m = re.search(r'_run(\d+)\.log$', log_file) + if m: + run_id = f"base_{m.group(1)}" + # case2：path includes base_* + elif 'base_' in root: + run_id = os.path.basename(root) + + run_data = process_log_file(log_path) + + # initialize run + if run_id not in run_groups: + run_groups[run_id] = { + 'run_id': run_id, + 'success': True, + 'metrics': {}, + 'errors': [], + 'files': [] + } + + # clustering + run_groups[run_id]['success'] &= run_data.get('success', True) + run_groups[run_id]['files'].append(log_path) + + if 'metrics' in run_data and run_data['metrics']: + run_groups[run_id]['metrics'].update(run_data['metrics']) + + if 'errors' in run_data and run_data['errors']: + run_groups[run_id]['errors'].extend(run_data['errors']) + + for run_id, run_data in run_groups.items(): + print(f"DEBUG: Run {run_id} success: {run_data['success']}") + print(f"DEBUG: Run {run_id} metrics: {run_data['metrics']}") + print(f"DEBUG: Run {run_id} errors: {run_data['errors']}") + print(f"DEBUG: Run {run_id} files: {run_data['files']}") + + log_data['runs'].append(run_data) + log_data['summary']['total_runs'] += 1 + if run_data['success']: + log_data['summary']['successful_runs'] += 1 + else: + log_data['summary']['failed_runs'] += 1 + + return log_data + + # def inspect_logs(self) -> Dict[str, Any]: + # """Step 1: Inspect all logs so far""" + # log_dir = f"logs/{self.platform}/{self.design}" + # log_data = { + # 'runs': [], + # 'summary': { + # 'total_runs': 0, + # 'successful_runs': 0, + # 'failed_runs': 0 + # } + # } + + # # Ensure log directory exists + # if not os.path.exists(log_dir): + # return log_data + + # # Process each log file + # for log_file in os.listdir(log_dir): + # if log_file.endswith('.log'): + # run_data = process_log_file(os.path.join(log_dir, log_file)) + # log_data['runs'].append(run_data) + + # # Update summary + # log_data['summary']['total_runs'] += 1 + # if run_data['success']: + # log_data['summary']['successful_runs'] += 1 + # else: + # log_data['summary']['failed_runs'] += 1 + + # return log_data + + def analyze_metrics(self, log_data: Dict[str, Any], n_clusters: int, correlation_threshold: float) -> Dict[str, Any]: + """Step 2: Analyze metrics from log data with improved analysis""" + metrics = { + 'objectives': [], + 'surrogates': [], + 'correlations': {}, + 'structure_analysis': {} + } + + # Extract feature vectors and objectives + feature_vectors = [] + objective_values = [] + surrogate_values = [] + + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + run_metrics = run['metrics'] + obj_values = self._calculate_objective(run) + + if obj_values['value'] is not None or obj_values['surrogate'] is not None: + # Extract parameter values as features + params = [] + for param in self.parameter_names: + params.append(float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0)))) + feature_vectors.append(params) + + objective_values.append(obj_values['value'] if obj_values['value'] is not None else np.nan) + surrogate_values.append(obj_values['surrogate'] if obj_values['surrogate'] is not None else np.nan) + + # Track correlations and other metrics + if obj_values['value'] is not None: + metrics['objectives'].append(obj_values['value']) + if obj_values['surrogate'] is not None: + metrics['surrogates'].append(obj_values['surrogate']) + + if obj_values['value'] is not None and obj_values['surrogate'] is not None: + if 'real_vs_surrogate' not in metrics['correlations']: + metrics['correlations']['real_vs_surrogate'] = [] + metrics['correlations']['real_vs_surrogate'].append({ + 'real': obj_values['value'], + 'surrogate': obj_values['surrogate'] + }) + + if feature_vectors: + X = np.array(feature_vectors) + Y = np.array(objective_values) + Y_surrogate = np.array(surrogate_values) + + # Use improved inspection functions + metrics['distribution_analysis'] = inspect_data_distribution(X, Y, Y_surrogate) + metrics['structure_analysis'] = inspect_data_structure(X, Y, { + 'n_clusters': n_clusters, + 'correlation_threshold': correlation_threshold + }) + + # Extract model recommendations if available (from new functions) + if 'model_recommendations' in metrics['structure_analysis']: + metrics['model_recommendations'] = metrics['structure_analysis']['model_recommendations'] + + # Add objective-specific metrics + if self.objective == 'ECP': + metrics['clock_period_impact'] = {} + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + period = float(run['metrics'].get('clock_period', 0)) + if period > 0: + if period not in metrics['clock_period_impact']: + metrics['clock_period_impact'][period] = { + 'final_slack': [], + 'cts_slack': [] + } + if 'worst_slack' in run['metrics']: + metrics['clock_period_impact'][period]['final_slack'].append( + float(run['metrics']['worst_slack'])) + if 'cts_ws' in run['metrics']: + metrics['clock_period_impact'][period]['cts_slack'].append( + float(run['metrics']['cts_ws'])) + + elif self.objective == 'DWL': + metrics['wirelength_progression'] = [] + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + if 'cts_wirelength' in run['metrics'] and 'total_wirelength' in run['metrics']: + metrics['wirelength_progression'].append({ + 'cts': float(run['metrics']['cts_wirelength']), + 'final': float(run['metrics']['total_wirelength']) + }) + + return metrics + + def evaluate_models(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + kernel_type: str, preprocessing: str, acquisition: str, surrogate_weight: float) -> Dict[str, Any]: + """Step 3: Use improved model functions to evaluate parameter quality""" + model_results = {} + + # Build context from log data and metrics + context = { + 'log_data': log_data, + 'metrics': metrics, + 'design_config': self.design_config, + 'initial_params': self.initial_params, + 'model_recommendations': metrics.get('model_recommendations', {}) + } + + # Use model recommendations if available (from new functions) + if 'model_recommendations' in metrics: + kernel_type = metrics['model_recommendations'].get('kernel_type', kernel_type) + preprocessing = 'robust' if metrics['model_recommendations'].get('needs_feature_scaling', True) else 'none' + + # Call appropriate model functions with improved modeling + if self.objective == 'ECP': + model_results = evaluate_timing_model(context) + elif self.objective == 'DWL': + model_results = evaluate_wirelength_model(context) + + # Add model configuration used + model_results['configuration'] = { + 'kernel_type': kernel_type, + 'preprocessing': preprocessing, + 'acquisition': acquisition, + 'surrogate_weight': surrogate_weight + } + + return model_results + + def generate_parameters(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + model_results: Dict[str, Any], num_runs: int, + selection_method: str = 'hybrid', quality_weight: float = 0.7, + uncertainty_bonus: float = 0.2, model_config: Dict[str, Any] = None) -> None: + """Step 4: Generate parameter combinations and write to CSV""" + # Get list of parameters to optimize from constraints + param_names = list(self.param_constraints.keys()) + print(f"\nGenerating parameters for {len(param_names)} variables:") + for name in param_names: + print(f" - {name}: {self.param_constraints[name]}") + + # Extract successful runs for training data + successful_params = [] + successful_objectives = [] + for run in log_data.get('runs', []): + if run.get('success', False) and 'metrics' in run: + params = {} + for param in param_names: + params[param] = float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0))) + successful_params.append(params) + + obj = self._calculate_objective(run) + successful_objectives.append(obj['value'] if obj['value'] is not None else obj['surrogate']) + + print(f"Using {len(successful_params)} successful runs as training data") + + # Convert to numpy arrays + if successful_params: + X = np.array([[params[name] for name in param_names] for params in successful_params]) + y = np.array(successful_objectives) + else: + print("Warning: No successful runs, using initial parameters as base") + X = np.array([[float(self.initial_params.get(name, 0)) for name in param_names]]) + y = np.array([0.0]) + + # Get kernel type from model config + kernel_type = model_config.get('kernel_type', 'matern') if model_config else 'matern' + print(f"\nCreating surrogate model with {kernel_type} kernel") + model = create_model(X, y, kernel_type=kernel_type) + + # Generate candidates + n_candidates = num_runs * 10 + print(f"Generating {n_candidates} candidate points") + candidates = latin_hypercube(n_candidates, len(param_names)) + + # Scale candidates to parameter ranges + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + candidates[:, i] = candidates[:, i] * (max_val - min_val) + min_val + + # Get predictions + predictions, uncertainties = model.predict(candidates, return_std=True) + + # Select points + print(f"\nSelecting points using {selection_method} method") + print(f"Quality weight: {quality_weight}, Uncertainty bonus: {uncertainty_bonus}") + quality_scores = create_quality_scores(candidates, y, predictions, uncertainties) + selected_indices = select_points( + candidates, quality_scores, + method=selection_method, + n_points=num_runs, + config={"quality_weight": quality_weight, + "uncertainty_bonus": uncertainty_bonus} + ) + + selected_params = candidates[selected_indices] + + # Validate domain constraints + print("\nValidating domain constraints...") + valid_params = [] + for params in selected_params: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + else: + print("Warning: Parameter set failed domain constraints") + + print(f"Found {len(valid_params)} valid parameter sets out of {len(selected_params)}") + + # Generate more if needed + while len(valid_params) < num_runs: + needed = num_runs - len(valid_params) + print(f"Generating {needed} additional parameter sets...") + new_candidates = latin_hypercube(needed, len(param_names)) + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + new_candidates[:, i] = new_candidates[:, i] * (max_val - min_val) + min_val + + for params in new_candidates: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + if len(valid_params) >= num_runs: + break + + # Write to CSV + print(f"\nWriting {num_runs} parameter sets to CSV...") + self._write_params_to_csv(valid_params[:num_runs]) + + def _calculate_objective(self, run: Dict[str, Any]) -> Dict[str, float]: + """Calculate objective value and surrogate from run metrics""" + metrics = run.get('metrics', {}) + result = {'value': None, 'surrogate': None} + + if self.objective == 'ECP': + if 'clock_period' in metrics: + period = float(metrics['clock_period']) + # Real ECP from final worst slack + if 'worst_slack' in metrics: + result['value'] = period - float(metrics['worst_slack']) + # Surrogate ECP from CTS worst slack + if 'cts_ws' in metrics: + result['surrogate'] = period - float(metrics['cts_ws']) + + elif self.objective == 'DWL': + # Real wirelength from detailed route + if 'total_wirelength' in metrics: + result['value'] = float(metrics['total_wirelength']) + # Surrogate wirelength from CTS + if 'cts_wirelength' in metrics: + result['surrogate'] = float(metrics['cts_wirelength']) + + elif self.objective == 'COMBO': + # Get weights from environment variables + try: + ecp_weight = float(os.environ.get('ECP_WEIGHT')) + wl_weight = float(os.environ.get('WL_WEIGHT')) + ecp_weight_surrogate = float(os.environ.get('ECP_WEIGHT_SURROGATE')) + wl_weight_surrogate = float(os.environ.get('WL_WEIGHT_SURROGATE')) + except (ValueError, TypeError): + raise ValueError("Weights not properly set in environment variables.") + + # Calculate real ECP and WL values + ecp_value = None + wl_value = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'worst_slack' in metrics: + ecp_value = clock_period - float(metrics['worst_slack']) + if 'total_wirelength' in metrics: + wl_value = float(metrics['total_wirelength']) + + # Calculate surrogate ECP and WL values + ecp_surrogate = None + wl_surrogate = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'cts_ws' in metrics: + ecp_surrogate = clock_period - float(metrics['cts_ws']) + if 'cts_wirelength' in metrics: + wl_surrogate = float(metrics['cts_wirelength']) + + # Calculate weighted objective for real values + if ecp_value is not None and wl_value is not None: + result['value'] = ecp_weight * ecp_value + wl_weight * wl_value + elif ecp_value is not None: + result['value'] = ecp_weight * ecp_value + elif wl_value is not None: + result['value'] = wl_weight * wl_value + + # Calculate weighted surrogate objective + if ecp_surrogate is not None and wl_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + wl_weight_surrogate * wl_surrogate + elif ecp_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + elif wl_surrogate is not None: + result['surrogate'] = wl_weight_surrogate * wl_surrogate + + return result + + def _validate_domain_constraints(self, params: Dict[str, Any]) -> bool: + """Validate parameter combinations against domain constraints""" + # 1. Core utilization vs cell padding + core_util = float(params.get('core_util', 0)) + gp_pad = float(params.get('cell_pad_global', 0)) + dp_pad = float(params.get('cell_pad_detail', 0)) + + if core_util > 80 and (gp_pad > 2 or dp_pad > 2): + print(f"Domain constraint failed: core_util > 80 and gp_pad > 2 or dp_pad > 2") + return False + + # 2. TNS end percent vs place density + tns_end = float(params.get('tns', 0)) + place_density = float(params.get('lb_addon', 0)) + + if tns_end < 70 and place_density > 0.7: + print(f"Domain constraint failed: tns_end < 70 and place_density > 0.7") + return False + + # 3. CTS cluster constraints + cts_size = float(params.get('cts_size', 0)) + cts_diameter = float(params.get('cts_diameter', 0)) + + if cts_size > 30 and cts_diameter < 100: + print(f"Domain constraint failed: cts_size > 30 and cts_diameter < 100") + return False + + return True + + def _write_params_to_csv(self, params_list: List[Dict[str, Any]]) -> None: + """Write the new parameter sets to the expected CSV file for the next iteration""" + csv_file = f"designs/{self.platform}/{self.design}/{self.platform}_{self.design}.csv" + + # Ensure parameters are in correct order and properly typed + with open(csv_file, 'w', newline='\n') as f: # Explicitly use Unix line endings + writer = csv.writer(f) + # Write header in correct order + writer.writerow(self.parameter_names) + + # Write parameter rows + for params in params_list: + row = [] + for param_name in self.parameter_names: + value = params.get(param_name) + if value is None: + print(f"Warning: Missing value for parameter {param_name}") + continue + + # Apply type constraints + constraint = self.param_constraints[param_name] + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param_name} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + + except (ValueError, TypeError) as e: + print(f"Error converting {param_name} value '{value}' to {param_type}: {e}") + continue + + row.append(value) + + if len(row) == len(self.parameter_names): + writer.writerow(row) + else: + print(f"Warning: Skipping incomplete parameter set") + + print(f"New parameter sets written to {csv_file}") + + def _parse_llm_output(self, llm_response: str) -> List[Dict[str, Any]]: + """Parse the LLM's response and enforce parameter constraints""" + try: + param_sets = json.loads(llm_response) + except json.JSONDecodeError as e: + print(f"Error parsing LLM response: {e}") + return [] + + constrained_params = [] + for param_set in param_sets: + ordered_params = {} + valid = True + for param in self.parameter_names: + value = param_set.get(param) + if value is None: + print(f"Parameter '{param}' is missing in the LLM output.") + valid = False + break + + constraint = self.param_constraints.get(param) + if constraint: + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + elif param_type != 'float': + raise ValueError(f"Unsupported parameter type: {param_type}") + + ordered_params[param] = value + except (ValueError, TypeError) as e: + print(f"Parameter '{param}' has invalid value '{value}': {e}") + valid = False + break + else: + print(f"Unknown parameter '{param}' in parameter set.") + valid = False + break + + if valid and self._validate_domain_constraints(ordered_params): + constrained_params.append(ordered_params) + else: + print(f"Parameter set {ordered_params} failed validation and will be discarded.") + + return constrained_params + + def generate_initial_parameters(self, num_runs: int) -> None: + """Generate initial random parameters and write them to CSV using the same method as subsequent iterations""" + params_list = [] + for _ in range(num_runs): + params = {} + for param in self.parameter_names: + info = self.param_constraints[param] + param_type = info['type'] + min_value, max_value = info['range'] + if param_type == 'int': + value = random.randint(int(min_value), int(max_value)) + elif param_type == 'float': + value = random.uniform(min_value, max_value) + else: + continue # Skip unsupported types + params[param] = value + params_list.append(params) + + # Use the same method to write parameters to CSV + self._write_params_to_csv(params_list) + +def main(): + if len(sys.argv) != 5: + print("Usage: optimize.py ") + sys.exit(1) + + platform = sys.argv[1] + design = sys.argv[2] + objective = sys.argv[3] + num_runs = int(sys.argv[4]) + + workflow = OptimizationWorkflow(platform, design, objective) + workflow.run_iteration(num_runs) # Use the run_iteration method instead of individual steps + +if __name__ == "__main__": + main() diff --git a/flow-Agent/comparison/optimize_orfs-agent_deepseek.py b/flow-Agent/comparison/optimize_orfs-agent_deepseek.py new file mode 100644 index 0000000..b387eda --- /dev/null +++ b/flow-Agent/comparison/optimize_orfs-agent_deepseek.py @@ -0,0 +1,1205 @@ +#!/usr/bin/env python3 + +import json +import os +import sys +import re +import numpy as np +from typing import Dict, List, Any, Tuple, Optional +# import anthropic +import csv +import random +# from rag.util import answerWithRAG +# from rag.index import load_embeddings_and_docs, build_and_save_embeddings +import torch +from sentence_transformers import SentenceTransformer +from pathlib import Path + +from openai import OpenAI +from inspectfuncs import * +from modelfuncs import * +from agglomfuncs import * + +def process_log_file(log_path: str) -> Dict[str, Any]: + """Process a single log file to extract relevant metrics""" + run_data = { + 'file': os.path.basename(log_path), + 'success': False, + 'metrics': {}, + 'errors': [] + } + + with open(log_path, 'r') as f: + content = f.read() + print(f"File size: {len(content)} characters") + + # Extract timing information + timing_metrics = extract_timing_metrics(content) + run_data['metrics'].update(timing_metrics) + + # Extract wirelength information + wl_metrics = extract_wirelength_metrics(content) + run_data['metrics'].update(wl_metrics) + + # Extract any errors + errors = extract_errors(content) + run_data['errors'].extend(errors) + + # Determine success based on completion markers and errors + run_data['success'] = is_run_successful(content, errors) + + return run_data + +def extract_timing_metrics(log_content: str) -> Dict[str, float]: + """Extract timing-related metrics from log content""" + metrics = {} + + # Extract worst slack (final) + slack_match = re.search(r'(?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + if slack_match: + metrics['worst_slack'] = float(slack_match.group(1)) + + # Extract CTS worst slack + # cts_slack_match = re.search(r'(?:CTS|Clock Tree) (?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + cts_slack_match = re.search(r'Timing-driven:\s*(?:worst slack|WNS)\s+([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_slack_match: + metrics['cts_ws'] = float(cts_slack_match.group(1)) + + # Extract clock period + # period_match = re.search(r'[Cc]lock period:\s*([\d.]+)', log_content) + period_match = re.search(r'clock period to\s*([\d.]+)', log_content) + if period_match: + metrics['clock_period'] = float(period_match.group(1)) + + # Extract TNS + # tns_match = re.search(r'(?:Total negative slack|TNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + tns_match = re.search(r'"finish__timing__setup__tns"\s*:\s*([-\d.eE]+)', log_content) + if tns_match: + metrics['tns'] = float(tns_match.group(1)) + + return metrics + +def extract_wirelength_metrics(log_content: str) -> Dict[str, float]: + """Extract wirelength-related metrics from log content""" + metrics = {} + + # Extract total wirelength + wl_match = re.search(r'Total wirelength: ([\d.]+)', log_content) + if wl_match: + metrics['total_wirelength'] = float(wl_match.group(1)) + + # Extract estimated wirelength after CTS + # cts_wl_match = re.search(r'Estimated wirelength: ([\d.]+)', log_content) + cts_wl_match = re.search(r'"?cts__route__wirelength__estimated"?\s*[:=]\s*([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_wl_match: + metrics['cts_wirelength'] = float(cts_wl_match.group(1)) + + return metrics + +def extract_errors(log_content: str) -> List[str]: + """Extract error messages from log content""" + errors = [] + + # Look for common error patterns + error_patterns = [ + r'Error: .*', + r'ERROR: .*', + r'FATAL: .*', + r'Failed: .*' + ] + + for pattern in error_patterns: + matches = re.finditer(pattern, log_content, re.MULTILINE) + errors.extend(match.group(0) for match in matches) + + return errors + +def is_run_successful(log_content: str, errors: List[str]) -> bool: + """Determine if a run was successful based on log content and errors""" + if errors: + return False + + # Look for completion markers + completion_markers = [ + 'Flow complete', + 'Finished successfully' + 'Writing out GDS/OAS', + '6_report' + ] + + return any(marker in log_content for marker in completion_markers) + +class OptimizationWorkflow: + def __init__(self, platform: str, design: str, objective: str): + self.platform = platform + self.design = design + self.objective = objective.upper() # Convert to uppercase + + # Load configuration + self.config = self._load_config() + + # Find the design configuration + configurations = self.config.get('configurations', []) + for config in configurations: + if ( + config['platform'].lower() == self.platform.lower() + and config['design'].lower() == self.design.lower() + and config['goal'].upper() == self.objective + ): + self.design_config = config + break + else: + raise ValueError( + f"No configuration found for platform={self.platform}, design={self.design}, objective={self.objective}" + ) + + # Define initial clock periods for each design and platform + initial_clock_periods = { + ('asap7', 'aes'): 400, # in picoseconds + ('asap7', 'ibex'): 1260, # in picoseconds + ('asap7', 'jpeg'): 1100, # in picoseconds + ('sky130hd', 'aes'): 4.5, # in nanoseconds + ('sky130hd', 'ibex'): 10.0,# in nanoseconds + ('sky130hd', 'jpeg'): 8.0, # in nanoseconds + } + + # Get the initial clock period for the current platform and design + key = (self.platform.lower(), self.design.lower()) + if key in initial_clock_periods: + self.initial_clk_period = initial_clock_periods[key] + else: + raise ValueError(f"Initial clock period not defined for platform={self.platform}, design={self.design}") + + # Calculate clock period range + min_clk = self.initial_clk_period * 0.7 + max_clk = self.initial_clk_period * 1.3 + + # Define parameter names in the expected order + self.parameter_names = [ + 'core_util', + 'cell_pad_global', + 'cell_pad_detail', + 'synth_flatten', + 'pin_layer', + 'above_layer', + 'tns', + 'lb_addon', + 'cts_size', + 'cts_diameter', + 'enable_dpo', + 'clk_period' + ] + + # Set all parameter constraints including clock period range + self.param_constraints = { + 'core_util': {'type': 'int', 'range': [20, 99]}, + 'cell_pad_global': {'type': 'int', 'range': [0, 4]}, + 'cell_pad_detail': {'type': 'int', 'range': [0, 4]}, + 'synth_flatten': {'type': 'int', 'range': [0, 1]}, + 'pin_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'above_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'tns': {'type': 'int', 'range': [70, 100]}, + 'lb_addon': {'type': 'float', 'range': [0.00, 0.99]}, + 'cts_size': {'type': 'int', 'range': [10, 40]}, + 'cts_diameter': {'type': 'int', 'range': [80, 120]}, + 'enable_dpo': {'type': 'int', 'range': [0, 1]}, + 'clk_period': {'type': 'float', 'range': [min_clk, max_clk]} + } + + # Load initial parameters and SDC context + self.initial_params = self._load_initial_params() + self.sdc_context = self._load_sdc_context() + + # emb_np, docs, docsDict = load_embeddings_and_docs() + # self.rag_embeddings = torch.tensor(emb_np).cpu() + # self.rag_docs = docs + # self.rag_docsDict = docsDict + # print("[INFO] Loading embedding model...") + # model_path = Path(__file__).parent / "models" / "mxbai-embed-large-v1" + # model_path = model_path.resolve() + # self.rag_model = SentenceTransformer(str(model_path)) + + + def _load_config(self) -> Dict[str, Any]: + """Load the configuration from 'opt_config.json'.""" + with open('opt_config.json', 'r') as f: + config = json.load(f) + return config + + def _load_initial_params(self) -> Dict[str, Any]: + """Load initial parameters from the design's config.mk file""" + config_path = f"designs/{self.platform}/{self.design}/config.mk" + params = {} + with open(config_path, 'r') as f: + for line in f: + if line.startswith('export'): + parts = line.strip().split('=', 1) + if len(parts) == 2: + key = parts[0].replace('export', '').strip() + value = parts[1].strip() + params[key] = value + return params + + def _load_sdc_context(self) -> Dict[str, Any]: + """Load SDC context including special case for JPEG""" + sdc_context = {} + + # Determine SDC filename based on platform/design + if self.platform.lower() == 'asap7' and self.design.lower() == 'jpeg': + sdc_file = 'jpeg_encoder15_7nm.sdc' + else: + sdc_file = 'constraint.sdc' + + sdc_path = f"designs/{self.platform}/{self.design}/{sdc_file}" + + # Read SDC file + try: + with open(sdc_path, 'r') as f: + sdc_content = f.read() + + # Extract clock period + clock_period_match = re.search(r'set clk_period\s+([\d.]+)', sdc_content) + if clock_period_match: + sdc_context['clock_period'] = float(clock_period_match.group(1)) + + # Store full content for context + sdc_context['content'] = sdc_content + sdc_context['filename'] = sdc_file + + except Exception as e: + print(f"Warning: Could not load SDC file {sdc_path}: {str(e)}") + sdc_context['error'] = str(e) + + return sdc_context + + def _generate_llm_prompt(self, stage: str, data: Dict[str, Any]) -> str: + + constraints_text = "Parameter Constraints:\n" + for param, info in self.param_constraints.items(): + param_type = info['type'] + param_range = info['range'] + constraints_text += f"- {param} ({param_type}, range: {param_range})\n" + + tool_instructions = { + 'inspect': ( + f"**Stage: Inspect**\n" + "In this stage, we analyze the data from previous optimization runs to identify patterns, trends, and insights.\n\n" + f"Data to analyze:\n{json.dumps(data, indent=2, default=str)}\n\n" + "Please analyze the data and provide insights on:\n" + "1. Key patterns in successful vs unsuccessful runs.\n" + "2. Parameter ranges that appear promising.\n" + "3. Any timing or wirelength trends.\n" + "4. Recommendations for subsequent runs.\n" + "5. We hope to further reduce the total wirelength.\n" + ), + + 'model': ( + f"**Stage: Model**\n" + "In this stage, we decide how to model the optimization problem based on the data analysis.\n\n" + f"Data for modeling:\n{json.dumps(data, indent=2, default=str)}\n\n" + "Please suggest:\n" + "1. Appropriate modeling techniques.\n" + "2. Key parameters to focus on.\n" + "3. Surrogate model recommendations.\n" + "4. Acquisition function choices.\n" + ), + + 'agglomerate': ( + f"**Stage: Agglomerate**\n" + "In this stage, we generate new parameter combinations to explore in the next optimization runs.\n\n" + "Please provide a list of new parameter sets to try, ensuring they respect the domain constraints below.\n\n" + f"{constraints_text}\n" + "Each parameter set should be a dictionary with parameter names and their suggested values.\n" + "**Important:** Make sure all parameter sets satisfy the domain constraints before suggesting them.\n" + ) + } + + stage_contexts = { + 'inspect': ( + f"metrics analyze: Total runs={data.get('log_data', {}).get('summary', {}).get('total_runs', 0)}, " + f"successful runs ={data.get('log_data', {}).get('summary', {}).get('successful_runs', 0)}" + ), + 'model': "Configure modeling methods based on inspection results", + 'agglomerate': "Configure parameter selection strategy based on modeling results" + } + + prompt = f"""**stages:{stage.upper()}** + + {stage_contexts.get(stage, '')} + + {tool_instructions.get(stage, '')} + + **Important: Use **tool calls only**, and generate text responses!** + """ + # ========= 拼接 RAG ========= + # rag_context = "" + # if self.rag_model is not None and self.rag_embeddings is not None: + # try: + # print("[DEBUG] RAG: Starting retrieval...") + # query = ( + # f"Stage: {stage}. Objective: {self.objective}. " + # f"Focus on analyzing {stage}-related optimization results. " + # f"Important metrics include wirelength, timing, area, and success rate. " + # f"Find relevant OpenROAD documentation, parameter tuning guides, and failure pattern examples." + # ) + # rag_context = answerWithRAG( + # query, + # self.rag_embeddings, + # self.rag_model, + # self.rag_docs, + # self.rag_docsDict + # ) + # print(f"[DEBUG] RAG: Retrieved context length = {len(rag_context)}") + # if rag_context.strip(): + # prompt += ( + # "\n\n=== Retrieved OpenROAD Documentation (via RAG) ===\n" + # f"{rag_context}\n" + # "==============================================" + # ) + # print("[DEBUG] RAG: Context successfully added to prompt.") + # else: + # print("[DEBUG] RAG: Empty context retrieved.") + # except Exception as e: + # prompt += f"\n\n[WARN] RAG retrieval failed: {e}" + + return prompt + + def _call_llm(self, stage: str, data: Dict[str, Any]) -> Dict[str, Any]: + """Call Claude to get recommendations for optimization parameters""" + print(f"\n=== Calling LLM for {stage} stage ===") + + # Hardcode API key + # api_key = ""#PUT YOUR KEY HERE + + # client = anthropic.Anthropic(api_key=api_key) + client = OpenAI( + base_url="https://ai.gitee.com/v1", + api_key=" ", + ) + + tools = [ + { + "type": "function", + "function": { + "name": "configure_inspection", + "description": "Configure data inspection parameters", + "parameters": { + "type": "object", + "properties": { + "n_clusters": { + "type": "integer", + "description": "Number of clusters for structure analysis", + "minimum": 2, + "maximum": 10 + }, + "correlation_threshold": { + "type": "number", + "description": "Threshold for considering correlations significant", + "minimum": 0, + "maximum": 1 + } + }, + "required": ["n_clusters", "correlation_threshold"] + } + } + }, + { + "type": "function", + "function": { + "name": "configure_model", + "description": "Configure modeling approach", + "parameters": { + "type": "object", + "properties": { + "kernel_type": { + "type": "string", + "enum": ["rbf", "matern", "rational"], + "description": "Type of kernel to use" + }, + "preprocessing": { + "type": "string", + "enum": ["standard", "robust", "none"], + "description": "Type of preprocessing to apply" + }, + "acquisition": { + "type": "string", + "enum": ["ei", "ucb", "pi"], + "description": "Acquisition function to use" + }, + "surrogate_weight": { + "type": "number", + "description": "Weight to give surrogate values", + "minimum": 0, + "maximum": 1 + } + }, + "required": ["kernel_type", "preprocessing", "acquisition", "surrogate_weight"] + } + } + }, + { + "type": "function", + "function": { + "name": "configure_selection", + "description": "Configure point selection strategy", + "parameters": { + "type": "object", + "properties": { + "method": { + "type": "string", + "enum": ["entropy", "kmeans", "hybrid", "graph"], + "description": "Selection method to use" + }, + "quality_weight": { + "type": "number", + "description": "Weight between quality and diversity", + "minimum": 0, + "maximum": 1 + }, + "uncertainty_bonus": { + "type": "number", + "description": "Weight for uncertainty in quality scores", + "minimum": 0, + "maximum": 1 + } + }, + "required": ["method", "quality_weight", "uncertainty_bonus"] + } + } + } + ] + + # Get data summaries + if stage == 'inspect': + print("Generating data distribution and structure summaries...") + # Extract X and Y from successful runs if available + print("=== DEBUG: Checking data structure ===") + print(f"data keys: {list(data.keys()) if data else 'Empty data'}") + X = [] + Y = [] + if 'log_data' in data and 'runs' in data['log_data']: + print("✓ 'log_data' and 'runs' found in data") + print(f"Number of runs: {len(data['log_data']['runs'])}") + for run in data['log_data']['runs']: + if run['success'] and 'metrics' in run: + obj = self._calculate_objective(run) + if obj['value'] is not None or obj['surrogate'] is not None: + # Use parameters as X + params = [] + for param in self.param_constraints.keys(): + params.append(float(run.get('parameters', {}).get(param, 0))) + X.append(params) + # Use objective as Y + Y.append(obj['value'] if obj['value'] is not None else obj['surrogate']) + print(f" ✓ Added to X and Y: X={params}, Y={obj['value'] if obj['value'] is not None else obj['surrogate']}") + + if X and Y: + dist_summary = inspect_data_distribution(np.array(X), np.array(Y)) + # struct_summary = inspect_data_structure(np.array(X)) + struct_summary = inspect_data_structure(np.array(X), np.array(Y)) + print("dist_summary =", dist_summary) + print("struct_summary =", struct_summary) + print("DEBUG: len(X)=", len(X), " len(Y)=", len(Y)) + else: + print("No successful runs found, using empty summaries") + dist_summary = {} + struct_summary = {} + else: + dist_summary = {} + struct_summary = {} + + # Generate context message + context_message = self._generate_llm_prompt(stage, data) + print(f"Generated prompt with context for {stage}") + print("=== Context Message ===") + print(context_message) + print("========================") + + print("Making LLM API call...") + # response = client.messages.create( + response = client.chat.completions.create( + # model="claude-3-sonnet-20240229", + model="DeepSeek-V3", + messages=[{ + "role": "user", + "content": context_message + }], + # max_tokens=2048, + tools=tools, + tool_choice="auto", + # stream=True, + max_tokens=1024, + temperature=0.1, + timeout=300.0, + ) + + # Extract configurations + configs = {} + print("=== Complete API response ===") + print(f"Response type: {type(response)}") + print(f"Choices count: {len(response.choices)}") + print("\nReceived tool calls from LLM:") + message = response.choices[0].message + print(f"Message content: {getattr(message, 'content', 'No content')}") + print(f"Tool calls: {getattr(message, 'tool_calls', 'No tool calls')}") + + # Check if any tools are being called + if hasattr(message, 'tool_calls') and message.tool_calls: + for tool_call in message.tool_calls: + function_name = tool_call.function.name + function_args = json.loads(tool_call.function.arguments) + + print(f"- {function_name}: {function_args}") + + if function_name == 'configure_inspection': + configs['inspection'] = function_args + elif function_name == 'configure_model': + configs['model'] = function_args + elif function_name == 'configure_selection': + configs['selection'] = function_args + + # Add default configs if missing + for key, default in [ + ('inspection', {"n_clusters": 5, "correlation_threshold": 0.5}), + ('model', {"kernel_type": "matern", "preprocessing": "robust", + "acquisition": "ei", "surrogate_weight": 0.8}), + ('selection', {"method": "hybrid", "quality_weight": 0.7, + "uncertainty_bonus": 0.2}) + ]: + if key not in configs: + print(f"Warning: No {key} config from LLM, using defaults: {default}") + configs[key] = default + + return configs + + def run_iteration(self, num_runs: int) -> None: + """Run a complete iteration of the optimization workflow""" + print(f"\n=== Starting optimization iteration for {self.platform}/{self.design} ===") + print(f"Objective: {self.objective}") + print(f"Number of runs requested: {num_runs}") + + # Step 1: Inspect logs + print("\nStep 1: Inspecting logs...") + log_data = self.inspect_logs() + print(f"Found {log_data['summary']['total_runs']} total runs, " + f"{log_data['summary']['successful_runs']} successful") + + # Get LLM recommendations for inspection and analysis + print("\nGetting LLM recommendations for inspection...") + inspect_configs = self._call_llm('inspect', { + 'log_data': log_data, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context + }) + print(f"LLM inspection config: {inspect_configs['inspection']}") + + # Step 2: Analyze metrics with LLM config + print("\nStep 2: Analyzing metrics...") + metrics = self.analyze_metrics( + log_data, + n_clusters=inspect_configs['inspection']['n_clusters'], + correlation_threshold=inspect_configs['inspection']['correlation_threshold'] + ) + print(f"Processed metrics for {len(metrics.get('objectives', []))} successful runs") + + # Get LLM recommendations for modeling based on inspection results + print("\nGetting LLM recommendations for modeling...") + model_configs = self._call_llm('model', { + 'log_data': log_data, + 'metrics': metrics, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs + }) + print(f"LLM model config: {model_configs['model']}") + + # Step 3: Evaluate models with LLM config + print("\nStep 3: Evaluating models...") + model_results = self.evaluate_models( + log_data, metrics, + kernel_type=model_configs['model']['kernel_type'], + preprocessing=model_configs['model']['preprocessing'], + acquisition=model_configs['model']['acquisition'], + surrogate_weight=model_configs['model']['surrogate_weight'] + ) + + # Get LLM recommendations for parameter selection based on all previous results + print("\nGetting LLM recommendations for parameter selection...") + selection_configs = self._call_llm('agglomerate', { + 'log_data': log_data, + 'metrics': metrics, + 'model_results': model_results, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs, + 'model_configs': model_configs + }) + print(f"LLM selection config: {selection_configs['selection']}") + + # Step 4: Generate parameters with LLM config + print("\nStep 4: Generating parameters...") + self.generate_parameters( + log_data, metrics, model_results, num_runs, + selection_method=selection_configs['selection']['method'], + quality_weight=selection_configs['selection']['quality_weight'], + uncertainty_bonus=selection_configs['selection']['uncertainty_bonus'] + ) + + def inspect_logs(self) -> Dict[str, Any]: + """Step 1: Inspect all .log and .json logs recursively""" + log_dir = "logs" + pattern = f"{self.platform}_{self.design}_run" + + log_data = { + 'runs': [], + 'summary': { + 'total_runs': 0, + 'successful_runs': 0, + 'failed_runs': 0 + } + } + + if not os.path.exists(log_dir): + return log_data + + run_groups = {} + + for root, _, files in os.walk(log_dir): + for log_file in files: + if log_file.endswith(('.log', '.json')): + log_path = os.path.join(root, log_file) + + if log_file.startswith(pattern) or (self.platform in root and self.design in root): + + run_id = "main" + # case1：eg. logs/asap7_aes_run1.log + m = re.search(r'_run(\d+)\.log$', log_file) + if m: + run_id = f"base_{m.group(1)}" + # case2：path includes base_* + elif 'base_' in root: + run_id = os.path.basename(root) + + run_data = process_log_file(log_path) + + # initialize run + if run_id not in run_groups: + run_groups[run_id] = { + 'run_id': run_id, + 'success': True, + 'metrics': {}, + 'errors': [], + 'files': [] + } + + # clustering + run_groups[run_id]['success'] &= run_data.get('success', True) + run_groups[run_id]['files'].append(log_path) + + if 'metrics' in run_data and run_data['metrics']: + run_groups[run_id]['metrics'].update(run_data['metrics']) + + if 'errors' in run_data and run_data['errors']: + run_groups[run_id]['errors'].extend(run_data['errors']) + + for run_id, run_data in run_groups.items(): + print(f"DEBUG: Run {run_id} success: {run_data['success']}") + print(f"DEBUG: Run {run_id} metrics: {run_data['metrics']}") + print(f"DEBUG: Run {run_id} errors: {run_data['errors']}") + print(f"DEBUG: Run {run_id} files: {run_data['files']}") + + log_data['runs'].append(run_data) + log_data['summary']['total_runs'] += 1 + if run_data['success']: + log_data['summary']['successful_runs'] += 1 + else: + log_data['summary']['failed_runs'] += 1 + + return log_data + + def analyze_metrics(self, log_data: Dict[str, Any], n_clusters: int, correlation_threshold: float) -> Dict[str, Any]: + """Step 2: Analyze metrics from log data with improved analysis""" + metrics = { + 'objectives': [], + 'surrogates': [], + 'correlations': {}, + 'structure_analysis': {} + } + + # Extract feature vectors and objectives + feature_vectors = [] + objective_values = [] + surrogate_values = [] + + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + run_metrics = run['metrics'] + obj_values = self._calculate_objective(run) + + if obj_values['value'] is not None or obj_values['surrogate'] is not None: + # Extract parameter values as features + params = [] + for param in self.parameter_names: + params.append(float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0)))) + feature_vectors.append(params) + + objective_values.append(obj_values['value'] if obj_values['value'] is not None else np.nan) + surrogate_values.append(obj_values['surrogate'] if obj_values['surrogate'] is not None else np.nan) + + # Track correlations and other metrics + if obj_values['value'] is not None: + metrics['objectives'].append(obj_values['value']) + if obj_values['surrogate'] is not None: + metrics['surrogates'].append(obj_values['surrogate']) + + if obj_values['value'] is not None and obj_values['surrogate'] is not None: + if 'real_vs_surrogate' not in metrics['correlations']: + metrics['correlations']['real_vs_surrogate'] = [] + metrics['correlations']['real_vs_surrogate'].append({ + 'real': obj_values['value'], + 'surrogate': obj_values['surrogate'] + }) + + if feature_vectors: + X = np.array(feature_vectors) + Y = np.array(objective_values) + Y_surrogate = np.array(surrogate_values) + + # Use improved inspection functions + metrics['distribution_analysis'] = inspect_data_distribution(X, Y, Y_surrogate) + metrics['structure_analysis'] = inspect_data_structure(X, Y, { + 'n_clusters': n_clusters, + 'correlation_threshold': correlation_threshold + }) + + # Extract model recommendations if available (from new functions) + if 'model_recommendations' in metrics['structure_analysis']: + metrics['model_recommendations'] = metrics['structure_analysis']['model_recommendations'] + + # Add objective-specific metrics + if self.objective == 'ECP': + metrics['clock_period_impact'] = {} + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + period = float(run['metrics'].get('clock_period', 0)) + if period > 0: + if period not in metrics['clock_period_impact']: + metrics['clock_period_impact'][period] = { + 'final_slack': [], + 'cts_slack': [] + } + if 'worst_slack' in run['metrics']: + metrics['clock_period_impact'][period]['final_slack'].append( + float(run['metrics']['worst_slack'])) + if 'cts_ws' in run['metrics']: + metrics['clock_period_impact'][period]['cts_slack'].append( + float(run['metrics']['cts_ws'])) + + elif self.objective == 'DWL': + metrics['wirelength_progression'] = [] + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + if 'cts_wirelength' in run['metrics'] and 'total_wirelength' in run['metrics']: + metrics['wirelength_progression'].append({ + 'cts': float(run['metrics']['cts_wirelength']), + 'final': float(run['metrics']['total_wirelength']) + }) + + return metrics + + def evaluate_models(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + kernel_type: str, preprocessing: str, acquisition: str, surrogate_weight: float) -> Dict[str, Any]: + """Step 3: Use improved model functions to evaluate parameter quality""" + model_results = {} + + # Build context from log data and metrics + context = { + 'log_data': log_data, + 'metrics': metrics, + 'design_config': self.design_config, + 'initial_params': self.initial_params, + 'model_recommendations': metrics.get('model_recommendations', {}) + } + + # Use model recommendations if available (from new functions) + if 'model_recommendations' in metrics: + kernel_type = metrics['model_recommendations'].get('kernel_type', kernel_type) + preprocessing = 'robust' if metrics['model_recommendations'].get('needs_feature_scaling', True) else 'none' + + # Call appropriate model functions with improved modeling + if self.objective == 'ECP': + model_results = evaluate_timing_model(context) + elif self.objective == 'DWL': + model_results = evaluate_wirelength_model(context) + + # Add model configuration used + model_results['configuration'] = { + 'kernel_type': kernel_type, + 'preprocessing': preprocessing, + 'acquisition': acquisition, + 'surrogate_weight': surrogate_weight + } + + return model_results + + def generate_parameters(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + model_results: Dict[str, Any], num_runs: int, + selection_method: str = 'hybrid', quality_weight: float = 0.7, + uncertainty_bonus: float = 0.2, model_config: Dict[str, Any] = None) -> None: + """Step 4: Generate parameter combinations and write to CSV""" + # Get list of parameters to optimize from constraints + param_names = list(self.param_constraints.keys()) + print(f"\nGenerating parameters for {len(param_names)} variables:") + for name in param_names: + print(f" - {name}: {self.param_constraints[name]}") + + # Extract successful runs for training data + successful_params = [] + successful_objectives = [] + for run in log_data.get('runs', []): + if run.get('success', False) and 'metrics' in run: + params = {} + for param in param_names: + params[param] = float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0))) + successful_params.append(params) + + obj = self._calculate_objective(run) + successful_objectives.append(obj['value'] if obj['value'] is not None else obj['surrogate']) + + print(f"Using {len(successful_params)} successful runs as training data") + + # Convert to numpy arrays + if successful_params: + X = np.array([[params[name] for name in param_names] for params in successful_params]) + y = np.array(successful_objectives) + else: + print("Warning: No successful runs, using initial parameters as base") + X = np.array([[float(self.initial_params.get(name, 0)) for name in param_names]]) + y = np.array([0.0]) + + # Get kernel type from model config + kernel_type = model_config.get('kernel_type', 'matern') if model_config else 'matern' + print(f"\nCreating surrogate model with {kernel_type} kernel") + model = create_model(X, y, kernel_type=kernel_type) + + # Generate candidates + n_candidates = num_runs * 10 + print(f"Generating {n_candidates} candidate points") + candidates = latin_hypercube(n_candidates, len(param_names)) + + # Scale candidates to parameter ranges + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + candidates[:, i] = candidates[:, i] * (max_val - min_val) + min_val + + # Get predictions + predictions, uncertainties = model.predict(candidates, return_std=True) + + # Select points + print(f"\nSelecting points using {selection_method} method") + print(f"Quality weight: {quality_weight}, Uncertainty bonus: {uncertainty_bonus}") + quality_scores = create_quality_scores(candidates, y, predictions, uncertainties) + selected_indices = select_points( + candidates, quality_scores, + method=selection_method, + n_points=num_runs, + config={"quality_weight": quality_weight, + "uncertainty_bonus": uncertainty_bonus} + ) + + selected_params = candidates[selected_indices] + + # Validate domain constraints + print("\nValidating domain constraints...") + valid_params = [] + for params in selected_params: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + else: + print("Warning: Parameter set failed domain constraints") + + print(f"Found {len(valid_params)} valid parameter sets out of {len(selected_params)}") + + # Generate more if needed + while len(valid_params) < num_runs: + needed = num_runs - len(valid_params) + print(f"Generating {needed} additional parameter sets...") + new_candidates = latin_hypercube(needed, len(param_names)) + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + new_candidates[:, i] = new_candidates[:, i] * (max_val - min_val) + min_val + + for params in new_candidates: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + if len(valid_params) >= num_runs: + break + + # Write to CSV + print(f"\nWriting {num_runs} parameter sets to CSV...") + self._write_params_to_csv(valid_params[:num_runs]) + + def _calculate_objective(self, run: Dict[str, Any]) -> Dict[str, float]: + """Calculate objective value and surrogate from run metrics""" + metrics = run.get('metrics', {}) + result = {'value': None, 'surrogate': None} + + if self.objective == 'ECP': + if 'clock_period' in metrics: + period = float(metrics['clock_period']) + # Real ECP from final worst slack + if 'worst_slack' in metrics: + result['value'] = period - float(metrics['worst_slack']) + # Surrogate ECP from CTS worst slack + if 'cts_ws' in metrics: + result['surrogate'] = period - float(metrics['cts_ws']) + + elif self.objective == 'DWL': + # Real wirelength from detailed route + if 'total_wirelength' in metrics: + result['value'] = float(metrics['total_wirelength']) + # Surrogate wirelength from CTS + if 'cts_wirelength' in metrics: + result['surrogate'] = float(metrics['cts_wirelength']) + + elif self.objective == 'COMBO': + # Get weights from environment variables + try: + ecp_weight = float(os.environ.get('ECP_WEIGHT')) + wl_weight = float(os.environ.get('WL_WEIGHT')) + ecp_weight_surrogate = float(os.environ.get('ECP_WEIGHT_SURROGATE')) + wl_weight_surrogate = float(os.environ.get('WL_WEIGHT_SURROGATE')) + except (ValueError, TypeError): + raise ValueError("Weights not properly set in environment variables.") + + # Calculate real ECP and WL values + ecp_value = None + wl_value = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'worst_slack' in metrics: + ecp_value = clock_period - float(metrics['worst_slack']) + if 'total_wirelength' in metrics: + wl_value = float(metrics['total_wirelength']) + + # Calculate surrogate ECP and WL values + ecp_surrogate = None + wl_surrogate = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'cts_ws' in metrics: + ecp_surrogate = clock_period - float(metrics['cts_ws']) + if 'cts_wirelength' in metrics: + wl_surrogate = float(metrics['cts_wirelength']) + + # Calculate weighted objective for real values + if ecp_value is not None and wl_value is not None: + result['value'] = ecp_weight * ecp_value + wl_weight * wl_value + elif ecp_value is not None: + result['value'] = ecp_weight * ecp_value + elif wl_value is not None: + result['value'] = wl_weight * wl_value + + # Calculate weighted surrogate objective + if ecp_surrogate is not None and wl_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + wl_weight_surrogate * wl_surrogate + elif ecp_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + elif wl_surrogate is not None: + result['surrogate'] = wl_weight_surrogate * wl_surrogate + + return result + + def _validate_domain_constraints(self, params: Dict[str, Any]) -> bool: + """Validate parameter combinations against domain constraints""" + # 1. Core utilization vs cell padding + core_util = float(params.get('core_util', 0)) + gp_pad = float(params.get('cell_pad_global', 0)) + dp_pad = float(params.get('cell_pad_detail', 0)) + + if core_util > 80 and (gp_pad > 2 or dp_pad > 2): + print(f"Domain constraint failed: core_util > 80 and gp_pad > 2 or dp_pad > 2") + return False + + # 2. TNS end percent vs place density + tns_end = float(params.get('tns', 0)) + place_density = float(params.get('lb_addon', 0)) + + if tns_end < 70 and place_density > 0.7: + print(f"Domain constraint failed: tns_end < 70 and place_density > 0.7") + return False + + # 3. CTS cluster constraints + cts_size = float(params.get('cts_size', 0)) + cts_diameter = float(params.get('cts_diameter', 0)) + + if cts_size > 30 and cts_diameter < 100: + print(f"Domain constraint failed: cts_size > 30 and cts_diameter < 100") + return False + + return True + + def _write_params_to_csv(self, params_list: List[Dict[str, Any]]) -> None: + """Write the new parameter sets to the expected CSV file for the next iteration""" + csv_file = f"designs/{self.platform}/{self.design}/{self.platform}_{self.design}.csv" + + # Ensure parameters are in correct order and properly typed + with open(csv_file, 'w', newline='\n') as f: # Explicitly use Unix line endings + writer = csv.writer(f) + # Write header in correct order + writer.writerow(self.parameter_names) + + # Write parameter rows + for params in params_list: + row = [] + for param_name in self.parameter_names: + value = params.get(param_name) + if value is None: + print(f"Warning: Missing value for parameter {param_name}") + continue + + # Apply type constraints + constraint = self.param_constraints[param_name] + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param_name} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + + except (ValueError, TypeError) as e: + print(f"Error converting {param_name} value '{value}' to {param_type}: {e}") + continue + + row.append(value) + + if len(row) == len(self.parameter_names): + writer.writerow(row) + else: + print(f"Warning: Skipping incomplete parameter set") + + print(f"New parameter sets written to {csv_file}") + + def _parse_llm_output(self, llm_response: str) -> List[Dict[str, Any]]: + """Parse the LLM's response and enforce parameter constraints""" + try: + param_sets = json.loads(llm_response) + except json.JSONDecodeError as e: + print(f"Error parsing LLM response: {e}") + return [] + + constrained_params = [] + for param_set in param_sets: + ordered_params = {} + valid = True + for param in self.parameter_names: + value = param_set.get(param) + if value is None: + print(f"Parameter '{param}' is missing in the LLM output.") + valid = False + break + + constraint = self.param_constraints.get(param) + if constraint: + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + elif param_type != 'float': + raise ValueError(f"Unsupported parameter type: {param_type}") + + ordered_params[param] = value + except (ValueError, TypeError) as e: + print(f"Parameter '{param}' has invalid value '{value}': {e}") + valid = False + break + else: + print(f"Unknown parameter '{param}' in parameter set.") + valid = False + break + + if valid and self._validate_domain_constraints(ordered_params): + constrained_params.append(ordered_params) + else: + print(f"Parameter set {ordered_params} failed validation and will be discarded.") + + return constrained_params + + def generate_initial_parameters(self, num_runs: int) -> None: + """Generate initial random parameters and write them to CSV using the same method as subsequent iterations""" + params_list = [] + for _ in range(num_runs): + params = {} + for param in self.parameter_names: + info = self.param_constraints[param] + param_type = info['type'] + min_value, max_value = info['range'] + if param_type == 'int': + value = random.randint(int(min_value), int(max_value)) + elif param_type == 'float': + value = random.uniform(min_value, max_value) + else: + continue # Skip unsupported types + params[param] = value + params_list.append(params) + + # Use the same method to write parameters to CSV + self._write_params_to_csv(params_list) + +def main(): + if len(sys.argv) != 5: + print("Usage: optimize.py ") + sys.exit(1) + + platform = sys.argv[1] + design = sys.argv[2] + objective = sys.argv[3] + num_runs = int(sys.argv[4]) + + workflow = OptimizationWorkflow(platform, design, objective) + workflow.run_iteration(num_runs) # Use the run_iteration method instead of individual steps + +if __name__ == "__main__": + main() diff --git a/flow-Agent/comparison/optimize_rag_only.py b/flow-Agent/comparison/optimize_rag_only.py new file mode 100644 index 0000000..0a650d5 --- /dev/null +++ b/flow-Agent/comparison/optimize_rag_only.py @@ -0,0 +1,1460 @@ +#!/usr/bin/env python3 + +import json +import os +import sys +import re +import numpy as np +from typing import Dict, List, Any, Tuple, Optional +import anthropic +import csv +import random +from rag.util import answerWithRAG +from rag.index import load_embeddings_and_docs, build_and_save_embeddings +from sentence_transformers import SentenceTransformer +import torch +from pathlib import Path + +from openai import OpenAI +from inspectfuncs import * +from modelfuncs import * +from agglomfuncs import * + +def process_log_file(log_path: str) -> Dict[str, Any]: + """Process a single log file to extract relevant metrics""" + run_data = { + 'file': os.path.basename(log_path), + 'success': False, + 'metrics': {}, + 'errors': [] + } + + with open(log_path, 'r') as f: + content = f.read() + print(f"File size: {len(content)} characters") + + # Extract timing information + timing_metrics = extract_timing_metrics(content) + run_data['metrics'].update(timing_metrics) + + # Extract wirelength information + wl_metrics = extract_wirelength_metrics(content) + run_data['metrics'].update(wl_metrics) + + # Extract any errors + errors = extract_errors(content) + run_data['errors'].extend(errors) + + # Determine success based on completion markers and errors + run_data['success'] = is_run_successful(content, errors) + + return run_data + +def extract_timing_metrics(log_content: str) -> Dict[str, float]: + """Extract timing-related metrics from log content""" + metrics = {} + + # Extract worst slack (final) + slack_match = re.search(r'(?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + if slack_match: + metrics['worst_slack'] = float(slack_match.group(1)) + + # Extract CTS worst slack + # cts_slack_match = re.search(r'(?:CTS|Clock Tree) (?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + cts_slack_match = re.search(r'Timing-driven:\s*(?:worst slack|WNS)\s+([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_slack_match: + metrics['cts_ws'] = float(cts_slack_match.group(1)) + + # Extract clock period + # period_match = re.search(r'[Cc]lock period:\s*([\d.]+)', log_content) + period_match = re.search(r'clock period to\s*([\d.]+)', log_content) + if period_match: + metrics['clock_period'] = float(period_match.group(1)) + + # Extract TNS + # tns_match = re.search(r'(?:Total negative slack|TNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + tns_match = re.search(r'"finish__timing__setup__tns"\s*:\s*([-\d.eE]+)', log_content) + if tns_match: + metrics['tns'] = float(tns_match.group(1)) + + return metrics + +def extract_wirelength_metrics(log_content: str) -> Dict[str, float]: + """Extract wirelength-related metrics from log content""" + metrics = {} + + # Extract total wirelength + wl_match = re.search(r'Total wirelength: ([\d.]+)', log_content) + if wl_match: + metrics['total_wirelength'] = float(wl_match.group(1)) + + # Extract estimated wirelength after CTS + # cts_wl_match = re.search(r'Estimated wirelength: ([\d.]+)', log_content) + cts_wl_match = re.search(r'"?cts__route__wirelength__estimated"?\s*[:=]\s*([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_wl_match: + metrics['cts_wirelength'] = float(cts_wl_match.group(1)) + + return metrics + +def extract_errors(log_content: str) -> List[str]: + """Extract error messages from log content""" + errors = [] + + # Look for common error patterns + error_patterns = [ + r'Error: .*', + r'ERROR: .*', + r'FATAL: .*', + r'Failed: .*' + ] + + for pattern in error_patterns: + matches = re.finditer(pattern, log_content, re.MULTILINE) + errors.extend(match.group(0) for match in matches) + + return errors + +def is_run_successful(log_content: str, errors: List[str]) -> bool: + """Determine if a run was successful based on log content and errors""" + if errors: + return False + + # Look for completion markers + completion_markers = [ + 'Flow complete', + 'Finished successfully' + 'Writing out GDS/OAS', + '6_report' + ] + + return any(marker in log_content for marker in completion_markers) + +class OptimizationWorkflow: + def __init__(self, platform: str, design: str, objective: str): + self.platform = platform + self.design = design + self.objective = objective.upper() # Convert to uppercase + + # Load configuration + self.config = self._load_config() + + # Find the design configuration + configurations = self.config.get('configurations', []) + for config in configurations: + if ( + config['platform'].lower() == self.platform.lower() + and config['design'].lower() == self.design.lower() + and config['goal'].upper() == self.objective + ): + self.design_config = config + break + else: + raise ValueError( + f"No configuration found for platform={self.platform}, design={self.design}, objective={self.objective}" + ) + + # Define initial clock periods for each design and platform + initial_clock_periods = { + ('asap7', 'aes'): 400, # in picoseconds + ('asap7', 'ibex'): 1260, # in picoseconds + ('asap7', 'jpeg'): 1100, # in picoseconds + ('sky130hd', 'aes'): 4.5, # in nanoseconds + ('sky130hd', 'ibex'): 10.0,# in nanoseconds + ('sky130hd', 'jpeg'): 8.0, # in nanoseconds + } + + # Get the initial clock period for the current platform and design + key = (self.platform.lower(), self.design.lower()) + if key in initial_clock_periods: + self.initial_clk_period = initial_clock_periods[key] + else: + raise ValueError(f"Initial clock period not defined for platform={self.platform}, design={self.design}") + + # Calculate clock period range + min_clk = self.initial_clk_period * 0.7 + max_clk = self.initial_clk_period * 1.3 + + # Define parameter names in the expected order + self.parameter_names = [ + 'core_util', + 'cell_pad_global', + 'cell_pad_detail', + 'synth_flatten', + 'pin_layer', + 'above_layer', + 'tns', + 'lb_addon', + 'cts_size', + 'cts_diameter', + 'enable_dpo', + 'clk_period' + ] + + # Set all parameter constraints including clock period range + self.param_constraints = { + 'core_util': {'type': 'int', 'range': [20, 99]}, + 'cell_pad_global': {'type': 'int', 'range': [0, 4]}, + 'cell_pad_detail': {'type': 'int', 'range': [0, 4]}, + 'synth_flatten': {'type': 'int', 'range': [0, 1]}, + 'pin_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'above_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'tns': {'type': 'int', 'range': [70, 100]}, + 'lb_addon': {'type': 'float', 'range': [0.00, 0.99]}, + 'cts_size': {'type': 'int', 'range': [10, 40]}, + 'cts_diameter': {'type': 'int', 'range': [80, 120]}, + 'enable_dpo': {'type': 'int', 'range': [0, 1]}, + 'clk_period': {'type': 'float', 'range': [min_clk, max_clk]} + } + + # Load initial parameters and SDC context + self.initial_params = self._load_initial_params() + self.sdc_context = self._load_sdc_context() + + emb_np, docs, docsDict = load_embeddings_and_docs() + self.rag_embeddings = torch.tensor(emb_np).cpu() + self.rag_docs = docs + self.rag_docsDict = docsDict + print("[INFO] Loading embedding model...") + model_path = Path(__file__).parent / "models" / "mxbai-embed-large-v1" + model_path = model_path.resolve() + self.rag_model = SentenceTransformer(str(model_path)) + + + def _load_config(self) -> Dict[str, Any]: + """Load the configuration from 'opt_config.json'.""" + with open('opt_config.json', 'r') as f: + config = json.load(f) + return config + + def _load_initial_params(self) -> Dict[str, Any]: + """Load initial parameters from the design's config.mk file""" + config_path = f"designs/{self.platform}/{self.design}/config.mk" + params = {} + with open(config_path, 'r') as f: + for line in f: + if line.startswith('export'): + parts = line.strip().split('=', 1) + if len(parts) == 2: + key = parts[0].replace('export', '').strip() + value = parts[1].strip() + params[key] = value + return params + + def _load_sdc_context(self) -> Dict[str, Any]: + """Load SDC context including special case for JPEG""" + sdc_context = {} + + # Determine SDC filename based on platform/design + if self.platform.lower() == 'asap7' and self.design.lower() == 'jpeg': + sdc_file = 'jpeg_encoder15_7nm.sdc' + else: + sdc_file = 'constraint.sdc' + + sdc_path = f"designs/{self.platform}/{self.design}/{sdc_file}" + + # Read SDC file + try: + with open(sdc_path, 'r') as f: + sdc_content = f.read() + + # Extract clock period + clock_period_match = re.search(r'set clk_period\s+([\d.]+)', sdc_content) + if clock_period_match: + sdc_context['clock_period'] = float(clock_period_match.group(1)) + + # Store full content for context + sdc_context['content'] = sdc_content + sdc_context['filename'] = sdc_file + + except Exception as e: + print(f"Warning: Could not load SDC file {sdc_path}: {str(e)}") + sdc_context['error'] = str(e) + + return sdc_context + + # def _generate_llm_prompt(self, stage: str, data: Dict[str, Any]) -> str: + # """Generate LLM prompt for different stages""" + + # # Include parameter constraints in the prompt + # constraints_text = "Parameter Constraints:\n" + # for param, info in self.param_constraints.items(): + # param_type = info['type'] + # param_range = info['range'] + # constraints_text += f"- {param} ({param_type}, range: {param_range})\n" + + # # Construct the prompt based on the stage + # if stage == 'inspect': + # prompt = ( + # f"**Stage: Inspect**\n" + # "In this stage, we analyze the data from previous optimization runs to identify patterns, trends, and insights.\n\n" + # # f"Data to analyze:\n{json.dumps(data, indent=2)}\n\n" + # f"Data to analyze:\n{json.dumps(data, indent=2, default=str)}\n\n" + # "Please analyze the data and provide insights on:\n" + # "1. Key patterns in successful vs unsuccessful runs.\n" + # "2. Parameter ranges that appear promising.\n" + # "3. Any timing or wirelength trends.\n" + # "4. Recommendations for subsequent runs.\n" + # ) + # elif stage == 'model': + # prompt = ( + # f"**Stage: Model**\n" + # "In this stage, we decide how to model the optimization problem based on the data analysis.\n\n" + # # f"Data for modeling:\n{json.dumps(data, indent=2)}\n\n" + # f"Data for modeling:\n{json.dumps(data, indent=2, default=str)}\n\n" + # "Please suggest:\n" + # "1. Appropriate modeling techniques.\n" + # "2. Key parameters to focus on.\n" + # "3. Surrogate model recommendations.\n" + # "4. Acquisition function choices.\n" + # ) + # elif stage == 'agglomerate': + # prompt = ( + # f"**Stage: Agglomerate**\n" + # "In this stage, we generate new parameter combinations to explore in the next optimization runs.\n\n" + # "Please provide a list of new parameter sets to try, ensuring they respect the domain constraints below.\n\n" + # f"{constraints_text}\n" + # "Each parameter set should be a dictionary with parameter names and their suggested values.\n" + # "**Important:** Make sure all parameter sets satisfy the domain constraints before suggesting them.\n" + # ) + # else: + # prompt = ( + # f"**Stage: {stage.capitalize()}**\n" + # # f"Data:\n{json.dumps(data, indent=2)}\n\n" + # f"Data:\n{json.dumps(data, indent=2, default=str)}\n\n" + # "Please provide guidance based on the above data.\n" + # ) + + # return prompt + + def _generate_llm_prompt(self, stage: str, data: Dict[str, Any]) -> str: + + constraints_text = "Parameter Constraints:\n" + for param, info in self.param_constraints.items(): + param_type = info['type'] + param_range = info['range'] + constraints_text += f"- {param} ({param_type}, range: {param_range})\n" + + tool_instructions = { + 'inspect': ( + f"**Stage: Inspect**\n" + "In this stage, we analyze the data from previous optimization runs to identify patterns, trends, and insights.\n\n" + f"Data to analyze:\n{json.dumps(data, indent=2, default=str)}\n\n" + "Please analyze the data and provide insights on:\n" + "1. Key patterns in successful vs unsuccessful runs.\n" + "2. Parameter ranges that appear promising.\n" + "3. Any timing or wirelength trends.\n" + "4. Recommendations for subsequent runs.\n" + "5. We hope to further reduce the total wirelength.\n" + ), + + 'model': ( + f"**Stage: Model**\n" + "In this stage, we decide how to model the optimization problem based on the data analysis.\n\n" + f"Data for modeling:\n{json.dumps(data, indent=2, default=str)}\n\n" + "Please suggest:\n" + "1. Appropriate modeling techniques.\n" + "2. Key parameters to focus on.\n" + "3. Surrogate model recommendations.\n" + "4. Acquisition function choices.\n" + ), + + 'agglomerate': ( + f"**Stage: Agglomerate**\n" + "In this stage, we generate new parameter combinations to explore in the next optimization runs.\n\n" + "Please provide a list of new parameter sets to try, ensuring they respect the domain constraints below.\n\n" + f"{constraints_text}\n" + "Each parameter set should be a dictionary with parameter names and their suggested values.\n" + "**Important:** Make sure all parameter sets satisfy the domain constraints before suggesting them.\n" + ) + } + + stage_contexts = { + 'inspect': ( + f"metrics analyze: Total runs={data.get('log_data', {}).get('summary', {}).get('total_runs', 0)}, " + f"successful runs ={data.get('log_data', {}).get('summary', {}).get('successful_runs', 0)}" + ), + 'model': "Configure modeling methods based on inspection results", + 'agglomerate': "Configure parameter selection strategy based on modeling results" + } + + prompt = f"""**stages:{stage.upper()}** + + {stage_contexts.get(stage, '')} + + {tool_instructions.get(stage, '')} + + **Important: Use **tool calls only**, and generate text responses!** + """ + # ========= 拼接 RAG ========= + rag_context = "" + if self.rag_model is not None and self.rag_embeddings is not None: + try: + print("[DEBUG] RAG: Starting retrieval...") + query = ( + f"Stage: {stage}. Objective: {self.objective}. " + f"Focus on analyzing {stage}-related optimization results. " + f"Important metrics include wirelength, timing, area, and success rate. " + f"Find relevant OpenROAD documentation, parameter tuning guides, and failure pattern examples." + ) + rag_context = answerWithRAG( + query, + self.rag_embeddings, + self.rag_model, + self.rag_docs, + self.rag_docsDict + ) + print(f"[DEBUG] RAG: Retrieved context length = {len(rag_context)}") + if rag_context.strip(): + prompt += ( + "\n\n=== Retrieved OpenROAD Documentation (via RAG) ===\n" + f"{rag_context}\n" + "==============================================" + ) + print("[DEBUG] RAG: Context successfully added to prompt.") + else: + print("[DEBUG] RAG: Empty context retrieved.") + except Exception as e: + prompt += f"\n\n[WARN] RAG retrieval failed: {e}" + + return prompt + + def _call_llm(self, stage: str, data: Dict[str, Any]) -> Dict[str, Any]: + """Call Claude to get recommendations for optimization parameters""" + print(f"\n=== Calling LLM for {stage} stage ===") + + # Hardcode API key + # api_key = ""#PUT YOUR KEY HERE + + # client = anthropic.Anthropic(api_key=api_key) + client = OpenAI( + base_url="https://ai.gitee.com/v1", + api_key=""#PUT YOUR KEY HERE, + ) + + tools = [ + { + "type": "function", + "function": { + "name": "configure_inspection", + "description": "Configure data inspection parameters", + "parameters": { + "type": "object", + "properties": { + "n_clusters": { + "type": "integer", + "description": "Number of clusters for structure analysis", + "minimum": 2, + "maximum": 10 + }, + "correlation_threshold": { + "type": "number", + "description": "Threshold for considering correlations significant", + "minimum": 0, + "maximum": 1 + } + }, + "required": ["n_clusters", "correlation_threshold"] + } + } + }, + { + "type": "function", + "function": { + "name": "configure_model", + "description": "Configure modeling approach", + "parameters": { + "type": "object", + "properties": { + "kernel_type": { + "type": "string", + "enum": ["rbf", "matern", "rational"], + "description": "Type of kernel to use" + }, + "preprocessing": { + "type": "string", + "enum": ["standard", "robust", "none"], + "description": "Type of preprocessing to apply" + }, + "acquisition": { + "type": "string", + "enum": ["ei", "ucb", "pi"], + "description": "Acquisition function to use" + }, + "surrogate_weight": { + "type": "number", + "description": "Weight to give surrogate values", + "minimum": 0, + "maximum": 1 + } + }, + "required": ["kernel_type", "preprocessing", "acquisition", "surrogate_weight"] + } + } + }, + { + "type": "function", + "function": { + "name": "configure_selection", + "description": "Configure point selection strategy", + "parameters": { + "type": "object", + "properties": { + "method": { + "type": "string", + "enum": ["entropy", "kmeans", "hybrid", "graph"], + "description": "Selection method to use" + }, + "quality_weight": { + "type": "number", + "description": "Weight between quality and diversity", + "minimum": 0, + "maximum": 1 + }, + "uncertainty_bonus": { + "type": "number", + "description": "Weight for uncertainty in quality scores", + "minimum": 0, + "maximum": 1 + } + }, + "required": ["method", "quality_weight", "uncertainty_bonus"] + } + } + } + ] + + # tools = [ + # { + # "name": "configure_inspection", + # "description": "Configure data inspection parameters", + # "input_schema": { + # "type": "object", + # "properties": { + # "n_clusters": { + # "type": "integer", + # "description": "Number of clusters for structure analysis", + # "minimum": 2, + # "maximum": 10 + # }, + # "correlation_threshold": { + # "type": "number", + # "description": "Threshold for considering correlations significant", + # "minimum": 0, + # "maximum": 1 + # } + # }, + # "required": ["n_clusters", "correlation_threshold"] + # } + # }, + # { + # "name": "configure_model", + # "description": "Configure modeling approach", + # "input_schema": { + # "type": "object", + # "properties": { + # "kernel_type": { + # "type": "string", + # "enum": ["rbf", "matern", "rational"], + # "description": "Type of kernel to use" + # }, + # "preprocessing": { + # "type": "string", + # "enum": ["standard", "robust", "none"], + # "description": "Type of preprocessing to apply" + # }, + # "acquisition": { + # "type": "string", + # "enum": ["ei", "ucb", "pi"], + # "description": "Acquisition function to use" + # }, + # "surrogate_weight": { + # "type": "number", + # "description": "Weight to give surrogate values", + # "minimum": 0, + # "maximum": 1 + # } + # }, + # "required": ["kernel_type", "preprocessing", "acquisition", "surrogate_weight"] + # } + # }, + # { + # "name": "configure_selection", + # "description": "Configure point selection strategy", + # "input_schema": { + # "type": "object", + # "properties": { + # "method": { + # "type": "string", + # "enum": ["entropy", "kmeans", "hybrid", "graph"], + # "description": "Selection method to use" + # }, + # "quality_weight": { + # "type": "number", + # "description": "Weight between quality and diversity", + # "minimum": 0, + # "maximum": 1 + # }, + # "uncertainty_bonus": { + # "type": "number", + # "description": "Weight for uncertainty in quality scores", + # "minimum": 0, + # "maximum": 1 + # } + # }, + # "required": ["method", "quality_weight", "uncertainty_bonus"] + # } + # } + # ] + + # Get data summaries + if stage == 'inspect': + print("Generating data distribution and structure summaries...") + # Extract X and Y from successful runs if available + print("=== DEBUG: Checking data structure ===") + print(f"data keys: {list(data.keys()) if data else 'Empty data'}") + X = [] + Y = [] + if 'log_data' in data and 'runs' in data['log_data']: + print("✓ 'log_data' and 'runs' found in data") + print(f"Number of runs: {len(data['log_data']['runs'])}") + for run in data['log_data']['runs']: + if run['success'] and 'metrics' in run: + obj = self._calculate_objective(run) + if obj['value'] is not None or obj['surrogate'] is not None: + # Use parameters as X + params = [] + for param in self.param_constraints.keys(): + params.append(float(run.get('parameters', {}).get(param, 0))) + X.append(params) + # Use objective as Y + Y.append(obj['value'] if obj['value'] is not None else obj['surrogate']) + print(f" ✓ Added to X and Y: X={params}, Y={obj['value'] if obj['value'] is not None else obj['surrogate']}") + + if X and Y: + dist_summary = inspect_data_distribution(np.array(X), np.array(Y)) + # struct_summary = inspect_data_structure(np.array(X)) + struct_summary = inspect_data_structure(np.array(X), np.array(Y)) + print("dist_summary =", dist_summary) + print("struct_summary =", struct_summary) + print("DEBUG: len(X)=", len(X), " len(Y)=", len(Y)) + else: + print("No successful runs found, using empty summaries") + dist_summary = {} + struct_summary = {} + else: + dist_summary = {} + struct_summary = {} + + # Generate context message + context_message = self._generate_llm_prompt(stage, data) + print(f"Generated prompt with context for {stage}") + print("=== Context Message ===") + print(context_message) + print("========================") + + print("Making LLM API call...") + # response = client.messages.create( + response = client.chat.completions.create( + # model="claude-3-sonnet-20240229", + model="DeepSeek-V3", + messages=[{ + "role": "user", + "content": context_message + }], + # max_tokens=2048, + tools=tools, + tool_choice="auto", + # stream=True, + max_tokens=1024, + temperature=0.1, + # top_p=0.8, + # extra_body={ + # "top_k": 20, + # }, + # frequency_penalty=1.1, + + # messages=[{ + # "role": "user", + # "content": context_message + # }] + ) + + # Extract configurations + configs = {} + print("=== 完整API响应 ===") + print(f"Response type: {type(response)}") + print(f"Choices count: {len(response.choices)}") + print("\nReceived tool calls from LLM:") + message = response.choices[0].message + print(f"Message content: {getattr(message, 'content', 'No content')}") + print(f"Tool calls: {getattr(message, 'tool_calls', 'No tool calls')}") + + # 检查是否有工具调用 + if hasattr(message, 'tool_calls') and message.tool_calls: + for tool_call in message.tool_calls: + function_name = tool_call.function.name + function_args = json.loads(tool_call.function.arguments) + + print(f"- {function_name}: {function_args}") + + if function_name == 'configure_inspection': + configs['inspection'] = function_args + elif function_name == 'configure_model': + configs['model'] = function_args + elif function_name == 'configure_selection': + configs['selection'] = function_args + + # for block in response.content: + # if block.type == 'tool_use': + # print(f"- {block.name}: {block.input}") + # if block.name == 'configure_inspection': + # configs['inspection'] = block.input + # elif block.name == 'configure_model': + # configs['model'] = block.input + # elif block.name == 'configure_selection': + # configs['selection'] = block.input + + # Add default configs if missing + for key, default in [ + ('inspection', {"n_clusters": 5, "correlation_threshold": 0.5}), + ('model', {"kernel_type": "matern", "preprocessing": "robust", + "acquisition": "ei", "surrogate_weight": 0.8}), + ('selection', {"method": "hybrid", "quality_weight": 0.7, + "uncertainty_bonus": 0.2}) + ]: + if key not in configs: + print(f"Warning: No {key} config from LLM, using defaults: {default}") + configs[key] = default + + return configs + + def run_iteration(self, num_runs: int) -> None: + """Run a complete iteration of the optimization workflow""" + print(f"\n=== Starting optimization iteration for {self.platform}/{self.design} ===") + print(f"Objective: {self.objective}") + print(f"Number of runs requested: {num_runs}") + + # Step 1: Inspect logs + print("\nStep 1: Inspecting logs...") + log_data = self.inspect_logs() + print(f"Found {log_data['summary']['total_runs']} total runs, " + f"{log_data['summary']['successful_runs']} successful") + + # Get LLM recommendations for inspection and analysis + print("\nGetting LLM recommendations for inspection...") + inspect_configs = self._call_llm('inspect', { + 'log_data': log_data, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context + }) + print(f"LLM inspection config: {inspect_configs['inspection']}") + + # Step 2: Analyze metrics with LLM config + print("\nStep 2: Analyzing metrics...") + metrics = self.analyze_metrics( + log_data, + n_clusters=inspect_configs['inspection']['n_clusters'], + correlation_threshold=inspect_configs['inspection']['correlation_threshold'] + ) + print(f"Processed metrics for {len(metrics.get('objectives', []))} successful runs") + + # Get LLM recommendations for modeling based on inspection results + print("\nGetting LLM recommendations for modeling...") + model_configs = self._call_llm('model', { + 'log_data': log_data, + 'metrics': metrics, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs + }) + print(f"LLM model config: {model_configs['model']}") + + # Step 3: Evaluate models with LLM config + print("\nStep 3: Evaluating models...") + model_results = self.evaluate_models( + log_data, metrics, + kernel_type=model_configs['model']['kernel_type'], + preprocessing=model_configs['model']['preprocessing'], + acquisition=model_configs['model']['acquisition'], + surrogate_weight=model_configs['model']['surrogate_weight'] + ) + + # Get LLM recommendations for parameter selection based on all previous results + print("\nGetting LLM recommendations for parameter selection...") + selection_configs = self._call_llm('agglomerate', { + 'log_data': log_data, + 'metrics': metrics, + 'model_results': model_results, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs, + 'model_configs': model_configs + }) + print(f"LLM selection config: {selection_configs['selection']}") + + # Step 4: Generate parameters with LLM config + print("\nStep 4: Generating parameters...") + self.generate_parameters( + log_data, metrics, model_results, num_runs, + selection_method=selection_configs['selection']['method'], + quality_weight=selection_configs['selection']['quality_weight'], + uncertainty_bonus=selection_configs['selection']['uncertainty_bonus'] + ) + + def inspect_logs(self) -> Dict[str, Any]: + """Step 1: Inspect all .log and .json logs recursively""" + log_dir = "logs" + pattern = f"{self.platform}_{self.design}_run" + + log_data = { + 'runs': [], + 'summary': { + 'total_runs': 0, + 'successful_runs': 0, + 'failed_runs': 0 + } + } + + if not os.path.exists(log_dir): + return log_data + + run_groups = {} + + for root, _, files in os.walk(log_dir): + for log_file in files: + if log_file.endswith(('.log', '.json')): + log_path = os.path.join(root, log_file) + + # 匹配主日志或子目录日志 + if log_file.startswith(pattern) or (self.platform in root and self.design in root): + + # ---- 提取 run_id ---- + run_id = "main" # 默认 + # 情况1：主日志，例如 logs/asap7_aes_run1.log + m = re.search(r'_run(\d+)\.log$', log_file) + if m: + run_id = f"base_{m.group(1)}" + # 情况2：路径中包含 base_* + elif 'base_' in root: + run_id = os.path.basename(root) + + run_data = process_log_file(log_path) + + # 初始化 run 组 + if run_id not in run_groups: + run_groups[run_id] = { + 'run_id': run_id, + 'success': True, + 'metrics': {}, + 'errors': [], + 'files': [] + } + + # 聚合 + run_groups[run_id]['success'] &= run_data.get('success', True) + run_groups[run_id]['files'].append(log_path) + + if 'metrics' in run_data and run_data['metrics']: + run_groups[run_id]['metrics'].update(run_data['metrics']) + + if 'errors' in run_data and run_data['errors']: + run_groups[run_id]['errors'].extend(run_data['errors']) + + for run_id, run_data in run_groups.items(): + print(f"DEBUG: Run {run_id} success: {run_data['success']}") + print(f"DEBUG: Run {run_id} metrics: {run_data['metrics']}") + print(f"DEBUG: Run {run_id} errors: {run_data['errors']}") + print(f"DEBUG: Run {run_id} files: {run_data['files']}") + + log_data['runs'].append(run_data) + log_data['summary']['total_runs'] += 1 + if run_data['success']: + log_data['summary']['successful_runs'] += 1 + else: + log_data['summary']['failed_runs'] += 1 + + return log_data + + # def inspect_logs(self) -> Dict[str, Any]: + # """Step 1: Inspect all logs so far""" + # # log_dir = f"logs/{self.platform}/{self.design}" + # log_dir = "logs" + # pattern = f"{self.platform}_{self.design}_run" + # log_data = { + # 'runs': [], + # 'summary': { + # 'total_runs': 0, + # 'successful_runs': 0, + # 'failed_runs': 0 + # } + # } + + # # Ensure log directory exists + # if not os.path.exists(log_dir): + # return log_data + + # # Process each log file + # for log_file in os.listdir(log_dir): + # # if log_file.endswith('.log'): + # if log_file.endswith('.log') and log_file.startswith(pattern): + # run_data = process_log_file(os.path.join(log_dir, log_file)) + # print(f"DEBUG: Run success: {run_data['success']}") + # print(f"DEBUG: Run metrics: {run_data['metrics']}") + # print(f"DEBUG: Run errors: {run_data['errors']}") + # log_data['runs'].append(run_data) + + # # Update summary + # log_data['summary']['total_runs'] += 1 + # if run_data['success']: + # log_data['summary']['successful_runs'] += 1 + # else: + # log_data['summary']['failed_runs'] += 1 + + # return log_data + # def inspect_logs(self) -> Dict[str, Any]: + # """Step 1: Inspect all logs so far""" + # log_dir = f"logs/{self.platform}/{self.design}" + # log_data = { + # 'runs': [], + # 'summary': { + # 'total_runs': 0, + # 'successful_runs': 0, + # 'failed_runs': 0 + # } + # } + + # # Ensure log directory exists + # if not os.path.exists(log_dir): + # return log_data + + # # Process each log file + # for log_file in os.listdir(log_dir): + # if log_file.endswith('.log'): + # run_data = process_log_file(os.path.join(log_dir, log_file)) + # log_data['runs'].append(run_data) + + # # Update summary + # log_data['summary']['total_runs'] += 1 + # if run_data['success']: + # log_data['summary']['successful_runs'] += 1 + # else: + # log_data['summary']['failed_runs'] += 1 + + # return log_data + + def analyze_metrics(self, log_data: Dict[str, Any], n_clusters: int, correlation_threshold: float) -> Dict[str, Any]: + """Step 2: Analyze metrics from log data with improved analysis""" + metrics = { + 'objectives': [], + 'surrogates': [], + 'correlations': {}, + 'structure_analysis': {} + } + + # Extract feature vectors and objectives + feature_vectors = [] + objective_values = [] + surrogate_values = [] + + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + run_metrics = run['metrics'] + obj_values = self._calculate_objective(run) + + if obj_values['value'] is not None or obj_values['surrogate'] is not None: + # Extract parameter values as features + params = [] + for param in self.parameter_names: + params.append(float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0)))) + feature_vectors.append(params) + + objective_values.append(obj_values['value'] if obj_values['value'] is not None else np.nan) + surrogate_values.append(obj_values['surrogate'] if obj_values['surrogate'] is not None else np.nan) + + # Track correlations and other metrics + if obj_values['value'] is not None: + metrics['objectives'].append(obj_values['value']) + if obj_values['surrogate'] is not None: + metrics['surrogates'].append(obj_values['surrogate']) + + if obj_values['value'] is not None and obj_values['surrogate'] is not None: + if 'real_vs_surrogate' not in metrics['correlations']: + metrics['correlations']['real_vs_surrogate'] = [] + metrics['correlations']['real_vs_surrogate'].append({ + 'real': obj_values['value'], + 'surrogate': obj_values['surrogate'] + }) + + if feature_vectors: + X = np.array(feature_vectors) + Y = np.array(objective_values) + Y_surrogate = np.array(surrogate_values) + + # Use improved inspection functions + metrics['distribution_analysis'] = inspect_data_distribution(X, Y, Y_surrogate) + metrics['structure_analysis'] = inspect_data_structure(X, Y, { + 'n_clusters': n_clusters, + 'correlation_threshold': correlation_threshold + }) + + # Extract model recommendations if available (from new functions) + if 'model_recommendations' in metrics['structure_analysis']: + metrics['model_recommendations'] = metrics['structure_analysis']['model_recommendations'] + + # Add objective-specific metrics + if self.objective == 'ECP': + metrics['clock_period_impact'] = {} + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + period = float(run['metrics'].get('clock_period', 0)) + if period > 0: + if period not in metrics['clock_period_impact']: + metrics['clock_period_impact'][period] = { + 'final_slack': [], + 'cts_slack': [] + } + if 'worst_slack' in run['metrics']: + metrics['clock_period_impact'][period]['final_slack'].append( + float(run['metrics']['worst_slack'])) + if 'cts_ws' in run['metrics']: + metrics['clock_period_impact'][period]['cts_slack'].append( + float(run['metrics']['cts_ws'])) + + elif self.objective == 'DWL': + metrics['wirelength_progression'] = [] + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + if 'cts_wirelength' in run['metrics'] and 'total_wirelength' in run['metrics']: + metrics['wirelength_progression'].append({ + 'cts': float(run['metrics']['cts_wirelength']), + 'final': float(run['metrics']['total_wirelength']) + }) + + return metrics + + # def evaluate_models(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + # kernel_type: str, preprocessing: str, aciquisition: str, surrogate_weight: float) -> Dict[str, Any]: + # """Step 3: Use improved model functions to evaluate parameter quality""" + # model_results = {} + + def evaluate_models(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + kernel_type: str, preprocessing: str, acquisition: str, surrogate_weight: float) -> Dict[str, Any]: + """Step 3: Use improved model functions to evaluate parameter quality""" + model_results = {} + + # Build context from log data and metrics + context = { + 'log_data': log_data, + 'metrics': metrics, + 'design_config': self.design_config, + 'initial_params': self.initial_params, + 'model_recommendations': metrics.get('model_recommendations', {}) + } + + # Use model recommendations if available (from new functions) + if 'model_recommendations' in metrics: + kernel_type = metrics['model_recommendations'].get('kernel_type', kernel_type) + preprocessing = 'robust' if metrics['model_recommendations'].get('needs_feature_scaling', True) else 'none' + + # Call appropriate model functions with improved modeling + if self.objective == 'ECP': + model_results = evaluate_timing_model(context) + elif self.objective == 'DWL': + model_results = evaluate_wirelength_model(context) + + # Add model configuration used + model_results['configuration'] = { + 'kernel_type': kernel_type, + 'preprocessing': preprocessing, + 'acquisition': acquisition, + 'surrogate_weight': surrogate_weight + } + + return model_results + + def generate_parameters(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + model_results: Dict[str, Any], num_runs: int, + selection_method: str = 'hybrid', quality_weight: float = 0.7, + uncertainty_bonus: float = 0.2, model_config: Dict[str, Any] = None) -> None: + """Step 4: Generate parameter combinations and write to CSV""" + # Get list of parameters to optimize from constraints + param_names = list(self.param_constraints.keys()) + print(f"\nGenerating parameters for {len(param_names)} variables:") + for name in param_names: + print(f" - {name}: {self.param_constraints[name]}") + + # Extract successful runs for training data + successful_params = [] + successful_objectives = [] + for run in log_data.get('runs', []): + if run.get('success', False) and 'metrics' in run: + params = {} + for param in param_names: + params[param] = float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0))) + successful_params.append(params) + + obj = self._calculate_objective(run) + successful_objectives.append(obj['value'] if obj['value'] is not None else obj['surrogate']) + + print(f"Using {len(successful_params)} successful runs as training data") + + # Convert to numpy arrays + if successful_params: + X = np.array([[params[name] for name in param_names] for params in successful_params]) + y = np.array(successful_objectives) + else: + print("Warning: No successful runs, using initial parameters as base") + X = np.array([[float(self.initial_params.get(name, 0)) for name in param_names]]) + y = np.array([0.0]) + + # Get kernel type from model config + kernel_type = model_config.get('kernel_type', 'matern') if model_config else 'matern' + print(f"\nCreating surrogate model with {kernel_type} kernel") + model = create_model(X, y, kernel_type=kernel_type) + + # Generate candidates + n_candidates = num_runs * 10 + print(f"Generating {n_candidates} candidate points") + candidates = latin_hypercube(n_candidates, len(param_names)) + + # Scale candidates to parameter ranges + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + candidates[:, i] = candidates[:, i] * (max_val - min_val) + min_val + + # Get predictions + predictions, uncertainties = model.predict(candidates, return_std=True) + + # Select points + print(f"\nSelecting points using {selection_method} method") + print(f"Quality weight: {quality_weight}, Uncertainty bonus: {uncertainty_bonus}") + quality_scores = create_quality_scores(candidates, y, predictions, uncertainties) + selected_indices = select_points( + candidates, quality_scores, + method=selection_method, + n_points=num_runs, + config={"quality_weight": quality_weight, + "uncertainty_bonus": uncertainty_bonus} + ) + + selected_params = candidates[selected_indices] + + # Validate domain constraints + print("\nValidating domain constraints...") + valid_params = [] + for params in selected_params: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + else: + print("Warning: Parameter set failed domain constraints") + + print(f"Found {len(valid_params)} valid parameter sets out of {len(selected_params)}") + + # Generate more if needed + while len(valid_params) < num_runs: + needed = num_runs - len(valid_params) + print(f"Generating {needed} additional parameter sets...") + new_candidates = latin_hypercube(needed, len(param_names)) + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + new_candidates[:, i] = new_candidates[:, i] * (max_val - min_val) + min_val + + for params in new_candidates: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + if len(valid_params) >= num_runs: + break + + # Write to CSV + print(f"\nWriting {num_runs} parameter sets to CSV...") + self._write_params_to_csv(valid_params[:num_runs]) + + def _calculate_objective(self, run: Dict[str, Any]) -> Dict[str, float]: + """Calculate objective value and surrogate from run metrics""" + metrics = run.get('metrics', {}) + result = {'value': None, 'surrogate': None} + + if self.objective == 'ECP': + if 'clock_period' in metrics: + period = float(metrics['clock_period']) + # Real ECP from final worst slack + if 'worst_slack' in metrics: + result['value'] = period - float(metrics['worst_slack']) + # Surrogate ECP from CTS worst slack + if 'cts_ws' in metrics: + result['surrogate'] = period - float(metrics['cts_ws']) + + elif self.objective == 'DWL': + # Real wirelength from detailed route + if 'total_wirelength' in metrics: + result['value'] = float(metrics['total_wirelength']) + # Surrogate wirelength from CTS + if 'cts_wirelength' in metrics: + result['surrogate'] = float(metrics['cts_wirelength']) + + elif self.objective == 'COMBO': + # Get weights from environment variables + try: + ecp_weight = float(os.environ.get('ECP_WEIGHT')) + wl_weight = float(os.environ.get('WL_WEIGHT')) + ecp_weight_surrogate = float(os.environ.get('ECP_WEIGHT_SURROGATE')) + wl_weight_surrogate = float(os.environ.get('WL_WEIGHT_SURROGATE')) + except (ValueError, TypeError): + raise ValueError("Weights not properly set in environment variables.") + + # Calculate real ECP and WL values + ecp_value = None + wl_value = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'worst_slack' in metrics: + ecp_value = clock_period - float(metrics['worst_slack']) + if 'total_wirelength' in metrics: + wl_value = float(metrics['total_wirelength']) + + # Calculate surrogate ECP and WL values + ecp_surrogate = None + wl_surrogate = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'cts_ws' in metrics: + ecp_surrogate = clock_period - float(metrics['cts_ws']) + if 'cts_wirelength' in metrics: + wl_surrogate = float(metrics['cts_wirelength']) + + # Calculate weighted objective for real values + if ecp_value is not None and wl_value is not None: + result['value'] = ecp_weight * ecp_value + wl_weight * wl_value + elif ecp_value is not None: + result['value'] = ecp_weight * ecp_value + elif wl_value is not None: + result['value'] = wl_weight * wl_value + + # Calculate weighted surrogate objective + if ecp_surrogate is not None and wl_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + wl_weight_surrogate * wl_surrogate + elif ecp_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + elif wl_surrogate is not None: + result['surrogate'] = wl_weight_surrogate * wl_surrogate + + return result + + def _validate_domain_constraints(self, params: Dict[str, Any]) -> bool: + """Validate parameter combinations against domain constraints""" + # 1. Core utilization vs cell padding + core_util = float(params.get('core_util', 0)) + gp_pad = float(params.get('cell_pad_global', 0)) + dp_pad = float(params.get('cell_pad_detail', 0)) + + if core_util > 80 and (gp_pad > 2 or dp_pad > 2): + print(f"Domain constraint failed: core_util > 80 and gp_pad > 2 or dp_pad > 2") + return False + + # 2. TNS end percent vs place density + tns_end = float(params.get('tns', 0)) + place_density = float(params.get('lb_addon', 0)) + + if tns_end < 70 and place_density > 0.7: + print(f"Domain constraint failed: tns_end < 70 and place_density > 0.7") + return False + + # 3. CTS cluster constraints + cts_size = float(params.get('cts_size', 0)) + cts_diameter = float(params.get('cts_diameter', 0)) + + if cts_size > 30 and cts_diameter < 100: + print(f"Domain constraint failed: cts_size > 30 and cts_diameter < 100") + return False + + return True + + def _write_params_to_csv(self, params_list: List[Dict[str, Any]]) -> None: + """Write the new parameter sets to the expected CSV file for the next iteration""" + csv_file = f"designs/{self.platform}/{self.design}/{self.platform}_{self.design}.csv" + + # Ensure parameters are in correct order and properly typed + with open(csv_file, 'w', newline='\n') as f: # Explicitly use Unix line endings + writer = csv.writer(f) + # Write header in correct order + writer.writerow(self.parameter_names) + + # Write parameter rows + for params in params_list: + row = [] + for param_name in self.parameter_names: + value = params.get(param_name) + if value is None: + print(f"Warning: Missing value for parameter {param_name}") + continue + + # Apply type constraints + constraint = self.param_constraints[param_name] + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param_name} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + + except (ValueError, TypeError) as e: + print(f"Error converting {param_name} value '{value}' to {param_type}: {e}") + continue + + row.append(value) + + if len(row) == len(self.parameter_names): + writer.writerow(row) + else: + print(f"Warning: Skipping incomplete parameter set") + + print(f"New parameter sets written to {csv_file}") + + def _parse_llm_output(self, llm_response: str) -> List[Dict[str, Any]]: + """Parse the LLM's response and enforce parameter constraints""" + try: + param_sets = json.loads(llm_response) + except json.JSONDecodeError as e: + print(f"Error parsing LLM response: {e}") + return [] + + constrained_params = [] + for param_set in param_sets: + ordered_params = {} + valid = True + for param in self.parameter_names: + value = param_set.get(param) + if value is None: + print(f"Parameter '{param}' is missing in the LLM output.") + valid = False + break + + constraint = self.param_constraints.get(param) + if constraint: + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + elif param_type != 'float': + raise ValueError(f"Unsupported parameter type: {param_type}") + + ordered_params[param] = value + except (ValueError, TypeError) as e: + print(f"Parameter '{param}' has invalid value '{value}': {e}") + valid = False + break + else: + print(f"Unknown parameter '{param}' in parameter set.") + valid = False + break + + if valid and self._validate_domain_constraints(ordered_params): + constrained_params.append(ordered_params) + else: + print(f"Parameter set {ordered_params} failed validation and will be discarded.") + + return constrained_params + + def generate_initial_parameters(self, num_runs: int) -> None: + """Generate initial random parameters and write them to CSV using the same method as subsequent iterations""" + params_list = [] + for _ in range(num_runs): + params = {} + for param in self.parameter_names: + info = self.param_constraints[param] + param_type = info['type'] + min_value, max_value = info['range'] + if param_type == 'int': + value = random.randint(int(min_value), int(max_value)) + elif param_type == 'float': + value = random.uniform(min_value, max_value) + else: + continue # Skip unsupported types + params[param] = value + params_list.append(params) + + # Use the same method to write parameters to CSV + self._write_params_to_csv(params_list) + +def main(): + if len(sys.argv) != 5: + print("Usage: optimize.py ") + sys.exit(1) + + platform = sys.argv[1] + design = sys.argv[2] + objective = sys.argv[3] + num_runs = int(sys.argv[4]) + + workflow = OptimizationWorkflow(platform, design, objective) + workflow.run_iteration(num_runs) # Use the run_iteration method instead of individual steps + +# def main(): +# if len(sys.argv) != 6: +# print("Usage: optimize.py ") +# sys.exit(1) + +# platform = sys.argv[1] +# design = sys.argv[2] +# objective = sys.argv[3] +# num_runs = int(sys.argv[4]) +# num_iterations = int(sys.argv[5]) # 添加迭代次数参数 + +# workflow = OptimizationWorkflow(platform, design, objective) + +# for iteration in range(num_iterations): +# print(f"\n{'='*50}") +# print(f"Starting Optimization Iteration {iteration + 1}/{num_iterations}") +# print(f"{'='*50}") + +# workflow.run_iteration(num_runs) + +# # 等待新参数运行完成（需要实际部署运行） +# # wait_for_runs_completion() + +# print(f"Completed Iteration {iteration + 1}") + +if __name__ == "__main__": + main() diff --git a/flow-Agent/comparison/optimize_react_only.py b/flow-Agent/comparison/optimize_react_only.py new file mode 100644 index 0000000..b09a8d8 --- /dev/null +++ b/flow-Agent/comparison/optimize_react_only.py @@ -0,0 +1,2499 @@ +#!/usr/bin/env python3 +import json +import os +import sys +import re +import numpy as np +from typing import Dict, List, Any, Tuple, Optional +import anthropic +import csv +import random +from rag.util import answerWithRAG +from rag.index import load_embeddings_and_docs, build_and_save_embeddings +from sentence_transformers import SentenceTransformer +import torch +from pathlib import Path +from openai import OpenAI +from inspectfuncs import * +from modelfuncs import * +from agglomfuncs import * +import warnings +warnings.filterwarnings("ignore", category=RuntimeWarning) + +print("Python executable:", sys.executable) +print("sys.path:", sys.path[:3]) +print("Current working dir:", os.getcwd()) + +for pkg in ["anthropic", "sentence_transformers", "torch", "openai"]: + try: + __import__(pkg) + print(f" Imported {pkg}") + except ImportError as e: + print(f" Failed to import {pkg}: {e}") + +def process_log_file(log_path: str) -> Dict[str, Any]: + """Process a single log file to extract relevant metrics""" + run_data = { + 'file': os.path.basename(log_path), + 'success': False, + 'metrics': {}, + 'errors': [] + } + + with open(log_path, 'r') as f: + content = f.read() + print(f"File size: {len(content)} characters") + + # Extract timing information + timing_metrics = extract_timing_metrics(content) + run_data['metrics'].update(timing_metrics) + + # Extract wirelength information + wl_metrics = extract_wirelength_metrics(content) + run_data['metrics'].update(wl_metrics) + + # Extract any errors + errors = extract_errors(content) + run_data['errors'].extend(errors) + # === Inject a simulated error for testing RAG debugging === + # if "run3" in log_path: # 👈 你可以换成任意 run，比如 run1 或 run2 + # fake_error = "[ERROR] TEST_SIM: Simulated routing congestion failure" + # print(f"[DEBUG] Injected simulated error in {log_path}: {fake_error}") + # run_data['errors'].append(fake_error) + # run_data['success'] = False + + run_data['success'] = is_run_successful(content, errors) + + return run_data + +def extract_timing_metrics(log_content: str) -> Dict[str, float]: + """Extract timing-related metrics from log content""" + metrics = {} + + # Extract worst slack (final) + slack_match = re.search(r'(?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + if slack_match: + metrics['worst_slack'] = float(slack_match.group(1)) + + # Extract CTS worst slack + # cts_slack_match = re.search(r'(?:CTS|Clock Tree) (?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + cts_slack_match = re.search(r'Timing-driven:\s*(?:worst slack|WNS)\s+([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_slack_match: + metrics['cts_ws'] = float(cts_slack_match.group(1)) + + # Extract clock period + # period_match = re.search(r'[Cc]lock period:\s*([\d.]+)', log_content) + period_match = re.search(r'clock period to\s*([\d.]+)', log_content) + if period_match: + metrics['clock_period'] = float(period_match.group(1)) + + # Extract TNS + # tns_match = re.search(r'(?:Total negative slack|TNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + tns_match = re.search(r'"finish__timing__setup__tns"\s*:\s*([-\d.eE]+)', log_content) + if tns_match: + metrics['tns'] = float(tns_match.group(1)) + + return metrics + +def extract_wirelength_metrics(log_content: str) -> Dict[str, float]: + """Extract wirelength-related metrics from log content""" + metrics = {} + + # Extract total wirelength + wl_match = re.search(r'Total wirelength: ([\d.]+)', log_content) + if wl_match: + metrics['total_wirelength'] = float(wl_match.group(1)) + + # Extract estimated wirelength after CTS + # cts_wl_match = re.search(r'Estimated wirelength: ([\d.]+)', log_content) + cts_wl_match = re.search(r'"?cts__route__wirelength__estimated"?\s*[:=]\s*([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_wl_match: + metrics['cts_wirelength'] = float(cts_wl_match.group(1)) + + return metrics + +def extract_errors(log_content: str) -> List[str]: + """Extract error messages from log content""" + errors = [] + + # Look for common error patterns + error_patterns = [ + r'Error: .*', + r'ERROR: .*', + r'FATAL: .*', + r'Failed: .*' + ] + + for pattern in error_patterns: + matches = re.finditer(pattern, log_content, re.MULTILINE) + errors.extend(match.group(0) for match in matches) + + return errors + +def is_run_successful(log_content: str, errors: List[str], filename: str = "") -> bool: + """Determine if a run was successful based on log content and errors""" + if errors: + # If any real error lines were found, this file is a failure indicator + return False + + # Look for completion markers + completion_markers = [ + 'Flow complete', + 'Finished successfully' + 'Writing out GDS/OAS', + '6_report' + ] + + return any(marker in log_content for marker in completion_markers) + + +class ReActFramework: + """ReAct framework implementation""" + + def __init__(self, client, model_name="DeepSeek-V3"): + self.client = client + self.model_name = model_name + self.conversation_history = [] + + def add_to_history(self, role: str, content: str): + """add conversation history""" + self.conversation_history.append({"role": role, "content": content}) + + def clear_history(self): + """clear conversation history""" + self.conversation_history = [] + + def extract_thought_action(self, response: str) -> Tuple[str, str, str]: + """ + Extract Thought, Action, and Action Input from LLM responses + Format: Thought:... Action:... Action Input: ... + """ + thought = "" + action = "" + action_input = "" + + # Extract Thought + thought_match = re.search(r'Thought:\s*(.*?)(?=\nAction:|$)', response, re.DOTALL) + if thought_match: + thought = thought_match.group(1).strip() + + # Extract Action + action_match = re.search(r'Action:\s*(\w+)', response) + if action_match: + action = action_match.group(1).strip() + + # Extract Action Input + action_input_match = re.search(r'Action Input:\s*(.*?)(?=\nObservation:|$)', response, re.DOTALL) + if action_input_match: + action_input = action_input_match.group(1).strip() + # Try to parse JSON + try: + if action_input.startswith('{') or action_input.startswith('['): + action_input = json.loads(action_input) + except: + pass # Maintain the string format + + if "Final Answer:" in response and ("Action:" in response or "Observation:" in response): + + response = response.split("Final Answer:")[0] + print("Removed premature Final Answer from response") + + return thought, action, action_input + + def execute_action(self, action: str, action_input: Any, available_tools: Dict) -> str: + """Execute tool call and return observation results""" + if action in available_tools: + try: + result = available_tools[action](action_input) + return f"Action executed successfully. Result: {result}" + except Exception as e: + return f"Action execution failed: {str(e)}" + else: + return f"Unknown action: {action}. Available actions: {list(available_tools.keys())}" + + def run_react_cycle(self, + initial_prompt: str, + available_tools: Dict, + max_steps: int = 5, + temperature: float = 0.1) -> Dict[str, Any]: + """ + Run ReAct loop + + Args: + initial_prompt: Initial prompt + available_tools: Available tool function dictionary + max_steps: Maximum reasoning steps + temperature: temperature parameter + + Returns: + a dictionary containing the final result and the reasoning history + """ + self.clear_history() + self.add_to_history("user", initial_prompt) + + history = [] + final_answer = None + completed_steps = 0 + + for step in range(max_steps): + print(f"\n=== ReAct Step {step + 1}/{max_steps} ===") + completed_steps = step + 1 + + # Call LLM to obtain response + try: + response = self.client.chat.completions.create( + model=self.model_name, + messages=self.conversation_history, + temperature=temperature, + max_tokens=1024 + ) + + llm_response = response.choices[0].message.content + print(f"LLM Response: {llm_response}") + except Exception as e: + print(f"Error calling LLM: {e}") + llm_response = f"Error in LLM call: {e}" + + # Extract Thought, Action, Action Input + thought, action, action_input = self.extract_thought_action(llm_response) + + step_data = { + "step": step + 1, + "thought": thought, + "action": action, + "action_input": action_input, + "llm_response": llm_response + } + + # Check if it is the final answer + final_answer_detected = False + if "Final Answer:" in llm_response: + final_answer_match = re.search(r'Final Answer:\s*(.*?)$', llm_response, re.DOTALL) + if final_answer_match: + final_answer = final_answer_match.group(1).strip() + step_data["final_answer"] = final_answer + final_answer_detected = True + print(f"✓ Final answer detected at step {step + 1}") + + observation = "" + # Execute actions and obtain observation results + if action and not final_answer_detected: + observation = self.execute_action(action, action_input, available_tools) + step_data["observation"] = observation + + # Update conversation history + self.add_to_history("assistant", llm_response) + self.add_to_history("user", f"Observation: {observation}") + + print(f"Thought: {thought}") + print(f"Action: {action}") + print(f"Action Input: {action_input}") + print(f"Observation: {observation}") + else: + if not final_answer_detected: + # If there is no clear action, it may be during the reasoning process + self.add_to_history("assistant", llm_response) + step_data["observation"] = "No action taken - continuing reasoning" + observation = "No action taken" + else: + # If it is the final answer, no further action is required + step_data["observation"] = "Final answer provided - cycle complete" + observation = "Final answer provided" + + history.append(step_data) + + if final_answer_detected: + print(f" ReAct cycle completed at step {step + 1} with final answer") + break + + # Check if it should end early + if step >= max_steps - 1: + final_answer = f"Reached maximum steps ({max_steps}) without final answer" + print(f" Reached maximum steps without final answer") + break + + if final_answer is None: + final_answer = "No final answer produced" + + return { + "final_answer": final_answer, + "reasoning_history": history, + "success": final_answer is not None and "Reached maximum steps" not in final_answer and "No final answer" not in final_answer, + "completed_steps": completed_steps, + "max_steps": max_steps + } + + +class OptimizationWorkflow: + def __init__(self, platform: str, design: str, objective: str): + self.platform = platform + self.design = design + self.objective = objective.upper() # Convert to uppercase + + # Load configuration + self.config = self._load_config() + + # Find the design configuration + configurations = self.config.get('configurations', []) + for config in configurations: + if ( + config['platform'].lower() == self.platform.lower() + and config['design'].lower() == self.design.lower() + and config['goal'].upper() == self.objective + ): + self.design_config = config + break + else: + raise ValueError( + f"No configuration found for platform={self.platform}, design={self.design}, objective={self.objective}" + ) + + # Define initial clock periods for each design and platform + initial_clock_periods = { + ('asap7', 'aes'): 400, # in picoseconds + ('asap7', 'ibex'): 1260, # in picoseconds + ('asap7', 'jpeg'): 1100, # in picoseconds + ('sky130hd', 'aes'): 4.5, # in nanoseconds + ('sky130hd', 'ibex'): 10.0,# in nanoseconds + ('sky130hd', 'jpeg'): 8.0, # in nanoseconds + } + + # Get the initial clock period for the current platform and design + key = (self.platform.lower(), self.design.lower()) + if key in initial_clock_periods: + self.initial_clk_period = initial_clock_periods[key] + else: + raise ValueError(f"Initial clock period not defined for platform={self.platform}, design={self.design}") + + # Calculate clock period range + min_clk = self.initial_clk_period * 0.7 + max_clk = self.initial_clk_period * 1.3 + + # Define parameter names in the expected order + self.parameter_names = [ + 'core_util', + 'cell_pad_global', + 'cell_pad_detail', + 'synth_flatten', + 'pin_layer', + 'above_layer', + 'tns', + 'lb_addon', + 'cts_size', + 'cts_diameter', + 'enable_dpo', + 'clk_period' + ] + + # Set all parameter constraints including clock period range + self.param_constraints = { + 'core_util': {'type': 'int', 'range': [20, 99]}, + 'cell_pad_global': {'type': 'int', 'range': [0, 4]}, + 'cell_pad_detail': {'type': 'int', 'range': [0, 4]}, + 'synth_flatten': {'type': 'int', 'range': [0, 1]}, + 'pin_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'above_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'tns': {'type': 'int', 'range': [70, 100]}, + 'lb_addon': {'type': 'float', 'range': [0.00, 0.99]}, + 'cts_size': {'type': 'int', 'range': [10, 40]}, + 'cts_diameter': {'type': 'int', 'range': [80, 120]}, + 'enable_dpo': {'type': 'int', 'range': [0, 1]}, + 'clk_period': {'type': 'float', 'range': [min_clk, max_clk]} + } + + # Load initial parameters and SDC context + self.initial_params = self._load_initial_params() + self.sdc_context = self._load_sdc_context() + + emb_np, docs, docsDict = load_embeddings_and_docs() + self.rag_embeddings = torch.tensor(emb_np).cpu() + self.rag_docs = docs + self.rag_docsDict = docsDict + print("[INFO] Loading embedding model...") + model_path = Path(__file__).parent / "models" / "mxbai-embed-large-v1" + model_path = model_path.resolve() + # self.rag_model = SentenceTransformer(str(model_path)) + self.rag_model = SentenceTransformer(str(model_path), device='cpu') + + self.react_framework = ReActFramework( + client=OpenAI( + base_url="https://ai.gitee.com/v1", + # api_key=" ", + api_key=" ", + ), + model_name="DeepSeek-V3" + ) + + def _create_react_tools(self, stage: str, data: Dict[str, Any]) -> Dict: + """Create available utility functions for different stages""" + + base_tools = { + "analyze_data_distribution": lambda x: self._call_existing_distribution_analysis(data), + "analyze_data_structure": lambda x: self._call_existing_structure_analysis(data), + "evaluate_parameter_ranges": lambda x: self._evaluate_parameter_ranges(data), + "check_constraints": lambda x: self._check_constraints_compliance(data), + "suggest_improvements": lambda x: self._suggest_improvements(stage, data), + } + + if stage == 'inspect': + inspection_tools = { + "configure_inspection": lambda config: self._configure_inspection_with_existing(config, data), + "analyze_correlations": lambda params: self._analyze_correlations_with_existing(params, data), + "cluster_analysis": lambda config: self._cluster_analysis_with_existing(config, data), + "manifold_analysis": lambda config: self._manifold_analysis_with_existing(config, data), + "local_structure_analysis": lambda config: self._local_structure_analysis_with_existing(config, data), + } + base_tools.update(inspection_tools) + + elif stage == 'model': + modeling_tools = { + "configure_model": lambda config: self._configure_model_with_existing(config, data), + "evaluate_surrogate": lambda params: self._evaluate_surrogate_with_existing(params, data), + "select_acquisition": lambda method: self._select_acquisition_with_existing(method, data), + "create_surrogate_model": lambda config: self._create_surrogate_model_with_existing(config, data), + "evaluate_timing_model": lambda x: self._evaluate_timing_model_with_existing(data), + "evaluate_wirelength_model": lambda x: self._evaluate_wirelength_model_with_existing(data), + "get_model_recommendations": lambda x: self._get_model_recommendations_from_existing(data), + } + base_tools.update(modeling_tools) + + elif stage == 'agglomerate': + selection_tools = { + "configure_selection": lambda config: self._configure_selection_with_existing(config, data), + "generate_parameters": lambda count: self._generate_parameters_with_existing(count, data), + "validate_parameters": lambda params: self._validate_parameters_tool(params), + "latin_hypercube_sampling": lambda config: self._latin_hypercube_sampling_with_existing(config, data), + "create_quality_scores": lambda config: self._create_quality_scores_with_existing(config, data), + "select_points": lambda config: self._select_points_with_existing(config, data), + "compare_selection_methods": lambda config: self._compare_selection_methods_with_existing(config, data), + "kmeans_selection": lambda config: self._kmeans_selection_with_existing(config, data), + "hybrid_selection": lambda config: self._hybrid_selection_with_existing(config, data), + "entropy_selection": lambda config: self._entropy_selection_with_existing(config, data), + "graph_selection": lambda config: self._graph_selection_with_existing(config, data), + } + base_tools.update(selection_tools) + + return base_tools + + + def _call_existing_distribution_analysis(self, data: Dict) -> str: + """Call existing data distribution analysis functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + result = inspect_data_distribution(X, Y) + return self._format_analysis_result("Data Distribution Analysis", result) + else: + return "Insufficient data for distribution analysis" + + except Exception as e: + return f"Error in distribution analysis: {str(e)}" + + def _call_existing_structure_analysis(self, data: Dict) -> str: + """Call existing data structure analysis functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Use default configuration or retrieve configuration from data + config = { + "n_clusters": 5, + "correlation_threshold": 0.5, + "n_neighbors": 20, + "perplexity": 30 + } + + result = inspect_data_structure(X, Y, config) + return self._format_analysis_result("Data Structure Analysis", result) + else: + return "Insufficient data for structure analysis" + + except Exception as e: + return f"Error in structure analysis: {str(e)}" + + def _evaluate_parameter_ranges(self, data: Dict) -> str: + """Evaluation Parameter Range Tool - Implementation""" + constraints_info = "Parameter Constraints Evaluation:\n" + + # Analyze the current usage of parameters + param_usage = {} + for run in data.get('log_data', {}).get('runs', []): + if run.get('parameters'): + for param, value in run['parameters'].items(): + if param not in param_usage: + param_usage[param] = [] + param_usage[param].append(float(value)) + + for param, info in self.param_constraints.items(): + min_val, max_val = info['range'] + param_type = info['type'] + + constraints_info += f"\n- {param} ({param_type}): range [{min_val}, {max_val}]" + + if param in param_usage: + values = param_usage[param] + used_min = min(values) + used_max = max(values) + constraints_info += f"\n Currently used: [{used_min:.2f}, {used_max:.2f}]" + + # Check if the parameter space has been fully explored + range_used = (used_max - used_min) / (max_val - min_val) + if range_used < 0.5: + constraints_info += f" (Only {range_used*100:.1f}% of range explored)" + + return constraints_info + + def _check_constraints_compliance(self, data: Dict) -> str: + """Check Constraint Compliance Tool - Implementation""" + violations = [] + constraint_checks = [] + + for run in data.get('log_data', {}).get('runs', []): + if run.get('success') and run.get('parameters'): + params = run['parameters'] + + # Check the basic scope constraints + for param, value in params.items(): + if param in self.param_constraints: + constraint = self.param_constraints[param] + min_val, max_val = constraint['range'] + if value < min_val or value > max_val: + violations.append(f"{param}={value} not in [{min_val}, {max_val}]") + + # Check domain constraints + if not self._validate_domain_constraints(params): + violations.append(f"Domain constraints violated for run with params: {params}") + + if violations: + constraint_checks.append(f"Constraint violations found in {len(violations)} cases:") + constraint_checks.extend(violations[:5]) # Only display the first 5 + else: + constraint_checks.append("All parameters comply with constraints") + + # Check the effectiveness of parameter combinations + successful_count = sum(1 for run in data.get('log_data', {}).get('runs', []) + if run.get('success') and run.get('parameters')) + total_with_params = sum(1 for run in data.get('log_data', {}).get('runs', []) + if run.get('parameters')) + + if total_with_params > 0: + success_rate = successful_count / total_with_params * 100 + constraint_checks.append(f"\nParameter success rate: {success_rate:.1f}%") + + return "\n".join(constraint_checks) + + def _suggest_improvements(self, stage: str, data: Dict) -> str: + """Provide improvement suggestions based on stages - implementation""" + suggestions = [] + + if stage == 'inspect': + successful_runs = data.get('log_data', {}).get('summary', {}).get('successful_runs', 0) + total_runs = data.get('log_data', {}).get('summary', {}).get('total_runs', 0) + + suggestions.append(f"Inspection Suggestions for {successful_runs}/{total_runs} successful runs:") + + if successful_runs < total_runs * 0.3: + suggestions.append("- Focus on identifying why runs are failing") + suggestions.append("- Check for common parameter ranges in failed runs") + else: + suggestions.append("- Analyze correlations between parameters and objectives") + suggestions.append("- Identify optimal parameter ranges from successful runs") + + elif stage == 'model': + suggestions.append("Modeling Suggestions:") + suggestions.append("- Use surrogate models for early prediction of results") + suggestions.append("- Balance exploration (trying new regions) and exploitation (refining good regions)") + + # Suggest modeling methods based on data volume + successful_runs = data.get('log_data', {}).get('summary', {}).get('successful_runs', 0) + if successful_runs < 10: + suggestions.append("- With limited data, use simpler models and focus on exploration") + else: + suggestions.append("- With sufficient data, use more complex models and balance exploration/exploitation") + + elif stage == 'agglomerate': + suggestions.append("Parameter Generation Suggestions:") + suggestions.append("- Generate diverse parameter sets to explore different regions") + suggestions.append("- Focus on promising parameter ranges identified in previous stages") + suggestions.append("- Ensure all generated parameters satisfy domain constraints") + + # Suggest strategies based on goals + if self.objective == 'ECP': + suggestions.append("- For ECP, prioritize timing-critical parameters like clk_period and cell padding") + elif self.objective == 'DWL': + suggestions.append("- For DWL, focus on placement and routing parameters") + + return "\n".join(suggestions) + + def _extract_XY_from_data(self, data: Dict) -> Tuple[Optional[np.ndarray], Optional[np.ndarray]]: + """Extracting X and Y arrays from data - Reusing logic in analyze_stetrics""" + feature_vectors = [] + objective_values = [] + + for run in data.get('log_data', {}).get('runs', []): + if run.get('success') and 'metrics' in run: + obj_values = self._calculate_objective(run) + + if obj_values['value'] is not None or obj_values['surrogate'] is not None: + # Extract parameter values as features + params = [] + for param in self.parameter_names: + params.append(float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0)))) + feature_vectors.append(params) + + # Use real values, if not available, use proxy values + objective_values.append(obj_values['value'] if obj_values['value'] is not None else obj_values['surrogate']) + + if feature_vectors and objective_values: + return np.array(feature_vectors), np.array(objective_values) + else: + return None, None + + def _format_analysis_result(self, title: str, result: Dict) -> str: + """Format the analysis result as a readable string""" + formatted = f"=== {title} ===\n" + + for key, value in result.items(): + if key == "model_recommendations": + formatted += "\n--- Model Recommendations ---\n" + for rec_key, rec_value in value.items(): + formatted += f"{rec_key}: {rec_value}\n" + elif isinstance(value, (int, float)): + formatted += f"{key}: {value:.4f}\n" + elif isinstance(value, list) and len(value) > 0 and isinstance(value[0], (int, float)): + # Format numerical list + formatted += f"{key}: [{', '.join(f'{v:.4f}' for v in value[:5])}{'...' if len(value) > 5 else ''}]\n" + else: + formatted += f"{key}: {value}\n" + + return formatted + + def _configure_inspection_with_existing(self, config: Dict, data: Dict) -> str: + """Use existing function configuration to check parameters""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Using configuration to run structural analysis + result = inspect_data_structure(X, Y, config) + + response = f"Inspection configured with: {config}\n" + response += "Key findings:\n" + + # Extract key findings + if "linearity_score" in result: + response += f"- Linearity: {result['linearity_score']:.3f}\n" + if "is_nonlinear" in result: + response += f"- Nonlinear: {result['is_nonlinear']}\n" + if "needs_local_models" in result: + response += f"- Needs local models: {result['needs_local_models']}\n" + if "cluster_sizes" in result: + response += f"- Cluster sizes: {result['cluster_sizes']}\n" + + return response + else: + return "No data available for inspection configuration" + + except Exception as e: + return f"Error in inspection configuration: {str(e)}" + + def _analyze_correlations_with_existing(self, params: Dict, data: Dict) -> str: + """Analyze correlation using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Perform structural analysis to obtain relevant information + config = {"correlation_threshold": params.get('threshold', 0.5)} + result = inspect_data_structure(X, Y, config) + + response = "Feature Correlations Analysis:\n" + + if "feature_importance" in result: + response += "Feature importance (correlation with objective):\n" + for i, importance in enumerate(result["feature_importance"]): + response += f"- {self.parameter_names[i]}: {importance:.3f}\n" + + if "has_correlated_features" in result: + response += f"Has highly correlated features: {result['has_correlated_features']}\n" + if "high_correlation_pairs" in result: + response += f"High correlation pairs: {result['high_correlation_pairs']}\n" + + return response + else: + return "No data available for correlation analysis" + + except Exception as e: + return f"Error in correlation analysis: {str(e)}" + + def _cluster_analysis_with_existing(self, config: Dict, data: Dict) -> str: + """Cluster analysis using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Perform structural analysis to obtain clustering information + result = inspect_data_structure(X, Y, config) + + response = "Cluster Analysis:\n" + + if "cluster_sizes" in result: + response += f"Cluster sizes: {result['cluster_sizes']}\n" + if "cluster_balance" in result: + response += f"Cluster balance: {result['cluster_balance']:.3f}\n" + if "cluster_y_means" in result: + response += "Cluster objective means:\n" + for i, mean in enumerate(result["cluster_y_means"]): + response += f"- Cluster {i}: {mean:.4f}\n" + if "needs_local_models" in result: + response += f"Recommend local models: {result['needs_local_models']}\n" + + return response + else: + return "No data available for cluster analysis" + + except Exception as e: + return f"Error in cluster analysis: {str(e)}" + + def _manifold_analysis_with_existing(self, config: Dict, data: Dict) -> str: + """Perform manifold analysis using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None: + result = analyze_manifold_structure(X, config) + return self._format_analysis_result("Manifold Structure Analysis", result) + else: + return "No data available for manifold analysis" + + except Exception as e: + return f"Error in manifold analysis: {str(e)}" + + def _local_structure_analysis_with_existing(self, config: Dict, data: Dict) -> str: + """Using existing functions for local structure analysis""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None: + result = analyze_local_structure(X, config) + return self._format_analysis_result("Local Structure Analysis", result) + else: + return "No data available for local structure analysis" + + except Exception as e: + return f"Error in local structure analysis: {str(e)}" + + def _get_model_recommendations_from_existing(self, data: Dict) -> str: + """Obtain model recommendations from existing analysis""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + result = inspect_data_structure(X, Y) + + if "model_recommendations" in result: + recommendations = result["model_recommendations"] + response = "Model Recommendations from Data Analysis:\n" + + for key, value in recommendations.items(): + if key == "feature_weights" and isinstance(value, list): + response += f"{key}: [" + response += ", ".join(f"{w:.3f}" for w in value[:5]) + if len(value) > 5: + response += ", ..." + response += "]\n" + else: + response += f"{key}: {value}\n" + + return response + else: + return "No model recommendations available" + else: + return "No data available for model recommendations" + + except Exception as e: + return f"Error getting model recommendations: {str(e)}" + + + def _configure_model_with_existing(self, config: Dict, data: Dict) -> str: + """Configure the model using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Create a model using configuration + kernel_type = config.get('kernel_type', 'matern') + preprocessing = config.get('preprocessing', 'standard') + acquisition = config.get('acquisition', 'ei') + + # Create Preprocessor + preprocessor = create_preprocessor(preprocessing) + + # Create acquisition function + acq_function = create_acquisition_function(acquisition) + + response = f"Model configured successfully:\n" + response += f"- Kernel type: {kernel_type}\n" + response += f"- Preprocessing: {preprocessing}\n" + response += f"- Acquisition function: {acquisition}\n" + response += f"- Data shape: {X.shape}\n" + + # If the amount of data is sufficient, a model can be created for testing + if len(X) >= 2: + model = create_model(X, Y, kernel_type=kernel_type) + response += f"- Model created successfully with {len(X)} samples\n" + else: + response += f"- Insufficient data for model creation (need at least 2 samples, have {len(X)})\n" + + return response + else: + return "No data available for model configuration" + + except Exception as e: + return f"Error in model configuration: {str(e)}" + + def _evaluate_surrogate_with_existing(self, params: Dict, data: Dict) -> str: + """Evaluate the proxy model using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Extract proxy values (if any) + surrogate_values = None + if 'surrogates' in data.get('metrics', {}): + surrogate_values = np.array(data['metrics']['surrogates']) + + # Use existing functions to process proxy data + if surrogate_values is not None: + X_processed, y_combined, uncertainty = handle_surrogate_data(X, Y, surrogate_values) + + response = "Surrogate Model Evaluation:\n" + response += f"- Original data points: {len(Y)}\n" + response += f"- Valid target values: {np.sum(~np.isnan(Y))}\n" + response += f"- Surrogate values used: {np.sum(np.isnan(Y))}\n" + response += f"- Combined data points: {len(y_combined)}\n" + + if len(uncertainty) > 0: + response += f"- Average surrogate uncertainty: {np.mean(uncertainty):.4f}\n" + + return response + else: + return "No surrogate data available for evaluation" + else: + return "No data available for surrogate evaluation" + + except Exception as e: + return f"Error in surrogate evaluation: {str(e)}" + + def _select_acquisition_with_existing(self, method: str, data: Dict) -> str: + """Use existing functions to select collection functions""" + try: + # Create a collection function using an existing function + acq_function = create_acquisition_function(method) + + response = f"Acquisition function selected: {method.upper()}\n" + + # Provide explanations for different collection functions + explanations = { + 'ei': "Expected Improvement - balances improvement probability and magnitude", + 'ucb': "Upper Confidence Bound - favors exploration of uncertain regions", + 'pi': "Probability of Improvement - focuses on areas likely to improve", + 'augmented_ei': "Augmented EI - combines EI with exploration bonus" + } + + response += f"Explanation: {explanations.get(method, 'No explanation available')}\n" + + # Provide recommendations based on data characteristics + X, Y = self._extract_XY_from_data(data) + if X is not None and Y is not None: + if len(Y) < 10: + response += "Recommendation: With limited data, consider using UCB for better exploration\n" + else: + response += "Recommendation: With sufficient data, EI or Augmented EI are good choices\n" + + return response + + except Exception as e: + return f"Error in acquisition function selection: {str(e)}" + + def _create_surrogate_model_with_existing(self, config: Dict, data: Dict) -> str: + """Create a proxy model using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + kernel_type = config.get('kernel_type', 'matern') + noise_level = config.get('noise_level', 1e-6) + + # Create a model using existing functions + model = create_model(X, Y, noise_level=noise_level, kernel_type=kernel_type) + + response = f"Surrogate Model Created:\n" + response += f"- Kernel: {kernel_type}\n" + response += f"- Data points: {len(X)}\n" + response += f"- Features: {X.shape[1]}\n" + response += f"- Kernel parameters: {model.kernel_}\n" + + # Test model prediction + if len(X) > 0: + predictions, stds = predict_with_model(model, X[:1]) # Test a point + response += f"- Test prediction successful\n" + response += f"- Prediction range: [{predictions[0]:.4f} ± {stds[0]:.4f}]\n" + + return response + else: + return "No data available for model creation" + + except Exception as e: + return f"Error in surrogate model creation: {str(e)}" + + def _evaluate_timing_model_with_existing(self, data: Dict) -> str: + """Evaluate timing models using existing functions""" + try: + # Build context + context = { + 'log_data': data.get('log_data', {}), + 'metrics': data.get('metrics', {}), + 'model_recommendations': data.get('model_recommendations', {}) + } + + # Evaluate timing models using existing functions + results = evaluate_timing_model(context) + + response = "Timing Model Evaluation:\n" + + if 'performance' in results: + for key, value in results['performance'].items(): + response += f"- {key}: {value:.4f}\n" + + if 'suggestions' in results: + response += "\nSuggestions:\n" + for suggestion in results['suggestions']: + response += f"- {suggestion}\n" + + if 'recommendations' in results: + response += "\nRecommendations:\n" + for key, value in results['recommendations'].items(): + response += f"- {key}: {value}\n" + + return response + + except Exception as e: + return f"Error in timing model evaluation: {str(e)}" + + def _evaluate_wirelength_model_with_existing(self, data: Dict) -> str: + """Evaluate the wire length model using existing functions""" + try: + # Build context + context = { + 'log_data': data.get('log_data', {}), + 'metrics': data.get('metrics', {}), + 'model_recommendations': data.get('model_recommendations', {}) + } + + # Evaluate the wire length model using existing functions + results = evaluate_wirelength_model(context) + + response = "Wirelength Model Evaluation:\n" + + if 'performance' in results: + for key, value in results['performance'].items(): + response += f"- {key}: {value:.4f}\n" + + if 'suggestions' in results: + response += "\nSuggestions:\n" + for suggestion in results['suggestions']: + response += f"- {suggestion}\n" + + if 'recommendations' in results: + response += "\nRecommendations:\n" + for key, value in results['recommendations'].items(): + response += f"- {key}: {value}\n" + + return response + + except Exception as e: + return f"Error in wirelength model evaluation: {str(e)}" + + def _generate_parameters_with_existing(self, count: int, data: Dict) -> str: + """Generate parameters using existing functions""" + try: + if count <= 0 or count > 50: + return "Error: count must be between 1 and 50" + + # Obtain parameter dimensions + n_dims = len(self.parameter_names) + + # Use existing Latin hypercube sampling + samples = latin_hypercube(count, n_dims) + + response = f"Parameter Generation using Latin Hypercube:\n" + response += f"- Samples generated: {count}\n" + response += f"- Parameter dimensions: {n_dims}\n" + response += f"- Sampling method: Latin Hypercube\n" + + # Display parameter range information + response += "\nParameter Ranges:\n" + for i, param in enumerate(self.parameter_names): + constraint = self.param_constraints[param] + min_val, max_val = constraint['range'] + response += f"- {param}: [{min_val}, {max_val}] ({constraint['type']})\n" + + return response + + except Exception as e: + return f"Error in parameter generation: {str(e)}" + + def _latin_hypercube_sampling_with_existing(self, config: Dict, data: Dict) -> str: + """Using existing functions for Latin hypercube sampling""" + try: + n_points = config.get('n_points', 10) + n_dims = len(self.parameter_names) + + # Use the existing Latin hypercube sampling function + samples = latin_hypercube(n_points, n_dims) + + response = f"Latin Hypercube Sampling:\n" + response += f"- Points: {n_points}\n" + response += f"- Dimensions: {n_dims}\n" + response += f"- Sample shape: {samples.shape}\n" + + # Display sampling statistics + response += f"- Sample range: [{samples.min():.3f}, {samples.max():.3f}]\n" + response += f"- Sample mean: {samples.mean():.3f}\n" + response += f"- Sample std: {samples.std():.3f}\n" + + return response + + except Exception as e: + return f"Error in Latin hypercube sampling: {str(e)}" + + def _configure_selection_with_existing(self, config: Dict, data: Dict) -> str: + """Configure selection strategy using existing functions""" + try: + method = config.get('method', 'hybrid') + quality_weight = config.get('quality_weight', 0.7) + uncertainty_bonus = config.get('uncertainty_bonus', 0.2) + n_points = config.get('n_points', 10) + + response = f"Selection Strategy Configured:\n" + response += f"- Method: {method}\n" + response += f"- Quality weight: {quality_weight}\n" + response += f"- Uncertainty bonus: {uncertainty_bonus}\n" + response += f"- Points to select: {n_points}\n" + + # Provide explanations for different methods + method_descriptions = { + "kmeans": "K-means clustering - selects best point from each cluster", + "hybrid": "Hybrid approach - balances quality and diversity", + "entropy": "Entropy-based - maximizes information diversity", + "graph": "Graph-based - uses network centrality measures" + } + + response += f"Method description: {method_descriptions.get(method, 'No description')}\n" + + return response + + except Exception as e: + return f"Error in selection configuration: {str(e)}" + + + def _create_quality_scores_with_existing(self, config: Dict, data: Dict) -> str: + """Create a quality score using an existing function""" + try: + # Extract necessary information from data + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Simulation model predictions and uncertainties (in practical use, these should come from real models) + model_predictions = Y # Using real values as a proxy for prediction + model_uncertainties = np.ones_like(Y) * 0.1 # Simulate uncertainty + + # Create a quality score using an existing function + quality_scores = create_quality_scores(X, Y, model_predictions, model_uncertainties) + + response = "Quality Scores Created:\n" + response += f"- Data points: {len(X)}\n" + response += f"- Quality score range: [{quality_scores.min():.4f}, {quality_scores.max():.4f}]\n" + response += f"- Quality score mean: {quality_scores.mean():.4f}\n" + response += f"- Quality score std: {quality_scores.std():.4f}\n" + + response += f"- First 5 quality scores: {quality_scores[:5].tolist()}\n" + + if 'selection_data' not in data: + data['selection_data'] = {} + data['selection_data']['quality_scores'] = quality_scores + data['selection_data']['X'] = X + data['selection_data']['Y'] = Y + + return response + else: + return "No data available for quality score creation" + + except Exception as e: + return f"Error in quality score creation: {str(e)}" + + def _select_points_with_existing(self, config: Dict, data: Dict) -> str: + """_select_points_with_existing""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + method = config.get('method', 'hybrid') + n_points = config.get('n_points', 10) + quality_weight = config.get('quality_weight', 0.7) + + selection_config = { + "quality_weight": quality_weight, + "uncertainty_bonus": config.get('uncertainty_bonus', 0.2) + } + + selected_indices = select_points( + X, quality_scores, + method=method, + n_points=n_points, + config=selection_config + ) + + response = f"Points Selected using {method.upper()} method:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Selected quality scores: {selected_qualities.tolist()}\n" + response += f"- Average quality of selected: {selected_qualities.mean():.4f}\n" + + # store selection data + data['selection_data']['selected_indices'] = selected_indices + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in point selection: {str(e)}" + + def _compare_selection_methods_with_existing(self, config: Dict, data: Dict) -> str: + """compare selection methods with existing(""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 5) + methods = ['kmeans', 'hybrid', 'entropy', 'graph'] + + response = "Selection Method Comparison:\n" + response += f"- Comparing {len(methods)} methods\n" + response += f"- Points to select: {n_points}\n\n" + + for method in methods: + try: + selected_indices = select_points( + X, quality_scores, + method=method, + n_points=n_points + ) + + selected_qualities = quality_scores[selected_indices] + + response += f"**{method.upper()}**:\n" + response += f" - Selected indices: {selected_indices.tolist()}\n" + response += f" - Avg quality: {selected_qualities.mean():.4f}\n" + response += f" - Quality range: [{selected_qualities.min():.4f}, {selected_qualities.max():.4f}]\n" + + except Exception as e: + response += f"**{method.upper()}**: Error - {str(e)}\n" + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in method comparison: {str(e)}" + + def _kmeans_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using K-means selection method""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + + # using K-means selecting function + selected_indices = kmeans_select(X, quality_scores, n_points) + + response = "K-means Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + response += f"- Quality diversity: {selected_qualities.std():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'kmeans' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in K-means selection: {str(e)}" + + def _hybrid_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using existing hybrid selection method""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + quality_weight = config.get('quality_weight', 0.7) + + distance_matrix = cdist(X, X) + + # using hybrid_select function + selected_indices = hybrid_select( + X, quality_scores, distance_matrix, + n_points, quality_weight + ) + + response = "Hybrid Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Quality weight: {quality_weight}\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + + selected_points = X[selected_indices] + min_distances = np.min(cdist(selected_points, selected_points) + np.eye(len(selected_points)) * 1e6, axis=1) + response += f"- Minimum inter-point distance: {min_distances.mean():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'hybrid' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in hybrid selection: {str(e)}" + + def _entropy_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using existing entropy selecting methods""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + + # using entropy selecting function + selected_indices = entropy_select(X, quality_scores, n_points) + + response = "Entropy-based Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'entropy' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in entropy selection: {str(e)}" + + def _graph_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using existing graph selection method""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + + # using graph selecting function + selected_indices = graph_select(X, quality_scores, n_points) + + response = "Graph-based Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'graph' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in graph selection: {str(e)}" + + + def _validate_parameters_tool(self, params: Dict) -> str: + validation_results = [] + + for param_name, value in params.items(): + if param_name in self.param_constraints: + constraint = self.param_constraints[param_name] + min_val, max_val = constraint['range'] + param_type = constraint['type'] + + if value < min_val or value > max_val: + validation_results.append(f" {param_name}={value} outside range [{min_val}, {max_val}]") + else: + validation_results.append(f" {param_name}={value} within valid range") + + if self._validate_domain_constraints(params): + validation_results.append("Domain constraints satisfied") + else: + validation_results.append("Domain constraints violated") + + return "Parameter Validation:\n" + "\n".join(validation_results) + + + def _load_config(self) -> Dict[str, Any]: + """Load the configuration from 'opt_config.json'.""" + with open('opt_config.json', 'r') as f: + config = json.load(f) + return config + + def _load_initial_params(self) -> Dict[str, Any]: + """Load initial parameters from the design's config.mk file""" + config_path = f"designs/{self.platform}/{self.design}/config.mk" + params = {} + with open(config_path, 'r') as f: + for line in f: + if line.startswith('export'): + parts = line.strip().split('=', 1) + if len(parts) == 2: + key = parts[0].replace('export', '').strip() + value = parts[1].strip() + params[key] = value + return params + + def _load_sdc_context(self) -> Dict[str, Any]: + """Load SDC context including special case for JPEG""" + sdc_context = {} + + # Determine SDC filename based on platform/design + if self.platform.lower() == 'asap7' and self.design.lower() == 'jpeg': + sdc_file = 'jpeg_encoder15_7nm.sdc' + else: + sdc_file = 'constraint.sdc' + + sdc_path = f"designs/{self.platform}/{self.design}/{sdc_file}" + + # Read SDC file + try: + with open(sdc_path, 'r') as f: + sdc_content = f.read() + + # Extract clock period + clock_period_match = re.search(r'set clk_period\s+([\d.]+)', sdc_content) + if clock_period_match: + sdc_context['clock_period'] = float(clock_period_match.group(1)) + + # Store full content for context + sdc_context['content'] = sdc_content + sdc_context['filename'] = sdc_file + + except Exception as e: + print(f"Warning: Could not load SDC file {sdc_path}: {str(e)}") + sdc_context['error'] = str(e) + + return sdc_context + + + def _generate_llm_prompt(self, stage: str, data: Dict[str, Any]) -> str: + + constraints_text = "Parameter Constraints:\n" + for param, info in self.param_constraints.items(): + param_type = info['type'] + param_range = info['range'] + constraints_text += f"- {param} ({param_type}, range: {param_range})\n" + + tool_instructions = { + 'inspect': ( + f"**Stage: Inspect**\n" + "In this stage, we analyze the data from previous optimization runs to identify patterns, trends, and insights.\n\n" + f"Data to analyze:\n{json.dumps(data, indent=2, default=str)}\n\n" + "Please analyze the data and provide insights on:\n" + "1. Key patterns in successful vs unsuccessful runs.\n" + "2. Parameter ranges that appear promising.\n" + "3. Any timing or wirelength trends.\n" + "4. Recommendations for subsequent runs.\n" + "5. We hope to further reduce the total wirelength.\n" + ), + + 'model': ( + f"**Stage: Model**\n" + "In this stage, we decide how to model the optimization problem based on the data analysis.\n\n" + f"Data for modeling:\n{json.dumps(data, indent=2, default=str)}\n\n" + "Please suggest:\n" + "1. Appropriate modeling techniques.\n" + "2. Key parameters to focus on.\n" + "3. Surrogate model recommendations.\n" + "4. Acquisition function choices.\n" + ), + + 'agglomerate': ( + f"**Stage: Agglomerate**\n" + "In this stage, we generate new parameter combinations to explore in the next optimization runs.\n\n" + "Please provide a list of new parameter sets to try, ensuring they respect the domain constraints below.\n\n" + f"{constraints_text}\n" + "Each parameter set should be a dictionary with parameter names and their suggested values.\n" + "**Important:** Make sure all parameter sets satisfy the domain constraints before suggesting them.\n" + ) + } + + stage_contexts = { + 'inspect': ( + f"metrics analyze: Total runs={data.get('log_data', {}).get('summary', {}).get('total_runs', 0)}, " + f"successful runs ={data.get('log_data', {}).get('summary', {}).get('successful_runs', 0)}" + ), + 'model': "Configure modeling methods based on inspection results", + 'agglomerate': "Configure parameter selection strategy based on modeling results" + } + + prompt = f"""**stages:{stage.upper()}** + + {stage_contexts.get(stage, '')} + + {tool_instructions.get(stage, '')} + + **Important: Use only tool calls and do not generate text replies!** + """ + + # ========= Splicing RAG ========= + # rag_context = "" + # if self.rag_model is not None and self.rag_embeddings is not None: + # try: + # print("[DEBUG] RAG: Starting retrieval...") + + # # Step 1: Extract error information + # error_summary = "" + # if "log_data" in data: + # all_errors = [] + # for run in data["log_data"].get("runs", []): + # if run.get("errors"): + # all_errors.extend(run["errors"]) + # if all_errors: + # # Retrieve the most recent or frequent errors + # top_errors = all_errors[-3:] # Last 3 posts + # error_summary = "\n".join(top_errors) + # print(f"[DEBUG] Detected {len(all_errors)} error messages. Sample:\n{error_summary}") + + # # Step 2: Construct RAG query + # if error_summary: + # query = ( + # f"Stage: {stage}. Objective: {self.objective}. " + # f"The recent optimization runs failed with errors:\n{error_summary}\n\n" + # "Retrieve relevant OpenROAD documentation, known failure modes, and " + # "potential parameter tuning suggestions that may fix these issues." + # ) + # else: + # query = ( + # f"Stage: {stage}. Objective: {self.objective}. " + # f"Focus on analyzing {stage}-related optimization results. " + # f"Important metrics include wirelength, timing, area, and success rate. " + # f"Find relevant OpenROAD documentation, parameter tuning guides, and failure pattern examples." + # ) + + # # Step 3: Execute search + # rag_context = answerWithRAG( + # query, + # self.rag_embeddings, + # self.rag_model, + # self.rag_docs, + # self.rag_docsDict, + # ) + + # if isinstance(rag_context, dict): # If returning dict + # print(f"[DEBUG] RAG Retrieved {len(rag_context.get('docs', []))} related entries.") + # for doc in rag_context.get("docs", [])[:3]: + # print(f" ↳ {doc['title']} (score={doc['score']:.3f}) from {doc['source']}") + # retrieved_text = rag_context.get("content", "") + # else: + # retrieved_text = rag_context + + # # Step 4: 加入 prompt + # if retrieved_text.strip(): + # prompt += ( + # "\n\n=== Retrieved OpenROAD Documentation (via RAG) ===\n" + # f"{retrieved_text}\n" + # "==============================================" + # ) + # print("[DEBUG] RAG: Context successfully added to prompt.") + # else: + # print("[DEBUG] RAG: Empty context retrieved.") + # except Exception as e: + # prompt += f"\n\n[WARN] RAG retrieval failed: {e}" + + if "log_data" in data: + all_errors = [] + for run in data["log_data"].get("runs", []): + if run.get("errors"): + all_errors.extend(run["errors"]) + + if all_errors: + error_summary = "\n".join(all_errors[-5:]) # The last 5 errors + prompt += f""" + + ### Detected Run Errors + {error_summary} + + The model must now act as an **EDA Debugging Assistant**. + Using the retrieved documentation and knowledge, analyze the errors above and: + 1. Identify the root causes of each error (e.g., tool misconfiguration, parameter overflow, timing issues, etc.) + 2. Suggest **specific parameter changes or flow adjustments** to prevent these errors. + 3. Indicate whether the error is likely due to constraints, routing congestion, or timing margin. + 4. Provide a short explanation for each suggestion. + + Output format: + Error Diagnosis: + - Root Cause: ... + - Recommended Fix: ... + - Suggested Parameter Change: ... + - Reason: ... + + """ + print("[DEBUG] Added error-fix section to prompt.") + def _collect_recent_errors(self, data: Dict[str, Any], max_errors=5) -> str: + errors = [] + for run in data.get("log_data", {}).get("runs", []): + if run.get("errors"): + errors.extend(run["errors"]) + print(f"[DEBUG] Found total {len(errors)} errors in all runs.") + return "\n".join(errors[-max_errors:]) if errors else "No errors detected." + + def _call_llm(self, stage: str, data: Dict[str, Any]) -> Dict[str, Any]: + # """Call Claude to get recommendations for optimization parameters""" + # print(f"\n=== Calling LLM for {stage} stage ===") + """Call LLM to get recommendations for optimization parameters using react framework""" + print(f"\n=== Calling LLM with ReAct framework for {stage} stage ===") + + try: + react_prompt = self._generate_react_prompt(stage, data) + print(f"Generated prompt with context for {stage}") + print("=== Context Message ===") + print(react_prompt) + print("========================") + available_tools = self._create_react_tools(stage, data) + + react_result = self.react_framework.run_react_cycle( + initial_prompt=react_prompt, + available_tools=available_tools, + max_steps=1, + temperature=0.1 + ) + # === If an error occurs, enter Debug mode === + if "log_data" in data and any(run.get("errors") for run in data["log_data"].get("runs", [])): + print("\n[DEBUG] Detected errors in previous runs. Invoking Debug Assistant mode...") + + # Collect error information + all_errors = [] + for run in data["log_data"]["runs"]: + if run.get("errors"): + all_errors.extend(run["errors"]) + error_text = "\n".join(all_errors[-5:]) # Recent entries + + # Construct a Debug Prompt + debug_prompt = f""" + You are now an **EDA Debugging Expert**. + Based on the following OpenROAD errors and RAG documentation, analyze and provide concrete repair suggestions. + + Errors Detected: + {error_text} + + Please identify: + 1. Root cause of each error. + 2. Specific parameter changes (e.g., in floorplan, CTS, or routing stages) that could fix the issue. + 3. Whether this issue is due to timing, congestion, or setup misconfiguration. + 4. One short explanation per fix. + + Return your answer in **JSON format** like: + {{ + "error_analysis": [ + {{ + "error": "...", + "cause": "...", + "fix": "...", + "params_to_adjust": {{"param_name": "new_value"}} + }} + ] + }} + """ + + # Call LLM to output repair suggestions + debug_result = self.react_framework.run_react_cycle( + initial_prompt=debug_prompt, + available_tools=available_tools, + max_steps=1, + temperature=0.2 + ) + + print("\n[DEBUG] LLM Debug Assistant Result:") + print(debug_result.get("final_answer", "")) + + # Save repair suggestions to the main results + react_result["error_fix_suggestions"] = debug_result.get("final_answer", "") + # Write files for manual viewing + with open("logs/error_fix_suggestions.json", "w") as f: + f.write(debug_result.get("final_answer", "")) + print(f"\n=== ReAct Cycle Completed ===") + print(f"Completed steps: {react_result.get('completed_steps', 0)}/{react_result.get('max_steps', 8)}") + print(f"Final Answer: {react_result['final_answer']}") + + configs = self._parse_react_final_answer(react_result["final_answer"], stage) + + if react_result.get('reasoning_history'): + print(f"\n=== Reasoning History ({len(react_result['reasoning_history'])} steps) ===") + for step in react_result['reasoning_history']: + print(f"Step {step['step']}: {step.get('thought', 'No thought')}") + + print(f"Returning config for stage '{stage}': {configs}") + return configs + + except Exception as e: + print(f"Error in LLM call for stage {stage}: {e}") + default_config = { + 'inspect': {"n_clusters": 5, "correlation_threshold": 0.5}, + 'model': {"kernel_type": "matern", "preprocessing": "robust", + "acquisition": "ei", "surrogate_weight": 0.8}, + 'agglomerate': {"method": "hybrid", "quality_weight": 0.7, + "uncertainty_bonus": 0.2} + } + return default_config.get(stage, {}) + + + def _generate_react_prompt(self, stage: str, data: Dict[str, Any]) -> str: + """generate prompts of ReAct framework""" + + stage_descriptions = { + 'inspect': ( + "You are an expert EDA optimization analyst. Analyze the optimization run data to identify patterns " + "and insights. Use the available tools to examine data distributions, correlations, and successful " + "parameter ranges. Your goal is to understand what makes runs successful and provide recommendations " + "for the modeling stage." + ), + 'model': ( + "You are an expert machine learning engineer for EDA optimization. Based on the inspection results, " + "configure the modeling approach for Bayesian optimization. Consider kernel selection, acquisition " + "functions, and surrogate modeling strategies. Balance exploration and exploitation based on the data." + ), + 'agglomerate': ( + "You are an expert parameter optimization specialist. Generate new parameter combinations for the " + "next optimization iteration. Use insights from previous stages to focus on promising regions while " + "maintaining diversity. Ensure all parameters satisfy the domain constraints." + ) + } + + constraints_text = "Parameter Constraints:\n" + for param, info in self.param_constraints.items(): + constraints_text += f"- {param} ({info['type']}, range: {info['range']})\n" + + react_format_instructions = """ +**ReAct Framework Instructions - MUST FOLLOW THIS FORMAT:** + +1. **Thought**: Analyze the current situation and decide what to do next +2. **Action**: Choose one tool from the available tools +3. **Action Input**: Provide the appropriate input for the chosen tool +4. **Observation**: Wait for the tool's response, then continue reasoning + +**Available Tools**: You have access to various analysis tools. Use them to gather information before making decisions. + +**DO NOT include Final Answer until you have completed all necessary analysis.** +**DO NOT predict or simulate tool observations.** +**You will receive actual Observation from tools before continuing.** + +Only after proper analysis: +**Final Answer Format**: Only when you have completed your analysis, provide: +Final Answer: {your_configuration_here} + +**Example**: +Thought: I need to understand the data patterns first. Let me analyze the success rates. +Action: analyze_data_patterns +Action Input: {} +Observation: [Tool response...] +Thought: Now I need to check parameter correlations... +Action: analyze_correlations +Action Input: {} +Observation: [Tool response...] +Final Answer: {"n_clusters": 5, "correlation_threshold": 0.7} +""" + + prompt = f""" + {stage_descriptions[stage]} + + **Current Stage**: {stage.upper()} + **Objective**: {self.objective} + **Platform**: {self.platform} + **Design**: {self.design} + + **Available Data**: + - Total runs: {data.get('log_data', {}).get('summary', {}).get('total_runs', 0)} + - Successful runs: {data.get('log_data', {}).get('summary', {}).get('successful_runs', 0)} + - Failed runs: {data.get('log_data', {}).get('summary', {}).get('failed_runs', 0)} + + {constraints_text} + {react_format_instructions} + + Begin your analysis: + """ + + rag_context = "" + # ======== extract errors ======== + error_summary = self._collect_recent_errors(data) + if error_summary and "No errors" not in error_summary: + print("[DEBUG] RAG: Detected error summary, adding error analysis prompt...") + prompt += f""" + + ### Detected Run Errors + {error_summary} + + You are now acting as an **EDA Debugging Assistant**. + Analyze the errors above and: + 1. Identify the root causes. + 2. Suggest specific parameter changes. + 3. Indicate whether the error is due to timing, routing, or constraints. + 4. Provide short explanations for each. + + Output format: + Error Diagnosis: + - Root Cause: ... + - Recommended Fix: ... + - Suggested Parameter Change: ... + - Reason: ... + """ + else: + print("[DEBUG] No errors found in logs for this stage.") + if self.rag_model is not None and self.rag_embeddings is not None: + try: + print("[DEBUG] RAG: Starting retrieval...") + query = ( + f"Stage: {stage}. Objective: {self.objective}. " + f"Focus on analyzing {stage}-related optimization results. " + f"Important metrics include wirelength, timing, area, and success rate. " + f"Find relevant OpenROAD documentation, parameter tuning guides, and failure pattern examples." + ) + rag_context = answerWithRAG( + query, + self.rag_embeddings, + self.rag_model, + self.rag_docs, + self.rag_docsDict + ) + print(f"[DEBUG] RAG: Retrieved context length = {len(rag_context)}") + if rag_context.strip(): + prompt += ( + "\n\n=== Retrieved OpenROAD Documentation (via RAG) ===\n" + f"{rag_context}\n" + "==============================================" + ) + print("[DEBUG] RAG: Context successfully added to prompt.") + else: + print("[DEBUG] RAG: Empty context retrieved.") + except Exception as e: + prompt += f"\n\n[WARN] RAG retrieval failed: {e}" + + return prompt + + def _parse_react_final_answer(self, final_answer: str, stage: str) -> Dict[str, Any]: + """parse react final answer""" + + default_configs = { + 'inspect': {"n_clusters": 5, "correlation_threshold": 0.5}, + 'model': {"kernel_type": "matern", "preprocessing": "robust", + "acquisition": "ei", "surrogate_weight": 0.8}, + 'selection': {"method": "hybrid", "quality_weight": 0.7, + "uncertainty_bonus": 0.2} + } + + configs = {} + + if final_answer and "Reached maximum steps" not in final_answer: + try: + json_match = re.search(r'\{.*\}', final_answer, re.DOTALL) + if json_match: + extracted_config = json.loads(json_match.group()) + configs[stage] = extracted_config + print(f"✓ Extracted configuration from ReAct response: {extracted_config}") + else: + configs[stage] = default_configs.get(stage, {}) + print(f"⚠ Using default configuration for {stage} stage") + except Exception as e: + print(f"Error parsing ReAct final answer: {e}") + configs[stage] = default_configs.get(stage, {}) + else: + configs[stage] = default_configs.get(stage, {}) + print(f"ReAct failed to produce answer, using default for {stage}") + + return configs + + def run_iteration(self, num_runs: int) -> None: + """Run a complete iteration of the optimization workflow using react framework""" + print(f"\n=== Starting optimization iteration for {self.platform}/{self.design} ===") + print(f"Objective: {self.objective}") + print(f"Number of runs requested: {num_runs}") + + # Step 1: Inspect logs + print("\nStep 1: Inspecting logs...") + log_data = self.inspect_logs() + print(f"Found {log_data['summary']['total_runs']} total runs, " + f"{log_data['summary']['successful_runs']} successful") + + # Get LLM recommendations for inspection and analysis + # print("\nGetting LLM recommendations for inspection...") + print("\nGetting LLM recommendations with ReAct framework for inspection...") + inspect_configs = self._call_llm('inspect', { + 'log_data': log_data, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context + }) + inspection_config = inspect_configs.get('inspect', {}) + print(f"React inspection config: {inspection_config}") + + # Step 2: Analyze metrics with LLM config + print("\nStep 2: Analyzing metrics ...") + metrics = self.analyze_metrics( + log_data, + # n_clusters=inspect_configs['inspection']['n_clusters'], + n_clusters=inspection_config.get('n_clusters', 5), + # correlation_threshold=inspect_configs['inspection']['correlation_threshold'] + correlation_threshold=inspection_config.get('correlation_threshold', 0.5) + ) + print(f"Processed metrics for {len(metrics.get('objectives', []))} successful runs") + + # Get LLM recommendations for modeling based on inspection results with ReAct framework + print("\nGetting LLM recommendations with ReAct framework for modeling...") + model_configs = self._call_llm('model', { + 'log_data': log_data, + 'metrics': metrics, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs + }) + model_config = model_configs.get('model', {}) + print(f"LLM model config: {model_config}") + + # Step 3: Evaluate models with LLM config + print("\nStep 3: Evaluating models...") + model_results = self.evaluate_models( + log_data, metrics, + # kernel_type=model_configs['model']['kernel_type'], + model_config.get('kernel_type', 'matern'), + # preprocessing=model_configs['model']['preprocessing'], + preprocessing=model_config.get('preprocessing', 'robust'), + # acquisition=model_configs['model']['acquisition'], + acquisition=model_config.get('acquisition', 'ei'), + # surrogate_weight=model_configs['model']['surrogate_weight'] + surrogate_weight=model_config.get('surrogate_weight', 0.8) + ) + + # Get LLM recommendations for parameter selection based on all previous results with ReAct framework + print("\nGetting LLM recommendations with ReAct framework for parameter selection...") + selection_configs = self._call_llm('agglomerate', { + 'log_data': log_data, + 'metrics': metrics, + 'model_results': model_results, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs, + 'model_configs': model_configs + }) + selection_config = selection_configs.get('agglomerate', {}) + print(f"LLM selection config: {selection_config}") + + # Step 4: Generate parameters with LLM config + print("\nStep 4: Generating parameters...") + self.generate_parameters( + log_data, metrics, model_results, num_runs, + # selection_method=selection_configs['selection']['method'], + # quality_weight=selection_configs['selection']['quality_weight'], + # uncertainty_bonus=selection_configs['selection']['uncertainty_bonus'] + selection_method=selection_config.get('method', 'hybrid'), + quality_weight=selection_config.get('quality_weight', 0.7), + uncertainty_bonus=selection_config.get('uncertainty_bonus', 0.2) + ) + + def inspect_logs(self) -> Dict[str, Any]: + """Step 1: Inspect all .log and .json logs recursively""" + log_dir = "logs" + pattern = f"{self.platform}_{self.design}_run" + + log_data = { + 'runs': [], + 'summary': { + 'total_runs': 0, + 'successful_runs': 0, + 'failed_runs': 0 + } + } + + if not os.path.exists(log_dir): + return log_data + + run_groups = {} + + for root, _, files in os.walk(log_dir): + for log_file in files: + if log_file.endswith(('.log', '.json')): + log_path = os.path.join(root, log_file) + + if log_file.startswith(pattern) or (self.platform in root and self.design in root): + + run_id = "main" + m = re.search(r'_run(\d+)\.log$', log_file) + if m: + run_id = f"base_{m.group(1)}" + + elif 'base_' in root: + run_id = os.path.basename(root) + + run_data = process_log_file(log_path) + + if run_id not in run_groups: + run_groups[run_id] = { + 'run_id': run_id, + 'success': True, + 'metrics': {}, + 'errors': [], + 'files': [] + } + + run_groups[run_id]['success'] &= run_data.get('success', True) + run_groups[run_id]['files'].append(log_path) + + if 'metrics' in run_data and run_data['metrics']: + run_groups[run_id]['metrics'].update(run_data['metrics']) + + if 'errors' in run_data and run_data['errors']: + run_groups[run_id]['errors'].extend(run_data['errors']) + + for run_id, run_data in run_groups.items(): + print(f"DEBUG: Run {run_id} success: {run_data['success']}") + print(f"DEBUG: Run {run_id} metrics: {run_data['metrics']}") + print(f"DEBUG: Run {run_id} errors: {run_data['errors']}") + print(f"DEBUG: Run {run_id} files: {run_data['files']}") + + log_data['runs'].append(run_data) + log_data['summary']['total_runs'] += 1 + if run_data['success']: + log_data['summary']['successful_runs'] += 1 + else: + log_data['summary']['failed_runs'] += 1 + + return log_data + + + def analyze_metrics(self, log_data: Dict[str, Any], n_clusters: int, correlation_threshold: float) -> Dict[str, Any]: + """Step 2: Analyze metrics from log data with improved analysis""" + metrics = { + 'objectives': [], + 'surrogates': [], + 'correlations': {}, + 'structure_analysis': {} + } + + # Extract feature vectors and objectives + feature_vectors = [] + objective_values = [] + surrogate_values = [] + + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + run_metrics = run['metrics'] + obj_values = self._calculate_objective(run) + + if obj_values['value'] is not None or obj_values['surrogate'] is not None: + # Extract parameter values as features + params = [] + for param in self.parameter_names: + params.append(float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0)))) + feature_vectors.append(params) + + objective_values.append(obj_values['value'] if obj_values['value'] is not None else np.nan) + surrogate_values.append(obj_values['surrogate'] if obj_values['surrogate'] is not None else np.nan) + + # Track correlations and other metrics + if obj_values['value'] is not None: + metrics['objectives'].append(obj_values['value']) + if obj_values['surrogate'] is not None: + metrics['surrogates'].append(obj_values['surrogate']) + + if obj_values['value'] is not None and obj_values['surrogate'] is not None: + if 'real_vs_surrogate' not in metrics['correlations']: + metrics['correlations']['real_vs_surrogate'] = [] + metrics['correlations']['real_vs_surrogate'].append({ + 'real': obj_values['value'], + 'surrogate': obj_values['surrogate'] + }) + + if feature_vectors: + X = np.array(feature_vectors) + Y = np.array(objective_values) + Y_surrogate = np.array(surrogate_values) + + # Use improved inspection functions + metrics['distribution_analysis'] = inspect_data_distribution(X, Y, Y_surrogate) + metrics['structure_analysis'] = inspect_data_structure(X, Y, { + 'n_clusters': n_clusters, + 'correlation_threshold': correlation_threshold + }) + + # Extract model recommendations if available (from new functions) + if 'model_recommendations' in metrics['structure_analysis']: + metrics['model_recommendations'] = metrics['structure_analysis']['model_recommendations'] + + # Add objective-specific metrics + if self.objective == 'ECP': + metrics['clock_period_impact'] = {} + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + period = float(run['metrics'].get('clock_period', 0)) + if period > 0: + if period not in metrics['clock_period_impact']: + metrics['clock_period_impact'][period] = { + 'final_slack': [], + 'cts_slack': [] + } + if 'worst_slack' in run['metrics']: + metrics['clock_period_impact'][period]['final_slack'].append( + float(run['metrics']['worst_slack'])) + if 'cts_ws' in run['metrics']: + metrics['clock_period_impact'][period]['cts_slack'].append( + float(run['metrics']['cts_ws'])) + + elif self.objective == 'DWL': + metrics['wirelength_progression'] = [] + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + if 'cts_wirelength' in run['metrics'] and 'total_wirelength' in run['metrics']: + metrics['wirelength_progression'].append({ + 'cts': float(run['metrics']['cts_wirelength']), + 'final': float(run['metrics']['total_wirelength']) + }) + + return metrics + + + def evaluate_models(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + kernel_type: str, preprocessing: str, acquisition: str, surrogate_weight: float) -> Dict[str, Any]: + """Step 3: Use improved model functions to evaluate parameter quality""" + model_results = {} + + # Build context from log data and metrics + context = { + 'log_data': log_data, + 'metrics': metrics, + 'design_config': self.design_config, + 'initial_params': self.initial_params, + 'model_recommendations': metrics.get('model_recommendations', {}) + } + + # Use model recommendations if available (from new functions) + if 'model_recommendations' in metrics: + kernel_type = metrics['model_recommendations'].get('kernel_type', kernel_type) + preprocessing = 'robust' if metrics['model_recommendations'].get('needs_feature_scaling', True) else 'none' + + # Call appropriate model functions with improved modeling + if self.objective == 'ECP': + model_results = evaluate_timing_model(context) + elif self.objective == 'DWL': + model_results = evaluate_wirelength_model(context) + + # Add model configuration used + model_results['configuration'] = { + 'kernel_type': kernel_type, + 'preprocessing': preprocessing, + 'acquisition': acquisition, + 'surrogate_weight': surrogate_weight + } + + return model_results + + def generate_parameters(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + model_results: Dict[str, Any], num_runs: int, + selection_method: str = 'hybrid', quality_weight: float = 0.7, + uncertainty_bonus: float = 0.2, model_config: Dict[str, Any] = None) -> None: + """Step 4: Generate parameter combinations and write to CSV""" + # Get list of parameters to optimize from constraints + param_names = list(self.param_constraints.keys()) + print(f"\nGenerating parameters for {len(param_names)} variables:") + for name in param_names: + print(f" - {name}: {self.param_constraints[name]}") + + # Extract successful runs for training data + successful_params = [] + successful_objectives = [] + for run in log_data.get('runs', []): + if run.get('success', False) and 'metrics' in run: + params = {} + for param in param_names: + params[param] = float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0))) + successful_params.append(params) + + obj = self._calculate_objective(run) + successful_objectives.append(obj['value'] if obj['value'] is not None else obj['surrogate']) + + print(f"Using {len(successful_params)} successful runs as training data") + + # Convert to numpy arrays + if successful_params: + X = np.array([[params[name] for name in param_names] for params in successful_params]) + y = np.array(successful_objectives) + else: + print("Warning: No successful runs, using initial parameters as base") + X = np.array([[float(self.initial_params.get(name, 0)) for name in param_names]]) + y = np.array([0.0]) + + # Get kernel type from model config + kernel_type = model_config.get('kernel_type', 'matern') if model_config else 'matern' + print(f"\nCreating surrogate model with {kernel_type} kernel") + model = create_model(X, y, kernel_type=kernel_type) + + # Generate candidates + n_candidates = num_runs * 10 + print(f"Generating {n_candidates} candidate points") + candidates = latin_hypercube(n_candidates, len(param_names)) + + # Scale candidates to parameter ranges + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + candidates[:, i] = candidates[:, i] * (max_val - min_val) + min_val + + # Get predictions + predictions, uncertainties = model.predict(candidates, return_std=True) + + # Select points + print(f"\nSelecting points using {selection_method} method") + print(f"Quality weight: {quality_weight}, Uncertainty bonus: {uncertainty_bonus}") + quality_scores = create_quality_scores(candidates, y, predictions, uncertainties) + selected_indices = select_points( + candidates, quality_scores, + method=selection_method, + n_points=num_runs, + config={"quality_weight": quality_weight, + "uncertainty_bonus": uncertainty_bonus} + ) + + selected_params = candidates[selected_indices] + + # Validate domain constraints + print("\nValidating domain constraints...") + valid_params = [] + for params in selected_params: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + else: + print("Warning: Parameter set failed domain constraints") + + print(f"Found {len(valid_params)} valid parameter sets out of {len(selected_params)}") + + # Generate more if needed + while len(valid_params) < num_runs: + needed = num_runs - len(valid_params) + print(f"Generating {needed} additional parameter sets...") + new_candidates = latin_hypercube(needed, len(param_names)) + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + new_candidates[:, i] = new_candidates[:, i] * (max_val - min_val) + min_val + + for params in new_candidates: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + if len(valid_params) >= num_runs: + break + + # Write to CSV + print(f"\nWriting {num_runs} parameter sets to CSV...") + self._write_params_to_csv(valid_params[:num_runs]) + + def _calculate_objective(self, run: Dict[str, Any]) -> Dict[str, float]: + """Calculate objective value and surrogate from run metrics""" + metrics = run.get('metrics', {}) + result = {'value': None, 'surrogate': None} + + if self.objective == 'ECP': + if 'clock_period' in metrics: + period = float(metrics['clock_period']) + # Real ECP from final worst slack + if 'worst_slack' in metrics: + result['value'] = period - float(metrics['worst_slack']) + # Surrogate ECP from CTS worst slack + if 'cts_ws' in metrics: + result['surrogate'] = period - float(metrics['cts_ws']) + + elif self.objective == 'DWL': + # Real wirelength from detailed route + if 'total_wirelength' in metrics: + result['value'] = float(metrics['total_wirelength']) + # Surrogate wirelength from CTS + if 'cts_wirelength' in metrics: + result['surrogate'] = float(metrics['cts_wirelength']) + + elif self.objective == 'COMBO': + # Get weights from environment variables + try: + ecp_weight = float(os.environ.get('ECP_WEIGHT')) + wl_weight = float(os.environ.get('WL_WEIGHT')) + ecp_weight_surrogate = float(os.environ.get('ECP_WEIGHT_SURROGATE')) + wl_weight_surrogate = float(os.environ.get('WL_WEIGHT_SURROGATE')) + except (ValueError, TypeError): + raise ValueError("Weights not properly set in environment variables.") + + # Calculate real ECP and WL values + ecp_value = None + wl_value = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'worst_slack' in metrics: + ecp_value = clock_period - float(metrics['worst_slack']) + if 'total_wirelength' in metrics: + wl_value = float(metrics['total_wirelength']) + + # Calculate surrogate ECP and WL values + ecp_surrogate = None + wl_surrogate = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'cts_ws' in metrics: + ecp_surrogate = clock_period - float(metrics['cts_ws']) + if 'cts_wirelength' in metrics: + wl_surrogate = float(metrics['cts_wirelength']) + + # Calculate weighted objective for real values + if ecp_value is not None and wl_value is not None: + result['value'] = ecp_weight * ecp_value + wl_weight * wl_value + elif ecp_value is not None: + result['value'] = ecp_weight * ecp_value + elif wl_value is not None: + result['value'] = wl_weight * wl_value + + # Calculate weighted surrogate objective + if ecp_surrogate is not None and wl_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + wl_weight_surrogate * wl_surrogate + elif ecp_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + elif wl_surrogate is not None: + result['surrogate'] = wl_weight_surrogate * wl_surrogate + + return result + + def _validate_domain_constraints(self, params: Dict[str, Any]) -> bool: + """Validate parameter combinations against domain constraints""" + # 1. Core utilization vs cell padding + core_util = float(params.get('core_util', 0)) + gp_pad = float(params.get('cell_pad_global', 0)) + dp_pad = float(params.get('cell_pad_detail', 0)) + + if core_util > 80 and (gp_pad > 2 or dp_pad > 2): + print(f"Domain constraint failed: core_util > 80 and gp_pad > 2 or dp_pad > 2") + return False + + # 2. TNS end percent vs place density + tns_end = float(params.get('tns', 0)) + place_density = float(params.get('lb_addon', 0)) + + if tns_end < 70 and place_density > 0.7: + print(f"Domain constraint failed: tns_end < 70 and place_density > 0.7") + return False + + # 3. CTS cluster constraints + cts_size = float(params.get('cts_size', 0)) + cts_diameter = float(params.get('cts_diameter', 0)) + + if cts_size > 30 and cts_diameter < 100: + print(f"Domain constraint failed: cts_size > 30 and cts_diameter < 100") + return False + + return True + + def _write_params_to_csv(self, params_list: List[Dict[str, Any]]) -> None: + """Write the new parameter sets to the expected CSV file for the next iteration""" + csv_file = f"designs/{self.platform}/{self.design}/{self.platform}_{self.design}.csv" + + # Ensure parameters are in correct order and properly typed + with open(csv_file, 'w', newline='\n') as f: # Explicitly use Unix line endings + writer = csv.writer(f) + # Write header in correct order + writer.writerow(self.parameter_names) + + # Write parameter rows + for params in params_list: + row = [] + for param_name in self.parameter_names: + value = params.get(param_name) + if value is None: + print(f"Warning: Missing value for parameter {param_name}") + continue + + # Apply type constraints + constraint = self.param_constraints[param_name] + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param_name} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + + except (ValueError, TypeError) as e: + print(f"Error converting {param_name} value '{value}' to {param_type}: {e}") + continue + + row.append(value) + + if len(row) == len(self.parameter_names): + writer.writerow(row) + else: + print(f"Warning: Skipping incomplete parameter set") + + print(f"New parameter sets written to {csv_file}") + + def _parse_llm_output(self, llm_response: str) -> List[Dict[str, Any]]: + """Parse the LLM's response and enforce parameter constraints""" + try: + param_sets = json.loads(llm_response) + except json.JSONDecodeError as e: + print(f"Error parsing LLM response: {e}") + return [] + + constrained_params = [] + for param_set in param_sets: + ordered_params = {} + valid = True + for param in self.parameter_names: + value = param_set.get(param) + if value is None: + print(f"Parameter '{param}' is missing in the LLM output.") + valid = False + break + + constraint = self.param_constraints.get(param) + if constraint: + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + elif param_type != 'float': + raise ValueError(f"Unsupported parameter type: {param_type}") + + ordered_params[param] = value + except (ValueError, TypeError) as e: + print(f"Parameter '{param}' has invalid value '{value}': {e}") + valid = False + break + else: + print(f"Unknown parameter '{param}' in parameter set.") + valid = False + break + + if valid and self._validate_domain_constraints(ordered_params): + constrained_params.append(ordered_params) + else: + print(f"Parameter set {ordered_params} failed validation and will be discarded.") + + return constrained_params + + def generate_initial_parameters(self, num_runs: int) -> None: + """Generate initial random parameters and write them to CSV using the same method as subsequent iterations""" + params_list = [] + for _ in range(num_runs): + params = {} + for param in self.parameter_names: + info = self.param_constraints[param] + param_type = info['type'] + min_value, max_value = info['range'] + if param_type == 'int': + value = random.randint(int(min_value), int(max_value)) + elif param_type == 'float': + value = random.uniform(min_value, max_value) + else: + continue # Skip unsupported types + params[param] = value + params_list.append(params) + + # Use the same method to write parameters to CSV + self._write_params_to_csv(params_list) + +def main(): + if len(sys.argv) != 5: + print("Usage: optimize.py ") + sys.exit(1) + + platform = sys.argv[1] + design = sys.argv[2] + objective = sys.argv[3] + num_runs = int(sys.argv[4]) + + workflow = OptimizationWorkflow(platform, design, objective) + workflow.run_iteration(num_runs) # Use the run_iteration method instead of individual steps + +if __name__ == "__main__": + main() diff --git a/flow-Agent/extract_log_metrics.py b/flow-Agent/extract_log_metrics.py new file mode 100644 index 0000000..916e6be --- /dev/null +++ b/flow-Agent/extract_log_metrics.py @@ -0,0 +1,116 @@ +#!/usr/bin/env python3 +""" +Extract wirelength and clock period metrics from result_dump logs and write a markdown report. + +Targets: +- 5_1_grt.log: line containing "[INFO GRT-0018] Total wirelength:" +- 1_1_yosys_canonicalize.log: line containing "Setting clock period to" +""" + +from __future__ import annotations + +import argparse +import datetime as _dt +import re +from pathlib import Path +from typing import Iterable, Optional, Tuple + + +WIRELENGTH_RE = re.compile(r"\[INFO GRT-0018\]\s*Total wirelength:\s*([0-9.]+)\s*um", re.IGNORECASE) +CLOCK_RE = re.compile(r"Setting clock period to\s*([0-9.]+)", re.IGNORECASE) + + +def parse_numeric(pattern: re.Pattern[str], path: Path) -> Optional[str]: + try: + with path.open("r", encoding="utf-8", errors="ignore") as fh: + for line in fh: + match = pattern.search(line) + if match: + return match.group(1) + except FileNotFoundError: + return None + return None + + +def discover_results(base_dir: Path) -> Iterable[Tuple[str, str, Path]]: + for result_dir in sorted(base_dir.glob("result_dump_*"), key=_numeric_suffix): + logs_root = result_dir / "logs_dump" + if not logs_root.is_dir(): + continue + for base_dir in sorted(logs_root.glob("base_*"), key=_numeric_suffix): + yield ( + result_dir.name.replace("result_dump_", ""), + base_dir.name.replace("base_", ""), + base_dir, + ) + + +def _numeric_suffix(path: Path) -> int: + stem = path.name.split("_")[-1] + try: + return int(stem) + except ValueError: + return 0 + + +def build_markdown(rows: list[dict[str, str]], source_root: Path) -> str: + timestamp = _dt.datetime.now().strftime("%Y-%m-%d %H:%M:%S") + lines = [ + "# Log Metrics Summary", + "", + f"- Source root: `{source_root}`", + f"- Generated at: {timestamp}", + "", + "| result_dump | base | clock_period | total_wirelength |", + "| --- | --- | --- | --- |", + ] + for row in rows: + lines.append( + f"| {row['result']} | {row['base']} | {row['clock']} | {row['wirelength']} |" + ) + if not rows: + lines.append("| (none) | (none) | (none) | (none) |") + return "\n".join(lines) + "\n" + + +def main() -> None: + repo_root = Path(__file__).resolve().parent + default_output = repo_root / "output_results" / "asap7" / "log_metrics.md" + + parser = argparse.ArgumentParser( + description="Extract wirelength and clock period metrics from result_dump logs." + ) + parser.add_argument( + "--output", + type=Path, + default=default_output, + help=f"Output markdown file (default: {default_output})", + ) + parser.add_argument( + "--source", + type=Path, + default=repo_root / "backup_dir" / "asap7" / "aes", + help="Root directory containing result_dump_* directories.", + ) + args = parser.parse_args() + + rows: list[dict[str, str]] = [] + for result_id, base_id, base_path in discover_results(args.source): + clock = parse_numeric(CLOCK_RE, base_path / "1_1_yosys_canonicalize.log") + wirelength = parse_numeric(WIRELENGTH_RE, base_path / "5_1_grt.log") + rows.append( + { + "result": result_id, + "base": base_id, + "clock": clock or "N/A", + "wirelength": f"{wirelength} um" if wirelength else "N/A", + } + ) + + output_md = build_markdown(rows, args.source) + args.output.parent.mkdir(parents=True, exist_ok=True) + args.output.write_text(output_md, encoding="utf-8") + + +if __name__ == "__main__": + main() diff --git a/flow-Agent/figures/README.md b/flow-Agent/figures/README.md new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/flow-Agent/figures/README.md @@ -0,0 +1 @@ + diff --git a/flow-Agent/figures/expanding.png b/flow-Agent/figures/expanding.png new file mode 100644 index 0000000..64af2b5 Binary files /dev/null and b/flow-Agent/figures/expanding.png differ diff --git a/flow-Agent/figures/framework.png b/flow-Agent/figures/framework.png new file mode 100644 index 0000000..fc104e5 Binary files /dev/null and b/flow-Agent/figures/framework.png differ diff --git a/flow-Agent/maindriver.sh b/flow-Agent/maindriver.sh index 731f332..7dd65e1 100644 --- a/flow-Agent/maindriver.sh +++ b/flow-Agent/maindriver.sh @@ -1,11 +1,11 @@ #!/bin/bash # Default values -TOTAL_ITERS=6 -PARALLEL_RUNS=50 +TOTAL_ITERS=20 +PARALLEL_RUNS=4 TIMEOUT="45m" -TOTAL_CPUS=110 -TOTAL_RAM=220 +TOTAL_CPUS=8 +TOTAL_RAM=16 ECP_WEIGHT=0.5 WL_WEIGHT=0.5 ECP_WEIGHT_SURROGATE=0.5 @@ -82,6 +82,10 @@ if [[ "$objective" != "ECP" && "$objective" != "DWL" && "$objective" != "COMBO" fi # Validate weights sum to 1 +export PLATFORM=$platform +export DESIGN=$design +export OBJECTIVE=$objective + if [[ "$objective" == "COMBO" ]]; then # Ensure jq is installed if ! command -v jq &> /dev/null; then @@ -191,13 +195,14 @@ create_backup() { local platform=$1 local design=$2 local iteration=$3 - local backup_dir="../result_dump_${iteration}" + local backup_dir="./backup_dir/${platform}/${design}/result_dump_${iteration}" echo "Creating backup for iteration ${iteration}..." mkdir -p "$backup_dir" # Move config and constraint files - mv designs/${platform}/${design}/config_*.mk "$backup_dir"/ 2>/dev/null + # mv designs/${platform}/${design}/config_*.mk "$backup_dir"/ 2>/dev/null + cp designs/${platform}/${design}/config_*.mk "$backup_dir"/ 2>/dev/null mv designs/${platform}/${design}/constraint_*.sdc "$backup_dir"/ 2>/dev/null if [[ "$platform" == "asap7" && "$design" == "jpeg" ]]; then mv designs/${platform}/${design}/jpeg_encoder15_7nm_*.sdc "$backup_dir"/ 2>/dev/null @@ -222,7 +227,10 @@ for i in $(seq 1 $TOTAL_ITERS); do echo "Starting iteration $i of $TOTAL_ITERS" # Run sequential phase + # echo '"$platform" "$design" "$PARALLEL_RUNS" "$i"' + echo "${platform}, ${design}, ${PARALLEL_RUNS}, ${i}" ./run_sequential.sh "$platform" "$design" "$PARALLEL_RUNS" "$i" + echo "./run_sequential.sh \"$platform\" \"$design\" \"$PARALLEL_RUNS\" \"$i\"" # Run parallel phase with timeout timeout "$TIMEOUT" ./run_parallel.sh "$platform" "$design" "$PARALLEL_RUNS" || true @@ -235,9 +243,16 @@ for i in $(seq 1 $TOTAL_ITERS); do # Generate constraints for next iteration (skip for last iteration) if [ "$i" -lt "$TOTAL_ITERS" ]; then + for objective in "$objective"; do + echo "Running optimization for $objective" + python3 stage_optimize.py "$platform" "$design" "$objective" --max-react-steps 3 + python3 stage_override.py "$platform" "$design" "$objective" + cp -r results/ results_${platform}_${design}_${objective}/ + done echo "Running optimization for next iteration..." - python3 optimize.py "$platform" "$design" "$objective" "$PARALLEL_RUNS" + python3 optimize.py "$platform" "$design" "$objective" "$PARALLEL_RUNS" + echo "python3 optimize.py \"$platform\" \"$design\" \"$PARALLEL_RUNS\" \"$i\"" fi done -echo "All iterations complete" \ No newline at end of file +echo "All iterations complete" diff --git a/flow-Agent/maindriver_stage.sh b/flow-Agent/maindriver_stage.sh new file mode 100644 index 0000000..4f0d10b --- /dev/null +++ b/flow-Agent/maindriver_stage.sh @@ -0,0 +1,399 @@ +#!/bin/bash + +# Default values +TOTAL_ITERS=6 +PARALLEL_RUNS=50 +TIMEOUT="45m" +TOTAL_CPUS=110 +TOTAL_RAM=220 +ECP_WEIGHT=0.5 +WL_WEIGHT=0.5 +ECP_WEIGHT_SURROGATE=0.5 +WL_WEIGHT_SURROGATE=0.5 +RUN_STAGE_OPTIMIZE=0 +RUN_STAGE_OVERRIDE=0 +RUN_OPTIMIZE=0 +STAGE_OPT_STAGES="" +STAGE_OPT_MAX_STEPS=3 +STAGE_OPT_TEMPERATURE=0.1 +STAGE_OPT_DRY_RUN=0 +STAGE_OVERRIDE_STAGES="" +STAGE_OVERRIDE_MAX_STEPS=3 +STAGE_OVERRIDE_TEMPERATURE=0.1 +STAGE_OVERRIDE_DRY_RUN=0 +OVERRIDE_FILES=() +OVERRIDE_PARAMS=() + +# Parse command line arguments +while [[ $# -gt 0 ]]; do + case $1 in + -p|--platform) + platform="$2" + shift 2 + ;; + -d|--design) + design="$2" + shift 2 + ;; + -i|--iterations) + TOTAL_ITERS="$2" + shift 2 + ;; + -r|--parallel-runs) + PARALLEL_RUNS="$2" + shift 2 + ;; + -t|--timeout) + TIMEOUT="$2" + shift 2 + ;; + -o|--objective) + objective="$2" + shift 2 + ;; + --run-stage-optimize) + RUN_STAGE_OPTIMIZE=1 + shift + ;; + --stage-opt-stages) + STAGE_OPT_STAGES="$2" + shift 2 + ;; + --stage-opt-max-steps) + STAGE_OPT_MAX_STEPS="$2" + shift 2 + ;; + --stage-opt-temperature) + STAGE_OPT_TEMPERATURE="$2" + shift 2 + ;; + --stage-opt-dry-run) + STAGE_OPT_DRY_RUN=1 + shift + ;; + --run-stage-override) + RUN_STAGE_OVERRIDE=1 + shift + ;; + --run-optimize) + RUN_OPTIMIZE=1 + shift + ;; + --override-stages) + STAGE_OVERRIDE_STAGES="$2" + shift 2 + ;; + --override-file) + OVERRIDE_FILES+=("$2") + shift 2 + ;; + --override-param) + OVERRIDE_PARAMS+=("$2") + shift 2 + ;; + --override-max-steps) + STAGE_OVERRIDE_MAX_STEPS="$2" + shift 2 + ;; + --override-temperature) + STAGE_OVERRIDE_TEMPERATURE="$2" + shift 2 + ;; + --override-dry-run) + STAGE_OVERRIDE_DRY_RUN=1 + shift + ;; + *) + echo "Unknown option: $1" + exit 1 + ;; + esac +done + +# Validate required arguments +if [[ -z "$platform" || -z "$design" ]]; then + echo "Usage: $0 -p -d [-i iterations] [-r parallel_runs] [-t timeout] [-o objective]" + echo " platform: asap7 or sky130hd" + echo " design: aes, ibex, or jpeg" + echo " iterations: total number of iterations (default: 6)" + echo " parallel_runs: number of parallel runs (default: 50)" + echo " timeout: timeout per run (default: 45m)" + echo " objective: ecp, wl, or weighted (default: ecp)" + echo " --run-stage-optimize: invoke stage_optimize.py before optimize_raw" + echo " --stage-opt-stages \"synth place\": optional subset passed to stage_optimize.py" + echo " --run-stage-override: invoke stage_override.py with provided overrides" + echo " --override-file file.json / --override-param stage.param=value: supply overrides" + echo " --run-optimize: invoke optimize.py alongside optimize_raw.py each iteration" + exit 1 +fi + +# Set default objective if not specified +objective=${objective:-"ECP"} + +# Convert objective to uppercase for consistency +objective="${objective^^}" + +# Validate platform +if [[ "$platform" != "asap7" && "$platform" != "sky130hd" ]]; then + echo "Error: platform must be either asap7 or sky130hd" + exit 1 +fi + +# Validate design +if [[ "$design" != "aes" && "$design" != "ibex" && "$design" != "jpeg" ]]; then + echo "Error: design must be one of: aes, ibex, jpeg" + exit 1 +fi + +# Validate objective +if [[ "$objective" != "ECP" && "$objective" != "DWL" && "$objective" != "COMBO" ]]; then + echo "Error: objective must be one of: ECP, DWL, COMBO" + exit 1 +fi + +# Validate weights sum to 1 +export PLATFORM=$platform +export DESIGN=$design +export OBJECTIVE=$objective + +if [[ "$objective" == "COMBO" ]]; then + # Ensure jq is installed + if ! command -v jq &> /dev/null; then + echo "Error: jq is required but not installed. Please install jq." + exit 1 + fi + + # Read weights from opt_config.json + weights=$(jq -r \ + --arg pdk "$platform" \ + --arg design "$design" \ + --arg goal "$objective" \ + '.configurations[] | select(.platform == $pdk and .design == $design and .goal == $goal)' \ + opt_config.json) + + if [[ -z "$weights" || "$weights" == "null" ]]; then + echo "Error: Could not find weights for platform $platform and design $design in opt_config.json." + exit 1 + fi + + # Extract real metric weights + ECP_WEIGHT=$(echo "$weights" | jq -r '.weights.ecp') + WL_WEIGHT=$(echo "$weights" | jq -r '.weights.dwl') + + # Extract surrogate metric weights + ECP_WEIGHT_SURROGATE=$(echo "$weights" | jq -r '.weights_surrogate.ecp') + WL_WEIGHT_SURROGATE=$(echo "$weights" | jq -r '.weights_surrogate.dwl') + + # Validate that the weights sum to 1 + weight_sum=$(echo "$ECP_WEIGHT + $WL_WEIGHT" | bc -l) + if (( $(echo "$weight_sum != 1" | bc -l) )); then + echo "Error: ECP_WEIGHT ($ECP_WEIGHT) and WL_WEIGHT ($WL_WEIGHT) must sum to 1." + exit 1 + fi + + surrogate_weight_sum=$(echo "$ECP_WEIGHT_SURROGATE + $WL_WEIGHT_SURROGATE" | bc -l) + if (( $(echo "$surrogate_weight_sum != 1" | bc -l) )); then + echo "Error: ECP_WEIGHT_SURROGATE ($ECP_WEIGHT_SURROGATE) and WL_WEIGHT_SURROGATE ($WL_WEIGHT_SURROGATE) must sum to 1." + exit 1 + fi + + # Export weights for use in optimize.py + export ECP_WEIGHT + export WL_WEIGHT + export ECP_WEIGHT_SURROGATE + export WL_WEIGHT_SURROGATE +fi + +# Calculate resources per run +cpus_per_run=$(( TOTAL_CPUS / PARALLEL_RUNS )) +ram_per_run=$(( TOTAL_RAM / PARALLEL_RUNS )) + +# Ensure minimum resources +if [[ $cpus_per_run -lt 2 ]]; then + echo "Warning: Not enough CPUs. Reducing parallel runs to $((TOTAL_CPUS / 2))" + PARALLEL_RUNS=$((TOTAL_CPUS / 2)) + cpus_per_run=2 +fi + +if [[ $ram_per_run -lt 4 ]]; then + echo "Warning: Not enough RAM. Reducing parallel runs to $((TOTAL_RAM / 4))" + PARALLEL_RUNS=$((TOTAL_RAM / 4)) + ram_per_run=4 +fi + +# Export resource variables for child scripts +export PARALLEL_RUNS +export CPUS_PER_RUN=$cpus_per_run +export RAM_PER_RUN=$ram_per_run +export TIMEOUT + +# Create logs directory +mkdir -p logs + +# Define the line numbers for DESIGN_CONFIG lines +start_line=9 +end_line=15 + +# Function to comment all DESIGN_CONFIG lines +comment_all_design_configs() { + sed -i "${start_line},${end_line} s/^\([^#]\)/#\1/" Makefile +} + +# Function to uncomment a specific DESIGN_CONFIG line +uncomment_design_config_line() { + local line_num=$1 + sed -i "${line_num} s/^#//" Makefile +} + +# Comment all DESIGN_CONFIG lines first +comment_all_design_configs + +# Find the line number matching the desired DESIGN_CONFIG +config_pattern="DESIGN_CONFIG=./designs/${platform}/${design}/config_\\\$(INT_PARAM).mk" +line_num=$(grep -n "$config_pattern" Makefile | cut -d: -f1) + +if [ -n "$line_num" ]; then + # Uncomment the specific DESIGN_CONFIG line + uncomment_design_config_line $line_num +else + echo "Error: Could not find DESIGN_CONFIG line for platform: $platform, design: $design" + exit 1 +fi + +# Function to create backup +create_backup() { + local platform=$1 + local design=$2 + local iteration=$3 + local backup_dir="./backup_dir/${platform}/${design}/result_dump_${iteration}" + + echo "Creating backup for iteration ${iteration}..." + mkdir -p "$backup_dir" + + # Move config and constraint files + # mv designs/${platform}/${design}/config_*.mk "$backup_dir"/ 2>/dev/null + cp designs/${platform}/${design}/config_*.mk "$backup_dir"/ 2>/dev/null + mv designs/${platform}/${design}/constraint_*.sdc "$backup_dir"/ 2>/dev/null + if [[ "$platform" == "asap7" && "$design" == "jpeg" ]]; then + mv designs/${platform}/${design}/jpeg_encoder15_7nm_*.sdc "$backup_dir"/ 2>/dev/null + fi + + # Move logs + mkdir -p "$backup_dir/logs_dump" + mv logs/${platform}/${design}/* "$backup_dir/logs_dump"/ 2>/dev/null + + # Move results + mkdir -p "$backup_dir/results_dump" + mv results/${platform}/${design}/* "$backup_dir/results_dump"/ 2>/dev/null + + # Move platform_design log files from current directory + mv ${platform}_${design}*.log "$backup_dir"/ 2>/dev/null + + echo "Backup created in ${backup_dir}" +} + +run_stage_optimize() { + local cmd=(python3 stage_optimize.py "$platform" "$design" "$objective" "--max-react-steps" "$STAGE_OPT_MAX_STEPS" "--temperature" "$STAGE_OPT_TEMPERATURE") + + if [[ -n "$STAGE_OPT_STAGES" ]]; then + read -r -a stage_list <<< "$STAGE_OPT_STAGES" + if [[ ${#stage_list[@]} -gt 0 ]]; then + cmd+=("--stages") + for stage_name in "${stage_list[@]}"; do + cmd+=("$stage_name") + done + fi + fi + + if [[ "$STAGE_OPT_DRY_RUN" -eq 1 ]]; then + cmd+=("--dry-run") + fi + + echo "Running stage_optimize.py: ${cmd[*]}" + "${cmd[@]}" +} + +run_stage_override() { + if [[ ${#OVERRIDE_FILES[@]} -eq 0 && ${#OVERRIDE_PARAMS[@]} -eq 0 ]]; then + echo "Error: --run-stage-override requires at least one --override-file or --override-param." + exit 1 + fi + + local cmd=(python3 stage_override.py "$platform" "$design" "$objective" "--max-react-steps" "$STAGE_OVERRIDE_MAX_STEPS" "--temperature" "$STAGE_OVERRIDE_TEMPERATURE") + + if [[ -n "$STAGE_OVERRIDE_STAGES" ]]; then + read -r -a override_stage_list <<< "$STAGE_OVERRIDE_STAGES" + if [[ ${#override_stage_list[@]} -gt 0 ]]; then + cmd+=("--stages") + for stage_name in "${override_stage_list[@]}"; do + cmd+=("$stage_name") + done + fi + fi + + for override_file in "${OVERRIDE_FILES[@]}"; do + cmd+=("--overrides-file" "$override_file") + done + + for override_param in "${OVERRIDE_PARAMS[@]}"; do + cmd+=("--override" "$override_param") + done + + if [[ "$STAGE_OVERRIDE_DRY_RUN" -eq 1 ]]; then + cmd+=("--dry-run") + fi + + echo "Running stage_override.py: ${cmd[*]}" + "${cmd[@]}" +} + +# Main iteration loop +for i in $(seq 1 $TOTAL_ITERS); do + echo "Starting iteration $i of $TOTAL_ITERS" + + # Run sequential phase + # echo '"$platform" "$design" "$PARALLEL_RUNS" "$i"' + echo "${platform}, ${design}, ${PARALLEL_RUNS}, ${i}" + ./run_sequential.sh "$platform" "$design" "$PARALLEL_RUNS" "$i" + echo "./run_sequential.sh \"$platform\" \"$design\" \"$PARALLEL_RUNS\" \"$i\"" + + # Run parallel phase with timeout + timeout "$TIMEOUT" ./run_parallel.sh "$platform" "$design" "$PARALLEL_RUNS" || true + + # Kill any remaining parallel jobs + pkill -P $$ || true + + # Create backup of this iteration's results + create_backup "$platform" "$design" "$i" + + # Generate constraints for next iteration (skip for last iteration) + if [ "$i" -lt "$TOTAL_ITERS" ]; then + # for objective in "$objective"; do + # echo "Running optimization for $objective" + # python3 stage_optimize.py "$platform" "$design" "$objective" --max-react-steps 3 + # cp -r results/ results_${platform}_${design}_${objective}/ + # done + echo "Running optimization for next iteration..." + + if [[ "$RUN_STAGE_OVERRIDE" -eq 1 ]]; then + echo "Applying explicit stage overrides before next iteration..." + run_stage_override + fi + + if [[ "$RUN_STAGE_OPTIMIZE" -eq 1 ]]; then + echo "Requesting stage-level recommendations..." + run_stage_optimize + fi + + # python3 optimize.py "$platform" "$design" "$objective" "$PARALLEL_RUNS" + # python3 optimize_rag.py "$platform" "$design" "$objective" "$PARALLEL_RUNS" + # python3 optimize_react.py "$platform" "$design" "$objective" "$PARALLEL_RUNS" + # python3 optimize_raw.py "$platform" "$design" "$objective" "$PARALLEL_RUNS" + if [[ "$RUN_OPTIMIZE" -eq 1 ]]; then + echo "Running optimize_dual.py for additional refinement..." + python3 optimize_dual.py "$platform" "$design" "$objective" "$PARALLEL_RUNS" + fi + fi +done + +echo "All iterations complete" diff --git a/flow-Agent/models/mxbai-embed-large-v1/1_Pooling/config.json b/flow-Agent/models/mxbai-embed-large-v1/1_Pooling/config.json new file mode 100644 index 0000000..553a16b --- /dev/null +++ b/flow-Agent/models/mxbai-embed-large-v1/1_Pooling/config.json @@ -0,0 +1,10 @@ +{ + "word_embedding_dimension": 1024, + "pooling_mode_cls_token": true, + "pooling_mode_mean_tokens": false, + "pooling_mode_max_tokens": false, + "pooling_mode_mean_sqrt_len_tokens": false, + "pooling_mode_weightedmean_tokens": false, + "pooling_mode_lasttoken": false, + "include_prompt": true +} \ No newline at end of file diff --git a/flow-Agent/models/mxbai-embed-large-v1/LICENSE b/flow-Agent/models/mxbai-embed-large-v1/LICENSE new file mode 100644 index 0000000..0836af1 --- /dev/null +++ b/flow-Agent/models/mxbai-embed-large-v1/LICENSE @@ -0,0 +1,190 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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task: + type: Classification + dataset: + type: mteb/amazon_counterfactual + name: MTEB AmazonCounterfactualClassification (en) + config: en + split: test + revision: e8379541af4e31359cca9fbcf4b00f2671dba205 + metrics: + - type: accuracy + value: 75.044776119403 + - type: ap + value: 37.7362433623053 + - type: f1 + value: 68.92736573359774 + - task: + type: Classification + dataset: + type: mteb/amazon_polarity + name: MTEB AmazonPolarityClassification + config: default + split: test + revision: e2d317d38cd51312af73b3d32a06d1a08b442046 + metrics: + - type: accuracy + value: 93.84025000000001 + - type: ap + value: 90.93190875404055 + - type: f1 + value: 93.8297833897293 + - task: + type: Classification + dataset: + type: mteb/amazon_reviews_multi + name: MTEB AmazonReviewsClassification (en) + config: en + split: test + revision: 1399c76144fd37290681b995c656ef9b2e06e26d + metrics: + - type: accuracy + value: 49.184 + - type: f1 + value: 48.74163227751588 + - task: + type: Retrieval + dataset: + type: arguana + name: MTEB ArguAna + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 41.252 + - type: map_at_10 + value: 57.778 + - type: map_at_100 + value: 58.233000000000004 + - type: map_at_1000 + value: 58.23700000000001 + - type: map_at_3 + value: 53.449999999999996 + - type: map_at_5 + value: 56.376000000000005 + - type: mrr_at_1 + value: 41.679 + - type: mrr_at_10 + value: 57.92699999999999 + - type: mrr_at_100 + value: 58.389 + - type: mrr_at_1000 + value: 58.391999999999996 + - type: mrr_at_3 + value: 53.651 + - type: mrr_at_5 + value: 56.521 + - type: ndcg_at_1 + value: 41.252 + - type: ndcg_at_10 + value: 66.018 + - type: ndcg_at_100 + value: 67.774 + - type: ndcg_at_1000 + value: 67.84400000000001 + - type: ndcg_at_3 + value: 57.372 + - type: ndcg_at_5 + value: 62.646 + - type: precision_at_1 + value: 41.252 + - type: precision_at_10 + value: 9.189 + - type: precision_at_100 + value: 0.991 + - type: precision_at_1000 + value: 0.1 + - type: precision_at_3 + value: 22.902 + - type: precision_at_5 + value: 16.302 + - type: recall_at_1 + value: 41.252 + - type: recall_at_10 + value: 91.892 + - type: recall_at_100 + value: 99.14699999999999 + - type: recall_at_1000 + value: 99.644 + - type: recall_at_3 + value: 68.706 + - type: recall_at_5 + value: 81.50800000000001 + - task: + type: Clustering + dataset: + type: mteb/arxiv-clustering-p2p + name: MTEB ArxivClusteringP2P + config: default + split: test + revision: a122ad7f3f0291bf49cc6f4d32aa80929df69d5d + metrics: + - type: v_measure + value: 48.97294504317859 + - task: + type: Clustering + dataset: + type: mteb/arxiv-clustering-s2s + name: MTEB ArxivClusteringS2S + config: default + split: test + revision: f910caf1a6075f7329cdf8c1a6135696f37dbd53 + metrics: + - type: v_measure + value: 42.98071077674629 + - task: + type: Reranking + dataset: + type: mteb/askubuntudupquestions-reranking + name: MTEB AskUbuntuDupQuestions + config: default + split: test + revision: 2000358ca161889fa9c082cb41daa8dcfb161a54 + metrics: + - type: map + value: 65.16477858490782 + - type: mrr + value: 78.23583080508287 + - task: + type: STS + dataset: + type: mteb/biosses-sts + name: MTEB BIOSSES + config: default + split: test + revision: d3fb88f8f02e40887cd149695127462bbcf29b4a + metrics: + - type: cos_sim_pearson + value: 89.6277629421789 + - type: cos_sim_spearman + value: 88.4056288400568 + - type: euclidean_pearson + value: 87.94871847578163 + - type: euclidean_spearman + value: 88.4056288400568 + - type: manhattan_pearson + value: 87.73271254229648 + - type: manhattan_spearman + value: 87.91826833762677 + - task: + type: Classification + dataset: + type: mteb/banking77 + name: MTEB Banking77Classification + config: default + split: test + revision: 0fd18e25b25c072e09e0d92ab615fda904d66300 + metrics: + - type: accuracy + value: 87.81818181818181 + - type: f1 + value: 87.79879337316918 + - task: + type: Clustering + dataset: + type: mteb/biorxiv-clustering-p2p + name: MTEB BiorxivClusteringP2P + config: default + split: test + revision: 65b79d1d13f80053f67aca9498d9402c2d9f1f40 + metrics: + - type: v_measure + value: 39.91773608582761 + - task: + type: Clustering + dataset: + type: mteb/biorxiv-clustering-s2s + name: MTEB BiorxivClusteringS2S + config: default + split: test + revision: 258694dd0231531bc1fd9de6ceb52a0853c6d908 + metrics: + - type: v_measure + value: 36.73059477462478 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackAndroidRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 32.745999999999995 + - type: map_at_10 + value: 43.632 + - type: map_at_100 + value: 45.206 + - type: map_at_1000 + value: 45.341 + - type: map_at_3 + value: 39.956 + - type: map_at_5 + value: 42.031 + - type: mrr_at_1 + value: 39.485 + - type: mrr_at_10 + value: 49.537 + - type: mrr_at_100 + value: 50.249 + - type: mrr_at_1000 + value: 50.294000000000004 + - type: mrr_at_3 + value: 46.757 + - type: mrr_at_5 + value: 48.481 + - type: ndcg_at_1 + value: 39.485 + - type: ndcg_at_10 + value: 50.058 + - type: ndcg_at_100 + value: 55.586 + - type: ndcg_at_1000 + value: 57.511 + - type: ndcg_at_3 + value: 44.786 + - type: ndcg_at_5 + value: 47.339999999999996 + - type: precision_at_1 + value: 39.485 + - type: precision_at_10 + value: 9.557 + - type: precision_at_100 + value: 1.552 + - type: precision_at_1000 + value: 0.202 + - type: precision_at_3 + value: 21.412 + - type: precision_at_5 + value: 15.479000000000001 + - type: recall_at_1 + value: 32.745999999999995 + - type: recall_at_10 + value: 62.056 + - type: recall_at_100 + value: 85.088 + - type: recall_at_1000 + value: 96.952 + - type: recall_at_3 + value: 46.959 + - type: recall_at_5 + value: 54.06999999999999 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackEnglishRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 31.898 + - type: map_at_10 + value: 42.142 + - type: map_at_100 + value: 43.349 + - type: map_at_1000 + value: 43.483 + - type: map_at_3 + value: 39.18 + - type: map_at_5 + value: 40.733000000000004 + - type: mrr_at_1 + value: 39.617999999999995 + - type: mrr_at_10 + value: 47.922 + - type: mrr_at_100 + value: 48.547000000000004 + - type: mrr_at_1000 + value: 48.597 + - type: mrr_at_3 + value: 45.86 + - type: mrr_at_5 + value: 46.949000000000005 + - type: ndcg_at_1 + value: 39.617999999999995 + - type: ndcg_at_10 + value: 47.739 + - type: ndcg_at_100 + value: 51.934999999999995 + - type: ndcg_at_1000 + value: 54.007000000000005 + - type: ndcg_at_3 + value: 43.748 + - type: ndcg_at_5 + value: 45.345 + - type: precision_at_1 + value: 39.617999999999995 + - type: precision_at_10 + value: 8.962 + - type: precision_at_100 + value: 1.436 + - type: precision_at_1000 + value: 0.192 + - type: precision_at_3 + value: 21.083 + - type: precision_at_5 + value: 14.752 + - type: recall_at_1 + value: 31.898 + - type: recall_at_10 + value: 57.587999999999994 + - type: recall_at_100 + value: 75.323 + - type: recall_at_1000 + value: 88.304 + - type: recall_at_3 + value: 45.275 + - type: recall_at_5 + value: 49.99 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackGamingRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 40.458 + - type: map_at_10 + value: 52.942 + - type: map_at_100 + value: 53.974 + - type: map_at_1000 + value: 54.031 + - type: map_at_3 + value: 49.559999999999995 + - type: map_at_5 + value: 51.408 + - type: mrr_at_1 + value: 46.27 + - type: mrr_at_10 + value: 56.31699999999999 + - type: mrr_at_100 + value: 56.95099999999999 + - type: mrr_at_1000 + value: 56.98 + - type: mrr_at_3 + value: 53.835 + - type: mrr_at_5 + value: 55.252 + - type: ndcg_at_1 + value: 46.27 + - type: ndcg_at_10 + value: 58.964000000000006 + - type: ndcg_at_100 + value: 62.875 + - type: ndcg_at_1000 + value: 63.969 + - type: ndcg_at_3 + value: 53.297000000000004 + - type: ndcg_at_5 + value: 55.938 + - type: precision_at_1 + value: 46.27 + - type: precision_at_10 + value: 9.549000000000001 + - type: precision_at_100 + value: 1.2409999999999999 + - type: precision_at_1000 + value: 0.13799999999999998 + - type: precision_at_3 + value: 23.762 + - type: precision_at_5 + value: 16.262999999999998 + - type: recall_at_1 + value: 40.458 + - type: recall_at_10 + value: 73.446 + - type: recall_at_100 + value: 90.12400000000001 + - type: recall_at_1000 + value: 97.795 + - type: recall_at_3 + value: 58.123000000000005 + - type: recall_at_5 + value: 64.68 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackGisRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 27.443 + - type: map_at_10 + value: 36.081 + - type: map_at_100 + value: 37.163000000000004 + - type: map_at_1000 + value: 37.232 + - type: map_at_3 + value: 33.308 + - type: map_at_5 + value: 34.724 + - type: mrr_at_1 + value: 29.492 + - type: mrr_at_10 + value: 38.138 + - type: mrr_at_100 + value: 39.065 + - type: mrr_at_1000 + value: 39.119 + - type: mrr_at_3 + value: 35.593 + - type: mrr_at_5 + value: 36.785000000000004 + - type: ndcg_at_1 + value: 29.492 + - type: ndcg_at_10 + value: 41.134 + - type: ndcg_at_100 + value: 46.300999999999995 + - type: ndcg_at_1000 + value: 48.106 + - type: ndcg_at_3 + value: 35.77 + - type: ndcg_at_5 + value: 38.032 + - type: precision_at_1 + value: 29.492 + - type: precision_at_10 + value: 6.249 + - type: precision_at_100 + value: 0.9299999999999999 + - type: precision_at_1000 + value: 0.11199999999999999 + - type: precision_at_3 + value: 15.065999999999999 + - type: precision_at_5 + value: 10.373000000000001 + - type: recall_at_1 + value: 27.443 + - type: recall_at_10 + value: 54.80199999999999 + - type: recall_at_100 + value: 78.21900000000001 + - type: recall_at_1000 + value: 91.751 + - type: recall_at_3 + value: 40.211000000000006 + - type: recall_at_5 + value: 45.599000000000004 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackMathematicaRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 18.731 + - type: map_at_10 + value: 26.717999999999996 + - type: map_at_100 + value: 27.897 + - type: map_at_1000 + value: 28.029 + - type: map_at_3 + value: 23.91 + - type: map_at_5 + value: 25.455 + - type: mrr_at_1 + value: 23.134 + - type: mrr_at_10 + value: 31.769 + - type: mrr_at_100 + value: 32.634 + - type: mrr_at_1000 + value: 32.707 + - type: mrr_at_3 + value: 28.938999999999997 + - type: mrr_at_5 + value: 30.531000000000002 + - type: ndcg_at_1 + value: 23.134 + - type: ndcg_at_10 + value: 32.249 + - type: ndcg_at_100 + value: 37.678 + - type: ndcg_at_1000 + value: 40.589999999999996 + - type: ndcg_at_3 + value: 26.985999999999997 + - type: ndcg_at_5 + value: 29.457 + - type: precision_at_1 + value: 23.134 + - type: precision_at_10 + value: 5.8709999999999996 + - type: precision_at_100 + value: 0.988 + - type: precision_at_1000 + value: 0.13799999999999998 + - type: precision_at_3 + value: 12.852 + - type: precision_at_5 + value: 9.428 + - type: recall_at_1 + value: 18.731 + - type: recall_at_10 + value: 44.419 + - type: recall_at_100 + value: 67.851 + - type: recall_at_1000 + value: 88.103 + - type: recall_at_3 + value: 29.919 + - type: recall_at_5 + value: 36.230000000000004 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackPhysicsRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 30.324 + - type: map_at_10 + value: 41.265 + - type: map_at_100 + value: 42.559000000000005 + - type: map_at_1000 + value: 42.669000000000004 + - type: map_at_3 + value: 38.138 + - type: map_at_5 + value: 39.881 + - type: mrr_at_1 + value: 36.67 + - type: mrr_at_10 + value: 46.774 + - type: mrr_at_100 + value: 47.554 + - type: mrr_at_1000 + value: 47.593 + - type: mrr_at_3 + value: 44.338 + - type: mrr_at_5 + value: 45.723 + - type: ndcg_at_1 + value: 36.67 + - type: ndcg_at_10 + value: 47.367 + - type: ndcg_at_100 + value: 52.623 + - type: ndcg_at_1000 + value: 54.59 + - type: ndcg_at_3 + value: 42.323 + - type: ndcg_at_5 + value: 44.727 + - type: precision_at_1 + value: 36.67 + - type: precision_at_10 + value: 8.518 + - type: precision_at_100 + value: 1.2890000000000001 + - type: precision_at_1000 + value: 0.163 + - type: precision_at_3 + value: 19.955000000000002 + - type: precision_at_5 + value: 14.11 + - type: recall_at_1 + value: 30.324 + - type: recall_at_10 + value: 59.845000000000006 + - type: recall_at_100 + value: 81.77499999999999 + - type: recall_at_1000 + value: 94.463 + - type: recall_at_3 + value: 46.019 + - type: recall_at_5 + value: 52.163000000000004 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackProgrammersRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 24.229 + - type: map_at_10 + value: 35.004000000000005 + - type: map_at_100 + value: 36.409000000000006 + - type: map_at_1000 + value: 36.521 + - type: map_at_3 + value: 31.793 + - type: map_at_5 + value: 33.432 + - type: mrr_at_1 + value: 30.365 + - type: mrr_at_10 + value: 40.502 + - type: mrr_at_100 + value: 41.372 + - type: mrr_at_1000 + value: 41.435 + - type: mrr_at_3 + value: 37.804 + - type: mrr_at_5 + value: 39.226 + - type: ndcg_at_1 + value: 30.365 + - type: ndcg_at_10 + value: 41.305 + - type: ndcg_at_100 + value: 47.028999999999996 + - type: ndcg_at_1000 + value: 49.375 + - type: ndcg_at_3 + value: 35.85 + - type: ndcg_at_5 + value: 38.12 + - type: precision_at_1 + value: 30.365 + - type: precision_at_10 + value: 7.808 + - type: precision_at_100 + value: 1.228 + - type: precision_at_1000 + value: 0.161 + - type: precision_at_3 + value: 17.352 + - type: precision_at_5 + value: 12.42 + - type: recall_at_1 + value: 24.229 + - type: recall_at_10 + value: 54.673 + - type: recall_at_100 + value: 78.766 + - type: recall_at_1000 + value: 94.625 + - type: recall_at_3 + value: 39.602 + - type: recall_at_5 + value: 45.558 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 26.695 + - type: map_at_10 + value: 36.0895 + - type: map_at_100 + value: 37.309416666666664 + - type: map_at_1000 + value: 37.42558333333334 + - type: map_at_3 + value: 33.19616666666666 + - type: map_at_5 + value: 34.78641666666667 + - type: mrr_at_1 + value: 31.486083333333337 + - type: mrr_at_10 + value: 40.34774999999999 + - type: mrr_at_100 + value: 41.17533333333333 + - type: mrr_at_1000 + value: 41.231583333333326 + - type: mrr_at_3 + value: 37.90075 + - type: mrr_at_5 + value: 39.266999999999996 + - type: ndcg_at_1 + value: 31.486083333333337 + - type: ndcg_at_10 + value: 41.60433333333334 + - type: ndcg_at_100 + value: 46.74525 + - type: ndcg_at_1000 + value: 48.96166666666667 + - type: ndcg_at_3 + value: 36.68825 + - type: ndcg_at_5 + value: 38.966499999999996 + - type: precision_at_1 + value: 31.486083333333337 + - type: precision_at_10 + value: 7.29675 + - type: precision_at_100 + value: 1.1621666666666666 + - type: precision_at_1000 + value: 0.1545 + - type: precision_at_3 + value: 16.8815 + - type: precision_at_5 + value: 11.974583333333333 + - type: recall_at_1 + value: 26.695 + - type: recall_at_10 + value: 53.651916666666665 + - type: recall_at_100 + value: 76.12083333333332 + - type: recall_at_1000 + value: 91.31191666666668 + - type: recall_at_3 + value: 40.03575 + - type: recall_at_5 + value: 45.876666666666665 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackStatsRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 25.668000000000003 + - type: map_at_10 + value: 32.486 + - type: map_at_100 + value: 33.371 + - type: map_at_1000 + value: 33.458 + - type: map_at_3 + value: 30.261 + - type: map_at_5 + value: 31.418000000000003 + - type: mrr_at_1 + value: 28.988000000000003 + - type: mrr_at_10 + value: 35.414 + - type: mrr_at_100 + value: 36.149 + - type: mrr_at_1000 + value: 36.215 + - type: mrr_at_3 + value: 33.333 + - type: mrr_at_5 + value: 34.43 + - type: ndcg_at_1 + value: 28.988000000000003 + - type: ndcg_at_10 + value: 36.732 + - type: ndcg_at_100 + value: 41.331 + - type: ndcg_at_1000 + value: 43.575 + - type: ndcg_at_3 + value: 32.413 + - type: ndcg_at_5 + value: 34.316 + - type: precision_at_1 + value: 28.988000000000003 + - type: precision_at_10 + value: 5.7059999999999995 + - type: precision_at_100 + value: 0.882 + - type: precision_at_1000 + value: 0.11299999999999999 + - type: precision_at_3 + value: 13.65 + - type: precision_at_5 + value: 9.417 + - type: recall_at_1 + value: 25.668000000000003 + - type: recall_at_10 + value: 47.147 + - type: recall_at_100 + value: 68.504 + - type: recall_at_1000 + value: 85.272 + - type: recall_at_3 + value: 35.19 + - type: recall_at_5 + value: 39.925 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackTexRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 17.256 + - type: map_at_10 + value: 24.58 + - type: map_at_100 + value: 25.773000000000003 + - type: map_at_1000 + value: 25.899 + - type: map_at_3 + value: 22.236 + - type: map_at_5 + value: 23.507 + - type: mrr_at_1 + value: 20.957 + - type: mrr_at_10 + value: 28.416000000000004 + - type: mrr_at_100 + value: 29.447000000000003 + - type: mrr_at_1000 + value: 29.524 + - type: mrr_at_3 + value: 26.245 + - type: mrr_at_5 + value: 27.451999999999998 + - type: ndcg_at_1 + value: 20.957 + - type: ndcg_at_10 + value: 29.285 + - type: ndcg_at_100 + value: 35.003 + - type: ndcg_at_1000 + value: 37.881 + - type: ndcg_at_3 + value: 25.063000000000002 + - type: ndcg_at_5 + value: 26.983 + - type: precision_at_1 + value: 20.957 + - type: precision_at_10 + value: 5.344 + - type: precision_at_100 + value: 0.958 + - type: precision_at_1000 + value: 0.13799999999999998 + - type: precision_at_3 + value: 11.918 + - type: precision_at_5 + value: 8.596 + - type: recall_at_1 + value: 17.256 + - type: recall_at_10 + value: 39.644 + - type: recall_at_100 + value: 65.279 + - type: recall_at_1000 + value: 85.693 + - type: recall_at_3 + value: 27.825 + - type: recall_at_5 + value: 32.792 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackUnixRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 26.700000000000003 + - type: map_at_10 + value: 36.205999999999996 + - type: map_at_100 + value: 37.316 + - type: map_at_1000 + value: 37.425000000000004 + - type: map_at_3 + value: 33.166000000000004 + - type: map_at_5 + value: 35.032999999999994 + - type: mrr_at_1 + value: 31.436999999999998 + - type: mrr_at_10 + value: 40.61 + - type: mrr_at_100 + value: 41.415 + - type: mrr_at_1000 + value: 41.48 + - type: mrr_at_3 + value: 37.966 + - type: mrr_at_5 + value: 39.599000000000004 + - type: ndcg_at_1 + value: 31.436999999999998 + - type: ndcg_at_10 + value: 41.771 + - type: ndcg_at_100 + value: 46.784 + - type: ndcg_at_1000 + value: 49.183 + - type: ndcg_at_3 + value: 36.437000000000005 + - type: ndcg_at_5 + value: 39.291 + - type: precision_at_1 + value: 31.436999999999998 + - type: precision_at_10 + value: 6.987 + - type: precision_at_100 + value: 1.072 + - type: precision_at_1000 + value: 0.13899999999999998 + - type: precision_at_3 + value: 16.448999999999998 + - type: precision_at_5 + value: 11.866 + - type: recall_at_1 + value: 26.700000000000003 + - type: recall_at_10 + value: 54.301 + - type: recall_at_100 + value: 75.871 + - type: recall_at_1000 + value: 92.529 + - type: recall_at_3 + value: 40.201 + - type: recall_at_5 + value: 47.208 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackWebmastersRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 24.296 + - type: map_at_10 + value: 33.116 + - type: map_at_100 + value: 34.81 + - type: map_at_1000 + value: 35.032000000000004 + - type: map_at_3 + value: 30.105999999999998 + - type: map_at_5 + value: 31.839000000000002 + - type: mrr_at_1 + value: 29.051 + - type: mrr_at_10 + value: 37.803 + - type: mrr_at_100 + value: 38.856 + - type: mrr_at_1000 + value: 38.903999999999996 + - type: mrr_at_3 + value: 35.211 + - type: mrr_at_5 + value: 36.545 + - type: ndcg_at_1 + value: 29.051 + - type: ndcg_at_10 + value: 39.007 + - type: ndcg_at_100 + value: 45.321 + - type: ndcg_at_1000 + value: 47.665 + - type: ndcg_at_3 + value: 34.1 + - type: ndcg_at_5 + value: 36.437000000000005 + - type: precision_at_1 + value: 29.051 + - type: precision_at_10 + value: 7.668 + - type: precision_at_100 + value: 1.542 + - type: precision_at_1000 + value: 0.24 + - type: precision_at_3 + value: 16.14 + - type: precision_at_5 + value: 11.897 + - type: recall_at_1 + value: 24.296 + - type: recall_at_10 + value: 49.85 + - type: recall_at_100 + value: 78.457 + - type: recall_at_1000 + value: 92.618 + - type: recall_at_3 + value: 36.138999999999996 + - type: recall_at_5 + value: 42.223 + - task: + type: Retrieval + dataset: + type: BeIR/cqadupstack + name: MTEB CQADupstackWordpressRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 20.591 + - type: map_at_10 + value: 28.902 + - type: map_at_100 + value: 29.886000000000003 + - type: map_at_1000 + value: 29.987000000000002 + - type: map_at_3 + value: 26.740000000000002 + - type: map_at_5 + value: 27.976 + - type: mrr_at_1 + value: 22.366 + - type: mrr_at_10 + value: 30.971 + - type: mrr_at_100 + value: 31.865 + - type: mrr_at_1000 + value: 31.930999999999997 + - type: mrr_at_3 + value: 28.927999999999997 + - type: mrr_at_5 + value: 30.231 + - type: ndcg_at_1 + value: 22.366 + - type: ndcg_at_10 + value: 33.641 + - type: ndcg_at_100 + value: 38.477 + - type: ndcg_at_1000 + value: 41.088 + - type: ndcg_at_3 + value: 29.486 + - type: ndcg_at_5 + value: 31.612000000000002 + - type: precision_at_1 + value: 22.366 + - type: precision_at_10 + value: 5.3420000000000005 + - type: precision_at_100 + value: 0.828 + - type: precision_at_1000 + value: 0.11800000000000001 + - type: precision_at_3 + value: 12.939 + - type: precision_at_5 + value: 9.094 + - type: recall_at_1 + value: 20.591 + - type: recall_at_10 + value: 46.052 + - type: recall_at_100 + value: 68.193 + - type: recall_at_1000 + value: 87.638 + - type: recall_at_3 + value: 34.966 + - type: recall_at_5 + value: 40.082 + - task: + type: Retrieval + dataset: + type: climate-fever + name: MTEB ClimateFEVER + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 15.091 + - type: map_at_10 + value: 26.38 + - type: map_at_100 + value: 28.421999999999997 + - type: map_at_1000 + value: 28.621999999999996 + - type: map_at_3 + value: 21.597 + - type: map_at_5 + value: 24.12 + - type: mrr_at_1 + value: 34.266999999999996 + - type: mrr_at_10 + value: 46.864 + - type: mrr_at_100 + value: 47.617 + - type: mrr_at_1000 + value: 47.644 + - type: mrr_at_3 + value: 43.312 + - type: mrr_at_5 + value: 45.501000000000005 + - type: ndcg_at_1 + value: 34.266999999999996 + - type: ndcg_at_10 + value: 36.095 + - type: ndcg_at_100 + value: 43.447 + - type: ndcg_at_1000 + value: 46.661 + - type: ndcg_at_3 + value: 29.337999999999997 + - type: ndcg_at_5 + value: 31.824 + - type: precision_at_1 + value: 34.266999999999996 + - type: precision_at_10 + value: 11.472 + - type: precision_at_100 + value: 1.944 + - type: precision_at_1000 + value: 0.255 + - type: precision_at_3 + value: 21.933 + - type: precision_at_5 + value: 17.224999999999998 + - type: recall_at_1 + value: 15.091 + - type: recall_at_10 + value: 43.022 + - type: recall_at_100 + value: 68.075 + - type: recall_at_1000 + value: 85.76 + - type: recall_at_3 + value: 26.564 + - type: recall_at_5 + value: 33.594 + - task: + type: Retrieval + dataset: + type: dbpedia-entity + name: MTEB DBPedia + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 9.252 + - type: map_at_10 + value: 20.923 + - type: map_at_100 + value: 30.741000000000003 + - type: map_at_1000 + value: 32.542 + - type: map_at_3 + value: 14.442 + - type: map_at_5 + value: 17.399 + - type: mrr_at_1 + value: 70.25 + - type: mrr_at_10 + value: 78.17 + - type: mrr_at_100 + value: 78.444 + - type: mrr_at_1000 + value: 78.45100000000001 + - type: mrr_at_3 + value: 76.958 + - type: mrr_at_5 + value: 77.571 + - type: ndcg_at_1 + value: 58.375 + - type: ndcg_at_10 + value: 44.509 + - type: ndcg_at_100 + value: 49.897999999999996 + - type: ndcg_at_1000 + value: 57.269999999999996 + - type: ndcg_at_3 + value: 48.64 + - type: ndcg_at_5 + value: 46.697 + - type: precision_at_1 + value: 70.25 + - type: precision_at_10 + value: 36.05 + - type: precision_at_100 + value: 11.848 + - type: precision_at_1000 + value: 2.213 + - type: precision_at_3 + value: 52.917 + - type: precision_at_5 + value: 45.7 + - type: recall_at_1 + value: 9.252 + - type: recall_at_10 + value: 27.006999999999998 + - type: recall_at_100 + value: 57.008 + - type: recall_at_1000 + value: 80.697 + - type: recall_at_3 + value: 15.798000000000002 + - type: recall_at_5 + value: 20.4 + - task: + type: Classification + dataset: + type: mteb/emotion + name: MTEB EmotionClassification + config: default + split: test + revision: 4f58c6b202a23cf9a4da393831edf4f9183cad37 + metrics: + - type: accuracy + value: 50.88 + - type: f1 + value: 45.545495028653384 + - task: + type: Retrieval + dataset: + type: fever + name: MTEB FEVER + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 75.424 + - type: map_at_10 + value: 83.435 + - type: map_at_100 + value: 83.66900000000001 + - type: map_at_1000 + value: 83.685 + - type: map_at_3 + value: 82.39800000000001 + - type: map_at_5 + value: 83.07 + - type: mrr_at_1 + value: 81.113 + - type: mrr_at_10 + value: 87.77199999999999 + - type: mrr_at_100 + value: 87.862 + - type: mrr_at_1000 + value: 87.86500000000001 + - type: mrr_at_3 + value: 87.17099999999999 + - type: mrr_at_5 + value: 87.616 + - type: ndcg_at_1 + value: 81.113 + - type: ndcg_at_10 + value: 86.909 + - type: ndcg_at_100 + value: 87.746 + - type: ndcg_at_1000 + value: 88.017 + - type: ndcg_at_3 + value: 85.368 + - type: ndcg_at_5 + value: 86.28099999999999 + - type: precision_at_1 + value: 81.113 + - type: precision_at_10 + value: 10.363 + - type: precision_at_100 + value: 1.102 + - type: precision_at_1000 + value: 0.11399999999999999 + - type: precision_at_3 + value: 32.507999999999996 + - type: precision_at_5 + value: 20.138 + - type: recall_at_1 + value: 75.424 + - type: recall_at_10 + value: 93.258 + - type: recall_at_100 + value: 96.545 + - type: recall_at_1000 + value: 98.284 + - type: recall_at_3 + value: 89.083 + - type: recall_at_5 + value: 91.445 + - task: + type: Retrieval + dataset: + type: fiqa + name: MTEB FiQA2018 + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 22.532 + - type: map_at_10 + value: 37.141999999999996 + - type: map_at_100 + value: 39.162 + - type: map_at_1000 + value: 39.322 + - type: map_at_3 + value: 32.885 + - type: map_at_5 + value: 35.093999999999994 + - type: mrr_at_1 + value: 44.29 + - type: mrr_at_10 + value: 53.516 + - type: mrr_at_100 + value: 54.24 + - type: mrr_at_1000 + value: 54.273 + - type: mrr_at_3 + value: 51.286 + - type: mrr_at_5 + value: 52.413 + - type: ndcg_at_1 + value: 44.29 + - type: ndcg_at_10 + value: 45.268 + - type: ndcg_at_100 + value: 52.125 + - type: ndcg_at_1000 + value: 54.778000000000006 + - type: ndcg_at_3 + value: 41.829 + - type: ndcg_at_5 + value: 42.525 + - type: precision_at_1 + value: 44.29 + - type: precision_at_10 + value: 12.5 + - type: precision_at_100 + value: 1.9720000000000002 + - type: precision_at_1000 + value: 0.245 + - type: precision_at_3 + value: 28.035 + - type: precision_at_5 + value: 20.093 + - type: recall_at_1 + value: 22.532 + - type: recall_at_10 + value: 52.419000000000004 + - type: recall_at_100 + value: 77.43299999999999 + - type: recall_at_1000 + value: 93.379 + - type: recall_at_3 + value: 38.629000000000005 + - type: recall_at_5 + value: 43.858000000000004 + - task: + type: Retrieval + dataset: + type: hotpotqa + name: MTEB HotpotQA + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 39.359 + - type: map_at_10 + value: 63.966 + - type: map_at_100 + value: 64.87 + - type: map_at_1000 + value: 64.92599999999999 + - type: map_at_3 + value: 60.409 + - type: map_at_5 + value: 62.627 + - type: mrr_at_1 + value: 78.717 + - type: mrr_at_10 + value: 84.468 + - type: mrr_at_100 + value: 84.655 + - type: mrr_at_1000 + value: 84.661 + - type: mrr_at_3 + value: 83.554 + - type: mrr_at_5 + value: 84.133 + - type: ndcg_at_1 + value: 78.717 + - type: ndcg_at_10 + value: 72.03399999999999 + - type: ndcg_at_100 + value: 75.158 + - type: ndcg_at_1000 + value: 76.197 + - type: ndcg_at_3 + value: 67.049 + - type: ndcg_at_5 + value: 69.808 + - type: precision_at_1 + value: 78.717 + - type: precision_at_10 + value: 15.201 + - type: precision_at_100 + value: 1.764 + - type: precision_at_1000 + value: 0.19 + - type: precision_at_3 + value: 43.313 + - type: precision_at_5 + value: 28.165000000000003 + - type: recall_at_1 + value: 39.359 + - type: recall_at_10 + value: 76.003 + - type: recall_at_100 + value: 88.197 + - type: recall_at_1000 + value: 95.003 + - type: recall_at_3 + value: 64.97 + - type: recall_at_5 + value: 70.41199999999999 + - task: + type: Classification + dataset: + type: mteb/imdb + name: MTEB ImdbClassification + config: default + split: test + revision: 3d86128a09e091d6018b6d26cad27f2739fc2db7 + metrics: + - type: accuracy + value: 92.83200000000001 + - type: ap + value: 89.33560571859861 + - type: f1 + value: 92.82322915005167 + - task: + type: Retrieval + dataset: + type: msmarco + name: MTEB MSMARCO + config: default + split: dev + revision: None + metrics: + - type: map_at_1 + value: 21.983 + - type: map_at_10 + value: 34.259 + - type: map_at_100 + value: 35.432 + - type: map_at_1000 + value: 35.482 + - type: map_at_3 + value: 30.275999999999996 + - type: map_at_5 + value: 32.566 + - type: mrr_at_1 + value: 22.579 + - type: mrr_at_10 + value: 34.882999999999996 + - type: mrr_at_100 + value: 35.984 + - type: mrr_at_1000 + value: 36.028 + - type: mrr_at_3 + value: 30.964999999999996 + - type: mrr_at_5 + value: 33.245000000000005 + - type: ndcg_at_1 + value: 22.564 + - type: ndcg_at_10 + value: 41.258 + - type: ndcg_at_100 + value: 46.824 + - type: ndcg_at_1000 + value: 48.037 + - type: ndcg_at_3 + value: 33.17 + - type: ndcg_at_5 + value: 37.263000000000005 + - type: precision_at_1 + value: 22.564 + - type: precision_at_10 + value: 6.572 + - type: precision_at_100 + value: 0.935 + - type: precision_at_1000 + value: 0.104 + - type: precision_at_3 + value: 14.130999999999998 + - type: precision_at_5 + value: 10.544 + - type: recall_at_1 + value: 21.983 + - type: recall_at_10 + value: 62.775000000000006 + - type: recall_at_100 + value: 88.389 + - type: recall_at_1000 + value: 97.603 + - type: recall_at_3 + value: 40.878 + - type: recall_at_5 + value: 50.690000000000005 + - task: + type: Classification + dataset: + type: mteb/mtop_domain + name: MTEB MTOPDomainClassification (en) + config: en + split: test + revision: d80d48c1eb48d3562165c59d59d0034df9fff0bf + metrics: + - type: accuracy + value: 93.95120839033288 + - type: f1 + value: 93.73824125055208 + - task: + type: Classification + dataset: + type: mteb/mtop_intent + name: MTEB MTOPIntentClassification (en) + config: en + split: test + revision: ae001d0e6b1228650b7bd1c2c65fb50ad11a8aba + metrics: + - type: accuracy + value: 76.78978568171455 + - type: f1 + value: 57.50180552858304 + - task: + type: Classification + dataset: + type: mteb/amazon_massive_intent + name: MTEB MassiveIntentClassification (en) + config: en + split: test + revision: 31efe3c427b0bae9c22cbb560b8f15491cc6bed7 + metrics: + - type: accuracy + value: 76.24411566913248 + - type: f1 + value: 74.37851403532832 + - task: + type: Classification + dataset: + type: mteb/amazon_massive_scenario + name: MTEB MassiveScenarioClassification (en) + config: en + split: test + revision: 7d571f92784cd94a019292a1f45445077d0ef634 + metrics: + - type: accuracy + value: 79.94620040349699 + - type: f1 + value: 80.21293397970435 + - task: + type: Clustering + dataset: + type: mteb/medrxiv-clustering-p2p + name: MTEB MedrxivClusteringP2P + config: default + split: test + revision: e7a26af6f3ae46b30dde8737f02c07b1505bcc73 + metrics: + - type: v_measure + value: 33.44403096245675 + - task: + type: Clustering + dataset: + type: mteb/medrxiv-clustering-s2s + name: MTEB MedrxivClusteringS2S + config: default + split: test + revision: 35191c8c0dca72d8ff3efcd72aa802307d469663 + metrics: + - type: v_measure + value: 31.659594631336812 + - task: + type: Reranking + dataset: + type: mteb/mind_small + name: MTEB MindSmallReranking + config: default + split: test + revision: 3bdac13927fdc888b903db93b2ffdbd90b295a69 + metrics: + - type: map + value: 32.53833075108798 + - type: mrr + value: 33.78840823218308 + - task: + type: Retrieval + dataset: + type: nfcorpus + name: MTEB NFCorpus + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 7.185999999999999 + - type: map_at_10 + value: 15.193999999999999 + - type: map_at_100 + value: 19.538 + - type: map_at_1000 + value: 21.178 + - type: map_at_3 + value: 11.208 + - type: map_at_5 + value: 12.745999999999999 + - type: mrr_at_1 + value: 48.916 + - type: mrr_at_10 + value: 58.141 + - type: mrr_at_100 + value: 58.656 + - type: mrr_at_1000 + value: 58.684999999999995 + - type: mrr_at_3 + value: 55.521 + - type: mrr_at_5 + value: 57.239 + - type: ndcg_at_1 + value: 47.059 + - type: ndcg_at_10 + value: 38.644 + - type: ndcg_at_100 + value: 36.272999999999996 + - type: ndcg_at_1000 + value: 44.996 + - type: ndcg_at_3 + value: 43.293 + - type: ndcg_at_5 + value: 40.819 + - type: precision_at_1 + value: 48.916 + - type: precision_at_10 + value: 28.607 + - type: precision_at_100 + value: 9.195 + - type: precision_at_1000 + value: 2.225 + - type: precision_at_3 + value: 40.454 + - type: precision_at_5 + value: 34.985 + - type: recall_at_1 + value: 7.185999999999999 + - type: recall_at_10 + value: 19.654 + - type: recall_at_100 + value: 37.224000000000004 + - type: recall_at_1000 + value: 68.663 + - type: recall_at_3 + value: 12.158 + - type: recall_at_5 + value: 14.674999999999999 + - task: + type: Retrieval + dataset: + type: nq + name: MTEB NQ + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 31.552000000000003 + - type: map_at_10 + value: 47.75 + - type: map_at_100 + value: 48.728 + - type: map_at_1000 + value: 48.754 + - type: map_at_3 + value: 43.156 + - type: map_at_5 + value: 45.883 + - type: mrr_at_1 + value: 35.66 + - type: mrr_at_10 + value: 50.269 + - type: mrr_at_100 + value: 50.974 + - type: mrr_at_1000 + value: 50.991 + - type: mrr_at_3 + value: 46.519 + - type: mrr_at_5 + value: 48.764 + - type: ndcg_at_1 + value: 35.632000000000005 + - type: ndcg_at_10 + value: 55.786 + - type: ndcg_at_100 + value: 59.748999999999995 + - type: ndcg_at_1000 + value: 60.339 + - type: ndcg_at_3 + value: 47.292 + - type: ndcg_at_5 + value: 51.766999999999996 + - type: precision_at_1 + value: 35.632000000000005 + - type: precision_at_10 + value: 9.267 + - type: precision_at_100 + value: 1.149 + - type: precision_at_1000 + value: 0.12 + - type: precision_at_3 + value: 21.601 + - type: precision_at_5 + value: 15.539 + - type: recall_at_1 + value: 31.552000000000003 + - type: recall_at_10 + value: 77.62400000000001 + - type: recall_at_100 + value: 94.527 + - type: recall_at_1000 + value: 98.919 + - type: recall_at_3 + value: 55.898 + - type: recall_at_5 + value: 66.121 + - task: + type: Retrieval + dataset: + type: quora + name: MTEB QuoraRetrieval + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 71.414 + - type: map_at_10 + value: 85.37400000000001 + - type: map_at_100 + value: 86.01100000000001 + - type: map_at_1000 + value: 86.027 + - type: map_at_3 + value: 82.562 + - type: map_at_5 + value: 84.284 + - type: mrr_at_1 + value: 82.24000000000001 + - type: mrr_at_10 + value: 88.225 + - type: mrr_at_100 + value: 88.324 + - type: mrr_at_1000 + value: 88.325 + - type: mrr_at_3 + value: 87.348 + - type: mrr_at_5 + value: 87.938 + - type: ndcg_at_1 + value: 82.24000000000001 + - type: ndcg_at_10 + value: 88.97699999999999 + - type: ndcg_at_100 + value: 90.16 + - type: ndcg_at_1000 + value: 90.236 + - type: ndcg_at_3 + value: 86.371 + - type: ndcg_at_5 + value: 87.746 + - type: precision_at_1 + value: 82.24000000000001 + - type: precision_at_10 + value: 13.481000000000002 + - type: precision_at_100 + value: 1.534 + - type: precision_at_1000 + value: 0.157 + - type: precision_at_3 + value: 37.86 + - type: precision_at_5 + value: 24.738 + - type: recall_at_1 + value: 71.414 + - type: recall_at_10 + value: 95.735 + - type: recall_at_100 + value: 99.696 + - type: recall_at_1000 + value: 99.979 + - type: recall_at_3 + value: 88.105 + - type: recall_at_5 + value: 92.17999999999999 + - task: + type: Clustering + dataset: + type: mteb/reddit-clustering + name: MTEB RedditClustering + config: default + split: test + revision: 24640382cdbf8abc73003fb0fa6d111a705499eb + metrics: + - type: v_measure + value: 60.22146692057259 + - task: + type: Clustering + dataset: + type: mteb/reddit-clustering-p2p + name: MTEB RedditClusteringP2P + config: default + split: test + revision: 282350215ef01743dc01b456c7f5241fa8937f16 + metrics: + - type: v_measure + value: 65.29273320614578 + - task: + type: Retrieval + dataset: + type: scidocs + name: MTEB SCIDOCS + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 5.023 + - type: map_at_10 + value: 14.161000000000001 + - type: map_at_100 + value: 16.68 + - type: map_at_1000 + value: 17.072000000000003 + - type: map_at_3 + value: 9.763 + - type: map_at_5 + value: 11.977 + - type: mrr_at_1 + value: 24.8 + - type: mrr_at_10 + value: 37.602999999999994 + - type: mrr_at_100 + value: 38.618 + - type: mrr_at_1000 + value: 38.659 + - type: mrr_at_3 + value: 34.117 + - type: mrr_at_5 + value: 36.082 + - type: ndcg_at_1 + value: 24.8 + - type: ndcg_at_10 + value: 23.316 + - type: ndcg_at_100 + value: 32.613 + - type: ndcg_at_1000 + value: 38.609 + - type: ndcg_at_3 + value: 21.697 + - type: ndcg_at_5 + value: 19.241 + - type: precision_at_1 + value: 24.8 + - type: precision_at_10 + value: 12.36 + - type: precision_at_100 + value: 2.593 + - type: precision_at_1000 + value: 0.402 + - type: precision_at_3 + value: 20.767 + - type: precision_at_5 + value: 17.34 + - type: recall_at_1 + value: 5.023 + - type: recall_at_10 + value: 25.069999999999997 + - type: recall_at_100 + value: 52.563 + - type: recall_at_1000 + value: 81.525 + - type: recall_at_3 + value: 12.613 + - type: recall_at_5 + value: 17.583 + - task: + type: STS + dataset: + type: mteb/sickr-sts + name: MTEB SICK-R + config: default + split: test + revision: a6ea5a8cab320b040a23452cc28066d9beae2cee + metrics: + - type: cos_sim_pearson + value: 87.71506247604255 + - type: cos_sim_spearman + value: 82.91813463738802 + - type: euclidean_pearson + value: 85.5154616194479 + - type: euclidean_spearman + value: 82.91815254466314 + - type: manhattan_pearson + value: 85.5280917850374 + - type: manhattan_spearman + value: 82.92276537286398 + - task: + type: STS + dataset: + type: mteb/sts12-sts + name: MTEB STS12 + config: default + split: test + revision: a0d554a64d88156834ff5ae9920b964011b16384 + metrics: + - type: cos_sim_pearson + value: 87.43772054228462 + - type: cos_sim_spearman + value: 78.75750601716682 + - type: euclidean_pearson + value: 85.76074482955764 + - type: euclidean_spearman + value: 78.75651057223058 + - type: manhattan_pearson + value: 85.73390291701668 + - type: manhattan_spearman + value: 78.72699385957797 + - task: + type: STS + dataset: + type: mteb/sts13-sts + name: MTEB STS13 + config: default + split: test + revision: 7e90230a92c190f1bf69ae9002b8cea547a64cca + metrics: + - type: cos_sim_pearson + value: 89.58144067172472 + - type: cos_sim_spearman + value: 90.3524512966946 + - type: euclidean_pearson + value: 89.71365391594237 + - type: euclidean_spearman + value: 90.35239632843408 + - type: manhattan_pearson + value: 89.66905421746478 + - type: manhattan_spearman + value: 90.31508211683513 + - task: + type: STS + dataset: + type: mteb/sts14-sts + name: MTEB STS14 + config: default + split: test + revision: 6031580fec1f6af667f0bd2da0a551cf4f0b2375 + metrics: + - type: cos_sim_pearson + value: 87.77692637102102 + - type: cos_sim_spearman + value: 85.45710562643485 + - type: euclidean_pearson + value: 87.42456979928723 + - type: euclidean_spearman + value: 85.45709386240908 + - type: manhattan_pearson + value: 87.40754529526272 + - type: manhattan_spearman + value: 85.44834854173303 + - task: + type: STS + dataset: + type: mteb/sts15-sts + name: MTEB STS15 + config: default + split: test + revision: ae752c7c21bf194d8b67fd573edf7ae58183cbe3 + metrics: + - type: cos_sim_pearson + value: 88.28491331695997 + - type: cos_sim_spearman + value: 89.62037029566964 + - type: euclidean_pearson + value: 89.02479391362826 + - type: euclidean_spearman + value: 89.62036733618466 + - type: manhattan_pearson + value: 89.00394756040342 + - type: manhattan_spearman + value: 89.60867744215236 + - task: + type: STS + dataset: + type: mteb/sts16-sts + name: MTEB STS16 + config: default + split: test + revision: 4d8694f8f0e0100860b497b999b3dbed754a0513 + metrics: + - type: cos_sim_pearson + value: 85.08911381280191 + - type: cos_sim_spearman + value: 86.5791780765767 + - type: euclidean_pearson + value: 86.16063473577861 + - type: euclidean_spearman + value: 86.57917745378766 + - type: manhattan_pearson + value: 86.13677924604175 + - type: manhattan_spearman + value: 86.56115615768685 + - task: + type: STS + dataset: + type: mteb/sts17-crosslingual-sts + name: MTEB STS17 (en-en) + config: en-en + split: test + revision: af5e6fb845001ecf41f4c1e033ce921939a2a68d + metrics: + - type: cos_sim_pearson + value: 89.58029496205235 + - type: cos_sim_spearman + value: 89.49551253826998 + - type: euclidean_pearson + value: 90.13714840963748 + - type: euclidean_spearman + value: 89.49551253826998 + - type: manhattan_pearson + value: 90.13039633601363 + - type: manhattan_spearman + value: 89.4513453745516 + - task: + type: STS + dataset: + type: mteb/sts22-crosslingual-sts + name: MTEB STS22 (en) + config: en + split: test + revision: 6d1ba47164174a496b7fa5d3569dae26a6813b80 + metrics: + - type: cos_sim_pearson + value: 69.01546399666435 + - type: cos_sim_spearman + value: 69.33824484595624 + - type: euclidean_pearson + value: 70.76511642998874 + - type: euclidean_spearman + value: 69.33824484595624 + - type: manhattan_pearson + value: 70.84320785047453 + - type: manhattan_spearman + value: 69.54233632223537 + - task: + type: STS + dataset: + type: mteb/stsbenchmark-sts + name: MTEB STSBenchmark + config: default + split: test + revision: b0fddb56ed78048fa8b90373c8a3cfc37b684831 + metrics: + - type: cos_sim_pearson + value: 87.26389196390119 + - type: cos_sim_spearman + value: 89.09721478341385 + - type: euclidean_pearson + value: 88.97208685922517 + - type: euclidean_spearman + value: 89.09720927308881 + - type: manhattan_pearson + value: 88.97513670502573 + - type: manhattan_spearman + value: 89.07647853984004 + - task: + type: Reranking + dataset: + type: mteb/scidocs-reranking + name: MTEB SciDocsRR + config: default + split: test + revision: d3c5e1fc0b855ab6097bf1cda04dd73947d7caab + metrics: + - type: map + value: 87.53075025771936 + - type: mrr + value: 96.24327651288436 + - task: + type: Retrieval + dataset: + type: scifact + name: MTEB SciFact + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 60.428000000000004 + - type: map_at_10 + value: 70.088 + - type: map_at_100 + value: 70.589 + - type: map_at_1000 + value: 70.614 + - type: map_at_3 + value: 67.191 + - type: map_at_5 + value: 68.515 + - type: mrr_at_1 + value: 63.333 + - type: mrr_at_10 + value: 71.13000000000001 + - type: mrr_at_100 + value: 71.545 + - type: mrr_at_1000 + value: 71.569 + - type: mrr_at_3 + value: 68.944 + - type: mrr_at_5 + value: 70.078 + - type: ndcg_at_1 + value: 63.333 + - type: ndcg_at_10 + value: 74.72800000000001 + - type: ndcg_at_100 + value: 76.64999999999999 + - type: ndcg_at_1000 + value: 77.176 + - type: ndcg_at_3 + value: 69.659 + - type: ndcg_at_5 + value: 71.626 + - type: precision_at_1 + value: 63.333 + - type: precision_at_10 + value: 10 + - type: precision_at_100 + value: 1.09 + - type: precision_at_1000 + value: 0.11299999999999999 + - type: precision_at_3 + value: 27.111 + - type: precision_at_5 + value: 17.666999999999998 + - type: recall_at_1 + value: 60.428000000000004 + - type: recall_at_10 + value: 87.98899999999999 + - type: recall_at_100 + value: 96.167 + - type: recall_at_1000 + value: 100 + - type: recall_at_3 + value: 74.006 + - type: recall_at_5 + value: 79.05 + - task: + type: PairClassification + dataset: + type: mteb/sprintduplicatequestions-pairclassification + name: MTEB SprintDuplicateQuestions + config: default + split: test + revision: d66bd1f72af766a5cc4b0ca5e00c162f89e8cc46 + metrics: + - type: cos_sim_accuracy + value: 99.87326732673267 + - type: cos_sim_ap + value: 96.81770773701805 + - type: cos_sim_f1 + value: 93.6318407960199 + - type: cos_sim_precision + value: 93.16831683168317 + - type: cos_sim_recall + value: 94.1 + - type: dot_accuracy + value: 99.87326732673267 + - type: dot_ap + value: 96.8174218946665 + - type: dot_f1 + value: 93.6318407960199 + - type: dot_precision + value: 93.16831683168317 + - type: dot_recall + value: 94.1 + - type: euclidean_accuracy + value: 99.87326732673267 + - type: euclidean_ap + value: 96.81770773701807 + - type: euclidean_f1 + value: 93.6318407960199 + - type: euclidean_precision + value: 93.16831683168317 + - type: euclidean_recall + value: 94.1 + - type: manhattan_accuracy + value: 99.87227722772278 + - type: manhattan_ap + value: 96.83164126821747 + - type: manhattan_f1 + value: 93.54677338669335 + - type: manhattan_precision + value: 93.5935935935936 + - type: manhattan_recall + value: 93.5 + - type: max_accuracy + value: 99.87326732673267 + - type: max_ap + value: 96.83164126821747 + - type: max_f1 + value: 93.6318407960199 + - task: + type: Clustering + dataset: + type: mteb/stackexchange-clustering + name: MTEB StackExchangeClustering + config: default + split: test + revision: 6cbc1f7b2bc0622f2e39d2c77fa502909748c259 + metrics: + - type: v_measure + value: 65.6212042420246 + - task: + type: Clustering + dataset: + type: mteb/stackexchange-clustering-p2p + name: MTEB StackExchangeClusteringP2P + config: default + split: test + revision: 815ca46b2622cec33ccafc3735d572c266efdb44 + metrics: + - type: v_measure + value: 35.779230635982564 + - task: + type: Reranking + dataset: + type: mteb/stackoverflowdupquestions-reranking + name: MTEB StackOverflowDupQuestions + config: default + split: test + revision: e185fbe320c72810689fc5848eb6114e1ef5ec69 + metrics: + - type: map + value: 55.217701909036286 + - type: mrr + value: 56.17658995416349 + - task: + type: Summarization + dataset: + type: mteb/summeval + name: MTEB SummEval + config: default + split: test + revision: cda12ad7615edc362dbf25a00fdd61d3b1eaf93c + metrics: + - type: cos_sim_pearson + value: 30.954206018888453 + - type: cos_sim_spearman + value: 32.71062599450096 + - type: dot_pearson + value: 30.95420929056943 + - type: dot_spearman + value: 32.71062599450096 + - task: + type: Retrieval + dataset: + type: trec-covid + name: MTEB TRECCOVID + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 0.22699999999999998 + - type: map_at_10 + value: 1.924 + - type: map_at_100 + value: 10.525 + - type: map_at_1000 + value: 24.973 + - type: map_at_3 + value: 0.638 + - type: map_at_5 + value: 1.0659999999999998 + - type: mrr_at_1 + value: 84 + - type: mrr_at_10 + value: 91.067 + - type: mrr_at_100 + value: 91.067 + - type: mrr_at_1000 + value: 91.067 + - type: mrr_at_3 + value: 90.667 + - type: mrr_at_5 + value: 91.067 + - type: ndcg_at_1 + value: 81 + - type: ndcg_at_10 + value: 75.566 + - type: ndcg_at_100 + value: 56.387 + - type: ndcg_at_1000 + value: 49.834 + - type: ndcg_at_3 + value: 80.899 + - type: ndcg_at_5 + value: 80.75099999999999 + - type: precision_at_1 + value: 84 + - type: precision_at_10 + value: 79 + - type: precision_at_100 + value: 57.56 + - type: precision_at_1000 + value: 21.8 + - type: precision_at_3 + value: 84.667 + - type: precision_at_5 + value: 85.2 + - type: recall_at_1 + value: 0.22699999999999998 + - type: recall_at_10 + value: 2.136 + - type: recall_at_100 + value: 13.861 + - type: recall_at_1000 + value: 46.299 + - type: recall_at_3 + value: 0.6649999999999999 + - type: recall_at_5 + value: 1.145 + - task: + type: Retrieval + dataset: + type: webis-touche2020 + name: MTEB Touche2020 + config: default + split: test + revision: None + metrics: + - type: map_at_1 + value: 2.752 + - type: map_at_10 + value: 9.951 + - type: map_at_100 + value: 16.794999999999998 + - type: map_at_1000 + value: 18.251 + - type: map_at_3 + value: 5.288 + - type: map_at_5 + value: 6.954000000000001 + - type: mrr_at_1 + value: 38.775999999999996 + - type: mrr_at_10 + value: 50.458000000000006 + - type: mrr_at_100 + value: 51.324999999999996 + - type: mrr_at_1000 + value: 51.339999999999996 + - type: mrr_at_3 + value: 46.939 + - type: mrr_at_5 + value: 47.857 + - type: ndcg_at_1 + value: 36.735 + - type: ndcg_at_10 + value: 25.198999999999998 + - type: ndcg_at_100 + value: 37.938 + - type: ndcg_at_1000 + value: 49.145 + - type: ndcg_at_3 + value: 29.348000000000003 + - type: ndcg_at_5 + value: 25.804 + - type: precision_at_1 + value: 38.775999999999996 + - type: precision_at_10 + value: 22.041 + - type: precision_at_100 + value: 7.939 + - type: precision_at_1000 + value: 1.555 + - type: precision_at_3 + value: 29.932 + - type: precision_at_5 + value: 24.490000000000002 + - type: recall_at_1 + value: 2.752 + - type: recall_at_10 + value: 16.197 + - type: recall_at_100 + value: 49.166 + - type: recall_at_1000 + value: 84.18900000000001 + - type: recall_at_3 + value: 6.438000000000001 + - type: recall_at_5 + value: 9.093 + - task: + type: Classification + dataset: + type: mteb/toxic_conversations_50k + name: MTEB ToxicConversationsClassification + config: default + split: test + revision: d7c0de2777da35d6aae2200a62c6e0e5af397c4c + metrics: + - type: accuracy + value: 71.47980000000001 + - type: ap + value: 14.605194452178754 + - type: f1 + value: 55.07362924988948 + - task: + type: Classification + dataset: + type: mteb/tweet_sentiment_extraction + name: MTEB TweetSentimentExtractionClassification + config: default + split: test + revision: d604517c81ca91fe16a244d1248fc021f9ecee7a + metrics: + - type: accuracy + value: 59.708545557441994 + - type: f1 + value: 60.04751270975683 + - task: + type: Clustering + dataset: + type: mteb/twentynewsgroups-clustering + name: MTEB TwentyNewsgroupsClustering + config: default + split: test + revision: 6125ec4e24fa026cec8a478383ee943acfbd5449 + metrics: + - type: v_measure + value: 53.21105960597211 + - task: + type: PairClassification + dataset: + type: mteb/twittersemeval2015-pairclassification + name: MTEB TwitterSemEval2015 + config: default + split: test + revision: 70970daeab8776df92f5ea462b6173c0b46fd2d1 + metrics: + - type: cos_sim_accuracy + value: 87.58419264469214 + - type: cos_sim_ap + value: 78.55300004517404 + - type: cos_sim_f1 + value: 71.49673530889001 + - type: cos_sim_precision + value: 68.20795400095831 + - type: cos_sim_recall + value: 75.11873350923483 + - type: dot_accuracy + value: 87.58419264469214 + - type: dot_ap + value: 78.55297659559511 + - type: dot_f1 + value: 71.49673530889001 + - type: dot_precision + value: 68.20795400095831 + - type: dot_recall + value: 75.11873350923483 + - type: euclidean_accuracy + value: 87.58419264469214 + - type: euclidean_ap + value: 78.55300477331477 + - type: euclidean_f1 + value: 71.49673530889001 + - type: euclidean_precision + value: 68.20795400095831 + - type: euclidean_recall + value: 75.11873350923483 + - type: manhattan_accuracy + value: 87.5663110210407 + - type: manhattan_ap + value: 78.49982050876562 + - type: manhattan_f1 + value: 71.35488740722104 + - type: manhattan_precision + value: 68.18946862226497 + - type: manhattan_recall + value: 74.82849604221636 + - type: max_accuracy + value: 87.58419264469214 + - type: max_ap + value: 78.55300477331477 + - type: max_f1 + value: 71.49673530889001 + - task: + type: PairClassification + dataset: + type: mteb/twitterurlcorpus-pairclassification + name: MTEB TwitterURLCorpus + config: default + split: test + revision: 8b6510b0b1fa4e4c4f879467980e9be563ec1cdf + metrics: + - type: cos_sim_accuracy + value: 89.09069740365584 + - type: cos_sim_ap + value: 86.22749303724757 + - type: cos_sim_f1 + value: 78.36863452005407 + - type: cos_sim_precision + value: 76.49560117302053 + - type: cos_sim_recall + value: 80.33569448721897 + - type: dot_accuracy + value: 89.09069740365584 + - type: dot_ap + value: 86.22750233655673 + - type: dot_f1 + value: 78.36863452005407 + - type: dot_precision + value: 76.49560117302053 + - type: dot_recall + value: 80.33569448721897 + - type: euclidean_accuracy + value: 89.09069740365584 + - type: euclidean_ap + value: 86.22749355597347 + - type: euclidean_f1 + value: 78.36863452005407 + - type: euclidean_precision + value: 76.49560117302053 + - type: euclidean_recall + value: 80.33569448721897 + - type: manhattan_accuracy + value: 89.08293553770326 + - type: manhattan_ap + value: 86.21913616084771 + - type: manhattan_f1 + value: 78.3907031479847 + - type: manhattan_precision + value: 75.0352013517319 + - type: manhattan_recall + value: 82.06036341238065 + - type: max_accuracy + value: 89.09069740365584 + - type: max_ap + value: 86.22750233655673 + - type: max_f1 + value: 78.3907031479847 +license: apache-2.0 +language: +- en +library_name: sentence-transformers +pipeline_tag: feature-extraction +--- + +

+ +

+ +

+ +

+The crispy sentence embedding family from Mixedbread. +

+ +

+ 🍞 Looking for a simple end-to-end retrieval solution? Meet Omni, our multimodal and multilingual model. Get in touch for access. +

+ + +# mixedbread-ai/mxbai-embed-large-v1 + +Here, we provide several ways to produce sentence embeddings. Please note that you have to provide the prompt `Represent this sentence for searching relevant passages:` for query if you want to use it for retrieval. Besides that you don't need any prompt. Our model also supports [Matryoshka Representation Learning and binary quantization](https://www.mixedbread.ai/blog/binary-mrl). + +## Quickstart + +Here, we provide several ways to produce sentence embeddings. Please note that you have to provide the prompt `Represent this sentence for searching relevant passages: ` for query if you want to use it for retrieval. Besides that you don't need any prompt. + +### sentence-transformers + +``` +python -m pip install -U sentence-transformers +``` + +```python +from sentence_transformers import SentenceTransformer +from sentence_transformers.util import cos_sim +from sentence_transformers.quantization import quantize_embeddings + +# 1. Specify preffered dimensions +dimensions = 512 + +# 2. load model +model = SentenceTransformer("mixedbread-ai/mxbai-embed-large-v1", truncate_dim=dimensions) + +# The prompt used for query retrieval tasks: +# query_prompt = 'Represent this sentence for searching relevant passages: ' + +query = "A man is eating a piece of bread" +docs = [ + "A man is eating food.", + "A man is eating pasta.", + "The girl is carrying a baby.", + "A man is riding a horse.", +] + +# 2. Encode +query_embedding = model.encode(query, prompt_name="query") +# Equivalent Alternatives: +# query_embedding = model.encode(query_prompt + query) +# query_embedding = model.encode(query, prompt=query_prompt) + +docs_embeddings = model.encode(docs) + +# Optional: Quantize the embeddings +binary_query_embedding = quantize_embeddings(query_embedding, precision="ubinary") +binary_docs_embeddings = quantize_embeddings(docs_embeddings, precision="ubinary") + +similarities = cos_sim(query_embedding, docs_embeddings) +print('similarities:', similarities) +``` + +### Transformers + +```python +from typing import Dict + +import torch +import numpy as np +from transformers import AutoModel, AutoTokenizer +from sentence_transformers.util import cos_sim + +# For retrieval you need to pass this prompt. Please find our more in our blog post. +def transform_query(query: str) -> str: + """ For retrieval, add the prompt for query (not for documents). + """ + return f'Represent this sentence for searching relevant passages: {query}' + +# The model works really well with cls pooling (default) but also with mean pooling. +def pooling(outputs: torch.Tensor, inputs: Dict, strategy: str = 'cls') -> np.ndarray: + if strategy == 'cls': + outputs = outputs[:, 0] + elif strategy == 'mean': + outputs = torch.sum( + outputs * inputs["attention_mask"][:, :, None], dim=1) / torch.sum(inputs["attention_mask"], dim=1, keepdim=True) + else: + raise NotImplementedError + return outputs.detach().cpu().numpy() + +# 1. load model +model_id = 'mixedbread-ai/mxbai-embed-large-v1' +tokenizer = AutoTokenizer.from_pretrained(model_id) +model = AutoModel.from_pretrained(model_id).cuda() + + +docs = [ + transform_query('A man is eating a piece of bread'), + "A man is eating food.", + "A man is eating pasta.", + "The girl is carrying a baby.", + "A man is riding a horse.", +] + +# 2. encode +inputs = tokenizer(docs, padding=True, return_tensors='pt') +for k, v in inputs.items(): + inputs[k] = v.cuda() +outputs = model(**inputs).last_hidden_state +embeddings = pooling(outputs, inputs, 'cls') + +similarities = cos_sim(embeddings[0], embeddings[1:]) +print('similarities:', similarities) +``` + +### Transformers.js + +If you haven't already, you can install the [Transformers.js](https://huggingface.co/docs/transformers.js) JavaScript library from [NPM](https://www.npmjs.com/package/@xenova/transformers) using: + +``` +npm i @xenova/transformers +``` + +You can then use the model to compute embeddings like this: + +```javascript +import { pipeline, cos_sim } from '@xenova/transformers'; + +// Create a feature extraction pipeline +const extractor = await pipeline('feature-extraction', 'mixedbread-ai/mxbai-embed-large-v1', { + quantized: false, // Comment out this line to use the quantized version +}); + +// Generate sentence embeddings +const docs = [ + 'Represent this sentence for searching relevant passages: A man is eating a piece of bread', + 'A man is eating food.', + 'A man is eating pasta.', + 'The girl is carrying a baby.', + 'A man is riding a horse.', +] +const output = await extractor(docs, { pooling: 'cls' }); + +// Compute similarity scores +const [source_embeddings, ...document_embeddings ] = output.tolist(); +const similarities = document_embeddings.map(x => cos_sim(source_embeddings, x)); +console.log(similarities); // [0.7919578577247139, 0.6369278664248345, 0.16512018371357193, 0.3620778366720027] +``` + +### Using API + +You can use the model via our API as follows: + +```python +from mixedbread_ai.client import MixedbreadAI, EncodingFormat +from sklearn.metrics.pairwise import cosine_similarity +import os + +mxbai = MixedbreadAI(api_key="{MIXEDBREAD_API_KEY}") + +english_sentences = [ + 'What is the capital of Australia?', + 'Canberra is the capital of Australia.' +] + +res = mxbai.embeddings( + input=english_sentences, + model="mixedbread-ai/mxbai-embed-large-v1", + normalized=True, + encoding_format=[EncodingFormat.FLOAT, EncodingFormat.UBINARY, EncodingFormat.INT_8], + dimensions=512 +) + +encoded_embeddings = res.data[0].embedding +print(res.dimensions, encoded_embeddings.ubinary, encoded_embeddings.float_, encoded_embeddings.int_8) +``` + +The API comes with native int8 and binary quantization support! Check out the [docs](https://mixedbread.ai/docs) for more information. + +### Infinity +```bash +docker run --gpus all -v $PWD/data:/app/.cache -p "7997":"7997" \ +michaelf34/infinity:0.0.68 \ +v2 --model-id mixedbread-ai/mxbai-embed-large-v1 --revision "main" --dtype float16 --engine torch --port 7997 +``` + +## Evaluation +As of March 2024, our model archives SOTA performance for Bert-large sized models on the [MTEB](https://huggingface.co/spaces/mteb/leaderboard). It ourperforms commercial models like OpenAIs text-embedding-3-large and matches the performance of model 20x it's size like the [echo-mistral-7b](https://huggingface.co/jspringer/echo-mistral-7b-instruct-lasttoken). Our model was trained with no overlap of the MTEB data, which indicates that our model generalizes well across several domains, tasks and text length. We know there are some limitations with this model, which will be fixed in v2. + + +| Model | Avg (56 datasets) | Classification (12 datasets) | Clustering (11 datasets) | PairClassification (3 datasets) | Reranking (4 datasets) | Retrieval (15 datasets) | STS (10 datasets) | Summarization (1 dataset) | +| --------------------------------------------------------------------------------------------- | ----------------- | ---------------------------- | ------------------------ | ------------------------------- | ---------------------- | ----------------------- | ----------------- | ------------------------- | +| **mxbai-embed-large-v1** | **64.68** | 75.64 | 46.71 | 87.2 | 60.11 | 54.39 | 85.00 | 32.71 | +| [bge-large-en-v1.5](https://huggingface.co/BAAI/bge-large-en-v1.5) | 64.23 | 75.97 | 46.08 | 87.12 | 60.03 | 54.29 | 83.11 | 31.61 | +| [mxbai-embed-2d-large-v1](https://huggingface.co/mixedbread-ai/mxbai-embed-2d-large-v1) | 63.25 | 74.14 | 46.07 | 85.89 | 58.94 | 51.42 | 84.9 | 31.55 | +| [nomic-embed-text-v1](https://huggingface.co/nomic-ai/nomic-embed-text-v1) | 62.39 | 74.12 | 43.91 | 85.15 | 55.69 | 52.81 | 82.06 | 30.08 | +| [jina-embeddings-v2-base-en](https://huggingface.co/jinaai/jina-embeddings-v2-base-en) | 60.38 | 73.45 | 41.73 | 85.38 | 56.98 | 47.87 | 80.7 | 31.6 | +| *Proprietary Models* | | | | | | | | | +| [OpenAI text-embedding-3-large](https://openai.com/blog/new-embedding-models-and-api-updates) | 64.58 | 75.45 | 49.01 | 85.72 | 59.16 | 55.44 | 81.73 | 29.92 | +| [Cohere embed-english-v3.0](https://txt.cohere.com/introducing-embed-v3/) | 64.47 | 76.49 | 47.43 | 85.84 | 58.01 | 55.00 | 82.62 | 30.18 | +| [OpenAI text-embedding-ada-002](https://openai.com/blog/new-and-improved-embedding-model) | 60.99 | 70.93 | 45.90 | 84.89 | 56.32 | 49.25 | 80.97 | 30.80 | + + +Please find more information in our [blog post](https://mixedbread.ai/blog/mxbai-embed-large-v1). + +## Matryoshka and Binary Quantization + +Embeddings in their commonly used form (float arrays) have a high memory footprint when used at scale. Two approaches to solve this problem are Matryoshka Representation Learning (MRL) and (Binary) Quantization. While MRL reduces the number of dimensions of an embedding, binary quantization transforms the value of each dimension from a float32 into a lower precision (int8 or even binary). The model supports both approaches! + +You can also take it one step further, and combine both MRL and quantization. This combination of binary quantization and MRL allows you to reduce the memory usage of your embeddings significantly. This leads to much lower costs when using a vector database in particular. You can read more about the technology and its advantages in our [blog post](https://www.mixedbread.ai/blog/binary-mrl). + +## Community +Please join our [Discord Community](https://discord.gg/jDfMHzAVfU) and share your feedback and thoughts! We are here to help and also always happy to chat. + +## License +Apache 2.0 + +## Citation + +```bibtex +@online{emb2024mxbai, + title={Open Source Strikes Bread - New Fluffy Embeddings Model}, + author={Sean Lee and Aamir Shakir and Darius Koenig and Julius Lipp}, + year={2024}, + url={https://www.mixedbread.ai/blog/mxbai-embed-large-v1}, +} + +@article{li2023angle, + title={AnglE-optimized Text Embeddings}, + author={Li, Xianming and Li, Jing}, + journal={arXiv preprint arXiv:2309.12871}, + year={2023} +} +``` diff --git a/flow-Agent/models/mxbai-embed-large-v1/config.json b/flow-Agent/models/mxbai-embed-large-v1/config.json new file mode 100644 index 0000000..a055edb --- /dev/null +++ b/flow-Agent/models/mxbai-embed-large-v1/config.json @@ -0,0 +1,26 @@ +{ + "_name_or_path": "mixedbread-ai/mxbai-embed-large-v1", + "architectures": [ + "BertModel" + ], + "attention_probs_dropout_prob": 0.1, + "classifier_dropout": null, + "gradient_checkpointing": false, + "hidden_act": "gelu", + "hidden_dropout_prob": 0.1, + "hidden_size": 1024, + "initializer_range": 0.02, + "intermediate_size": 4096, + "layer_norm_eps": 1e-12, + "max_position_embeddings": 512, + "model_type": "bert", + "num_attention_heads": 16, + "num_hidden_layers": 24, + "pad_token_id": 0, + "position_embedding_type": "absolute", + "torch_dtype": "float16", + "transformers_version": "4.38.2", + "type_vocab_size": 2, + "use_cache": false, + "vocab_size": 30522 +} diff --git a/flow-Agent/models/mxbai-embed-large-v1/config_sentence_transformers.json b/flow-Agent/models/mxbai-embed-large-v1/config_sentence_transformers.json new file mode 100644 index 0000000..173e6cf --- /dev/null +++ b/flow-Agent/models/mxbai-embed-large-v1/config_sentence_transformers.json @@ -0,0 +1,12 @@ +{ + "__version__": { + "sentence_transformers": "2.5.1", + "transformers": "4.37.0", + "pytorch": "2.1.0+cu121" + }, + "prompts": { + "query": "Represent this sentence for searching relevant passages: ", + "passage": "" + }, + "default_prompt_name": null +} \ No newline at end of file diff --git a/flow-Agent/models/mxbai-embed-large-v1/gguf/mxbai-embed-large-v1-f16.gguf b/flow-Agent/models/mxbai-embed-large-v1/gguf/mxbai-embed-large-v1-f16.gguf new file mode 100644 index 0000000..a07c052 --- /dev/null +++ b/flow-Agent/models/mxbai-embed-large-v1/gguf/mxbai-embed-large-v1-f16.gguf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:819c2adf5ce6df2b6bd2ae4ca90d2a69f060afeb438d0c171db57daa02e39c3d +size 669603712 diff --git a/flow-Agent/models/mxbai-embed-large-v1/modules.json b/flow-Agent/models/mxbai-embed-large-v1/modules.json new file mode 100644 index 0000000..f7640f9 --- /dev/null +++ b/flow-Agent/models/mxbai-embed-large-v1/modules.json @@ -0,0 +1,14 @@ +[ + { + "idx": 0, + "name": "0", + "path": "", + "type": "sentence_transformers.models.Transformer" + }, + { + "idx": 1, + "name": "1", + "path": "1_Pooling", + "type": "sentence_transformers.models.Pooling" + } +] \ No newline at end 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sys @@ -9,11 +8,27 @@ import anthropic import csv import random - +from rag.util import answerWithRAG +from rag.index import load_embeddings_and_docs, build_and_save_embeddings +from sentence_transformers import SentenceTransformer +import torch +from pathlib import Path +from openai import OpenAI from inspectfuncs import * from modelfuncs import * from agglomfuncs import * +print("Python executable:", sys.executable) +print("sys.path:", sys.path[:3]) +print("Current working dir:", os.getcwd()) + +for pkg in ["anthropic", "sentence_transformers", "torch", "openai"]: + try: + __import__(pkg) + print(f"Imported {pkg}") + except ImportError as e: + print(f"Failed to import {pkg}: {e}") + def process_log_file(log_path: str) -> Dict[str, Any]: """Process a single log file to extract relevant metrics""" run_data = { @@ -25,6 +40,7 @@ def process_log_file(log_path: str) -> Dict[str, Any]: with open(log_path, 'r') as f: content = f.read() + print(f"File size: {len(content)} characters") # Extract timing information timing_metrics = extract_timing_metrics(content) @@ -37,8 +53,13 @@ def process_log_file(log_path: str) -> Dict[str, Any]: # Extract any errors errors = extract_errors(content) run_data['errors'].extend(errors) - - # Determine success based on completion markers and errors + # === Inject a simulated error for testing RAG debugging === + # if "run3" in log_path: # You can change it to any run，eg. run1 or run2 + # fake_error = "[ERROR] TEST_SIM: Simulated routing congestion failure" + # print(f"[DEBUG] Injected simulated error in {log_path}: {fake_error}") + # run_data['errors'].append(fake_error) + # run_data['success'] = False + run_data['success'] = is_run_successful(content, errors) return run_data @@ -53,17 +74,20 @@ def extract_timing_metrics(log_content: str) -> Dict[str, float]: metrics['worst_slack'] = float(slack_match.group(1)) # Extract CTS worst slack - cts_slack_match = re.search(r'(?:CTS|Clock Tree) (?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + # cts_slack_match = re.search(r'(?:CTS|Clock Tree) (?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + cts_slack_match = re.search(r'Timing-driven:\s*(?:worst slack|WNS)\s+([-\d.eE]+)', log_content, re.IGNORECASE) if cts_slack_match: metrics['cts_ws'] = float(cts_slack_match.group(1)) # Extract clock period - period_match = re.search(r'[Cc]lock period:\s*([\d.]+)', log_content) + # period_match = re.search(r'[Cc]lock period:\s*([\d.]+)', log_content) + period_match = re.search(r'clock period to\s*([\d.]+)', log_content) if period_match: metrics['clock_period'] = float(period_match.group(1)) # Extract TNS - tns_match = re.search(r'(?:Total negative slack|TNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + # tns_match = re.search(r'(?:Total negative slack|TNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + tns_match = re.search(r'"finish__timing__setup__tns"\s*:\s*([-\d.eE]+)', log_content) if tns_match: metrics['tns'] = float(tns_match.group(1)) @@ -79,7 +103,8 @@ def extract_wirelength_metrics(log_content: str) -> Dict[str, float]: metrics['total_wirelength'] = float(wl_match.group(1)) # Extract estimated wirelength after CTS - cts_wl_match = re.search(r'Estimated wirelength: ([\d.]+)', log_content) + # cts_wl_match = re.search(r'Estimated wirelength: ([\d.]+)', log_content) + cts_wl_match = re.search(r'"?cts__route__wirelength__estimated"?\s*[:=]\s*([-\d.eE]+)', log_content, re.IGNORECASE) if cts_wl_match: metrics['cts_wirelength'] = float(cts_wl_match.group(1)) @@ -103,19 +128,200 @@ def extract_errors(log_content: str) -> List[str]: return errors -def is_run_successful(log_content: str, errors: List[str]) -> bool: +def is_run_successful(log_content: str, errors: List[str], filename: str = "") -> bool: """Determine if a run was successful based on log content and errors""" if errors: + # If any real error lines were found, this file is a failure indicator return False # Look for completion markers completion_markers = [ 'Flow complete', 'Finished successfully' + 'Writing out GDS/OAS', + '6_report' ] return any(marker in log_content for marker in completion_markers) + +class ReActFramework: + """ReAct framework implementation""" + + def __init__(self, client, model_name="DeepSeek-V3"): + self.client = client + self.model_name = model_name + self.conversation_history = [] + + def add_to_history(self, role: str, content: str): + """add conversation history""" + self.conversation_history.append({"role": role, "content": content}) + + def clear_history(self): + """clear conversation history""" + self.conversation_history = [] + + def extract_thought_action(self, response: str) -> Tuple[str, str, str]: + """ + Extract Thought, Action, and Action Input from LLM responses + Format: Thought:... Action:... Action Input: ... + """ + thought = "" + action = "" + action_input = "" + + # Extract Thought + thought_match = re.search(r'Thought:\s*(.*?)(?=\nAction:|$)', response, re.DOTALL) + if thought_match: + thought = thought_match.group(1).strip() + + # Extract Action + action_match = re.search(r'Action:\s*(\w+)', response) + if action_match: + action = action_match.group(1).strip() + + # Extract Action Input + action_input_match = re.search(r'Action Input:\s*(.*?)(?=\nObservation:|$)', response, re.DOTALL) + if action_input_match: + action_input = action_input_match.group(1).strip() + # Try to parse JSON + try: + if action_input.startswith('{') or action_input.startswith('['): + action_input = json.loads(action_input) + except: + pass # Maintain the string format + + if "Final Answer:" in response and ("Action:" in response or "Observation:" in response): + + response = response.split("Final Answer:")[0] + print("Removed premature Final Answer from response") + + return thought, action, action_input + + def execute_action(self, action: str, action_input: Any, available_tools: Dict) -> str: + """Execute tool call and return observation results""" + if action in available_tools: + try: + result = available_tools[action](action_input) + return f"Action executed successfully. Result: {result}" + except Exception as e: + return f"Action execution failed: {str(e)}" + else: + return f"Unknown action: {action}. Available actions: {list(available_tools.keys())}" + + def run_react_cycle(self, + initial_prompt: str, + available_tools: Dict, + max_steps: int = 5, + temperature: float = 0.1) -> Dict[str, Any]: + """ + Run ReAct loop + + Args: + initial_prompt: Initial prompt + available_tools: Available tool function dictionary + max_steps: Maximum reasoning steps + temperature: temperature parameter + + Returns: + a dictionary containing the final result and the reasoning history + """ + self.clear_history() + self.add_to_history("user", initial_prompt) + + history = [] + final_answer = None + completed_steps = 0 + + for step in range(max_steps): + print(f"\n=== ReAct Step {step + 1}/{max_steps} ===") + completed_steps = step + 1 + + # Call LLM to obtain response + try: + response = self.client.chat.completions.create( + model=self.model_name, + messages=self.conversation_history, + temperature=temperature, + max_tokens=1024 + ) + + llm_response = response.choices[0].message.content + print(f"LLM Response: {llm_response}") + except Exception as e: + print(f"Error calling LLM: {e}") + llm_response = f"Error in LLM call: {e}" + + # Extract Thought, Action, Action Input + thought, action, action_input = self.extract_thought_action(llm_response) + + step_data = { + "step": step + 1, + "thought": thought, + "action": action, + "action_input": action_input, + "llm_response": llm_response + } + + # Check if it is the final answer + final_answer_detected = False + if "Final Answer:" in llm_response: + final_answer_match = re.search(r'Final Answer:\s*(.*?)$', llm_response, re.DOTALL) + if final_answer_match: + final_answer = final_answer_match.group(1).strip() + step_data["final_answer"] = final_answer + final_answer_detected = True + print(f"Final answer detected at step {step + 1}") + + observation = "" + # Execute actions and obtain observation results + if action and not final_answer_detected: + observation = self.execute_action(action, action_input, available_tools) + step_data["observation"] = observation + + # Update conversation history + self.add_to_history("assistant", llm_response) + self.add_to_history("user", f"Observation: {observation}") + + print(f"Thought: {thought}") + print(f"Action: {action}") + print(f"Action Input: {action_input}") + print(f"Observation: {observation}") + else: + if not final_answer_detected: + # If there is no clear action, it may be during the reasoning process + self.add_to_history("assistant", llm_response) + step_data["observation"] = "No action taken - continuing reasoning" + observation = "No action taken" + else: + # If it is the final answer, no further action is required + step_data["observation"] = "Final answer provided - cycle complete" + observation = "Final answer provided" + + history.append(step_data) + + if final_answer_detected: + print(f" ReAct cycle completed at step {step + 1} with final answer") + break + + # Check if it should end early + if step >= max_steps - 1: + final_answer = f"Reached maximum steps ({max_steps}) without final answer" + print(f" Reached maximum steps without final answer") + break + + if final_answer is None: + final_answer = "No final answer produced" + + return { + "final_answer": final_answer, + "reasoning_history": history, + "success": final_answer is not None and "Reached maximum steps" not in final_answer and "No final answer" not in final_answer, + "completed_steps": completed_steps, + "max_steps": max_steps + } + + class OptimizationWorkflow: def __init__(self, platform: str, design: str, objective: str): self.platform = platform @@ -196,6 +402,974 @@ def __init__(self, platform: str, design: str, objective: str): # Load initial parameters and SDC context self.initial_params = self._load_initial_params() self.sdc_context = self._load_sdc_context() + + emb_np, docs, docsDict = load_embeddings_and_docs() + self.rag_embeddings = torch.tensor(emb_np).cpu() + self.rag_docs = docs + self.rag_docsDict = docsDict + print("[INFO] Loading embedding model...") + model_path = Path(__file__).parent / "models" / "mxbai-embed-large-v1" + model_path = model_path.resolve() + self.rag_model = SentenceTransformer(str(model_path)) + + self.react_framework = ReActFramework( + client=OpenAI( + base_url="https://ai.gitee.com/v1", + api_key= #PUT YOUR KEY HERE, + ), + model_name="DeepSeek-V3" + ) + + def _create_react_tools(self, stage: str, data: Dict[str, Any]) -> Dict: + """Create available utility functions for different stages""" + + base_tools = { + "analyze_data_distribution": lambda x: self._call_existing_distribution_analysis(data), + "analyze_data_structure": lambda x: self._call_existing_structure_analysis(data), + "evaluate_parameter_ranges": lambda x: self._evaluate_parameter_ranges(data), + "check_constraints": lambda x: self._check_constraints_compliance(data), + "suggest_improvements": lambda x: self._suggest_improvements(stage, data), + } + + if stage == 'inspect': + inspection_tools = { + "configure_inspection": lambda config: self._configure_inspection_with_existing(config, data), + "analyze_correlations": lambda params: self._analyze_correlations_with_existing(params, data), + "cluster_analysis": lambda config: self._cluster_analysis_with_existing(config, data), + "manifold_analysis": lambda config: self._manifold_analysis_with_existing(config, data), + "local_structure_analysis": lambda config: self._local_structure_analysis_with_existing(config, data), + } + base_tools.update(inspection_tools) + + elif stage == 'model': + modeling_tools = { + "configure_model": lambda config: self._configure_model_with_existing(config, data), + "evaluate_surrogate": lambda params: self._evaluate_surrogate_with_existing(params, data), + "select_acquisition": lambda method: self._select_acquisition_with_existing(method, data), + "create_surrogate_model": lambda config: self._create_surrogate_model_with_existing(config, data), + "evaluate_timing_model": lambda x: self._evaluate_timing_model_with_existing(data), + "evaluate_wirelength_model": lambda x: self._evaluate_wirelength_model_with_existing(data), + "get_model_recommendations": lambda x: self._get_model_recommendations_from_existing(data), + } + base_tools.update(modeling_tools) + + elif stage == 'agglomerate': + selection_tools = { + "configure_selection": lambda config: self._configure_selection_with_existing(config, data), + "generate_parameters": lambda count: self._generate_parameters_with_existing(count, data), + "validate_parameters": lambda params: self._validate_parameters_tool(params), + "latin_hypercube_sampling": lambda config: self._latin_hypercube_sampling_with_existing(config, data), + "create_quality_scores": lambda config: self._create_quality_scores_with_existing(config, data), + "select_points": lambda config: self._select_points_with_existing(config, data), + "compare_selection_methods": lambda config: self._compare_selection_methods_with_existing(config, data), + "kmeans_selection": lambda config: self._kmeans_selection_with_existing(config, data), + "hybrid_selection": lambda config: self._hybrid_selection_with_existing(config, data), + "entropy_selection": lambda config: self._entropy_selection_with_existing(config, data), + "graph_selection": lambda config: self._graph_selection_with_existing(config, data), + } + base_tools.update(selection_tools) + + return base_tools + + + def _call_existing_distribution_analysis(self, data: Dict) -> str: + """Call existing data distribution analysis functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + result = inspect_data_distribution(X, Y) + return self._format_analysis_result("Data Distribution Analysis", result) + else: + return "Insufficient data for distribution analysis" + + except Exception as e: + return f"Error in distribution analysis: {str(e)}" + + def _call_existing_structure_analysis(self, data: Dict) -> str: + """Call existing data structure analysis functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Use default configuration or retrieve configuration from data + config = { + "n_clusters": 5, + "correlation_threshold": 0.5, + "n_neighbors": 20, + "perplexity": 30 + } + + result = inspect_data_structure(X, Y, config) + return self._format_analysis_result("Data Structure Analysis", result) + else: + return "Insufficient data for structure analysis" + + except Exception as e: + return f"Error in structure analysis: {str(e)}" + + def _evaluate_parameter_ranges(self, data: Dict) -> str: + """Evaluation Parameter Range Tool - Implementation""" + constraints_info = "Parameter Constraints Evaluation:\n" + + # Analyze the current usage of parameters + param_usage = {} + for run in data.get('log_data', {}).get('runs', []): + if run.get('parameters'): + for param, value in run['parameters'].items(): + if param not in param_usage: + param_usage[param] = [] + param_usage[param].append(float(value)) + + for param, info in self.param_constraints.items(): + min_val, max_val = info['range'] + param_type = info['type'] + + constraints_info += f"\n- {param} ({param_type}): range [{min_val}, {max_val}]" + + if param in param_usage: + values = param_usage[param] + used_min = min(values) + used_max = max(values) + constraints_info += f"\n Currently used: [{used_min:.2f}, {used_max:.2f}]" + + # Check if the parameter space has been fully explored + range_used = (used_max - used_min) / (max_val - min_val) + if range_used < 0.5: + constraints_info += f" (Only {range_used*100:.1f}% of range explored)" + + return constraints_info + + def _check_constraints_compliance(self, data: Dict) -> str: + """Check Constraint Compliance Tool - Implementation""" + violations = [] + constraint_checks = [] + + for run in data.get('log_data', {}).get('runs', []): + if run.get('success') and run.get('parameters'): + params = run['parameters'] + + # Check the basic scope constraints + for param, value in params.items(): + if param in self.param_constraints: + constraint = self.param_constraints[param] + min_val, max_val = constraint['range'] + if value < min_val or value > max_val: + violations.append(f"{param}={value} not in [{min_val}, {max_val}]") + + # Check domain constraints + if not self._validate_domain_constraints(params): + violations.append(f"Domain constraints violated for run with params: {params}") + + if violations: + constraint_checks.append(f"Constraint violations found in {len(violations)} cases:") + constraint_checks.extend(violations[:5]) # Only display the first 5 + else: + constraint_checks.append("All parameters comply with constraints") + + # Check the effectiveness of parameter combinations + successful_count = sum(1 for run in data.get('log_data', {}).get('runs', []) + if run.get('success') and run.get('parameters')) + total_with_params = sum(1 for run in data.get('log_data', {}).get('runs', []) + if run.get('parameters')) + + if total_with_params > 0: + success_rate = successful_count / total_with_params * 100 + constraint_checks.append(f"\nParameter success rate: {success_rate:.1f}%") + + return "\n".join(constraint_checks) + + def _suggest_improvements(self, stage: str, data: Dict) -> str: + """Provide improvement suggestions based on stages - implementation""" + suggestions = [] + + if stage == 'inspect': + successful_runs = data.get('log_data', {}).get('summary', {}).get('successful_runs', 0) + total_runs = data.get('log_data', {}).get('summary', {}).get('total_runs', 0) + + suggestions.append(f"Inspection Suggestions for {successful_runs}/{total_runs} successful runs:") + + if successful_runs < total_runs * 0.3: + suggestions.append("- Focus on identifying why runs are failing") + suggestions.append("- Check for common parameter ranges in failed runs") + else: + suggestions.append("- Analyze correlations between parameters and objectives") + suggestions.append("- Identify optimal parameter ranges from successful runs") + + elif stage == 'model': + suggestions.append("Modeling Suggestions:") + suggestions.append("- Use surrogate models for early prediction of results") + suggestions.append("- Balance exploration (trying new regions) and exploitation (refining good regions)") + + # Suggest modeling methods based on data volume + successful_runs = data.get('log_data', {}).get('summary', {}).get('successful_runs', 0) + if successful_runs < 10: + suggestions.append("- With limited data, use simpler models and focus on exploration") + else: + suggestions.append("- With sufficient data, use more complex models and balance exploration/exploitation") + + elif stage == 'agglomerate': + suggestions.append("Parameter Generation Suggestions:") + suggestions.append("- Generate diverse parameter sets to explore different regions") + suggestions.append("- Focus on promising parameter ranges identified in previous stages") + suggestions.append("- Ensure all generated parameters satisfy domain constraints") + + # Suggest strategies based on goals + if self.objective == 'ECP': + suggestions.append("- For ECP, prioritize timing-critical parameters like clk_period and cell padding") + elif self.objective == 'DWL': + suggestions.append("- For DWL, focus on placement and routing parameters") + + return "\n".join(suggestions) + + def _extract_XY_from_data(self, data: Dict) -> Tuple[Optional[np.ndarray], Optional[np.ndarray]]: + """Extracting X and Y arrays from data - Reusing logic in analyze_stetrics""" + feature_vectors = [] + objective_values = [] + + for run in data.get('log_data', {}).get('runs', []): + if run.get('success') and 'metrics' in run: + obj_values = self._calculate_objective(run) + + if obj_values['value'] is not None or obj_values['surrogate'] is not None: + # Extract parameter values as features + params = [] + for param in self.parameter_names: + params.append(float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0)))) + feature_vectors.append(params) + + # Use real values, if not available, use proxy values + objective_values.append(obj_values['value'] if obj_values['value'] is not None else obj_values['surrogate']) + + if feature_vectors and objective_values: + return np.array(feature_vectors), np.array(objective_values) + else: + return None, None + + def _format_analysis_result(self, title: str, result: Dict) -> str: + """Format the analysis result as a readable string""" + formatted = f"=== {title} ===\n" + + for key, value in result.items(): + if key == "model_recommendations": + formatted += "\n--- Model Recommendations ---\n" + for rec_key, rec_value in value.items(): + formatted += f"{rec_key}: {rec_value}\n" + elif isinstance(value, (int, float)): + formatted += f"{key}: {value:.4f}\n" + elif isinstance(value, list) and len(value) > 0 and isinstance(value[0], (int, float)): + # Format numerical list + formatted += f"{key}: [{', '.join(f'{v:.4f}' for v in value[:5])}{'...' if len(value) > 5 else ''}]\n" + else: + formatted += f"{key}: {value}\n" + + return formatted + + def _configure_inspection_with_existing(self, config: Dict, data: Dict) -> str: + """Use existing function configuration to check parameters""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Using configuration to run structural analysis + result = inspect_data_structure(X, Y, config) + + response = f"Inspection configured with: {config}\n" + response += "Key findings:\n" + + # Extract key findings + if "linearity_score" in result: + response += f"- Linearity: {result['linearity_score']:.3f}\n" + if "is_nonlinear" in result: + response += f"- Nonlinear: {result['is_nonlinear']}\n" + if "needs_local_models" in result: + response += f"- Needs local models: {result['needs_local_models']}\n" + if "cluster_sizes" in result: + response += f"- Cluster sizes: {result['cluster_sizes']}\n" + + return response + else: + return "No data available for inspection configuration" + + except Exception as e: + return f"Error in inspection configuration: {str(e)}" + + def _analyze_correlations_with_existing(self, params: Dict, data: Dict) -> str: + """Analyze correlation using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Perform structural analysis to obtain relevant information + config = {"correlation_threshold": params.get('threshold', 0.5)} + result = inspect_data_structure(X, Y, config) + + response = "Feature Correlations Analysis:\n" + + if "feature_importance" in result: + response += "Feature importance (correlation with objective):\n" + for i, importance in enumerate(result["feature_importance"]): + response += f"- {self.parameter_names[i]}: {importance:.3f}\n" + + if "has_correlated_features" in result: + response += f"Has highly correlated features: {result['has_correlated_features']}\n" + if "high_correlation_pairs" in result: + response += f"High correlation pairs: {result['high_correlation_pairs']}\n" + + return response + else: + return "No data available for correlation analysis" + + except Exception as e: + return f"Error in correlation analysis: {str(e)}" + + def _cluster_analysis_with_existing(self, config: Dict, data: Dict) -> str: + """Cluster analysis using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Perform structural analysis to obtain clustering information + result = inspect_data_structure(X, Y, config) + + response = "Cluster Analysis:\n" + + if "cluster_sizes" in result: + response += f"Cluster sizes: {result['cluster_sizes']}\n" + if "cluster_balance" in result: + response += f"Cluster balance: {result['cluster_balance']:.3f}\n" + if "cluster_y_means" in result: + response += "Cluster objective means:\n" + for i, mean in enumerate(result["cluster_y_means"]): + response += f"- Cluster {i}: {mean:.4f}\n" + if "needs_local_models" in result: + response += f"Recommend local models: {result['needs_local_models']}\n" + + return response + else: + return "No data available for cluster analysis" + + except Exception as e: + return f"Error in cluster analysis: {str(e)}" + + def _manifold_analysis_with_existing(self, config: Dict, data: Dict) -> str: + """Perform manifold analysis using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None: + result = analyze_manifold_structure(X, config) + return self._format_analysis_result("Manifold Structure Analysis", result) + else: + return "No data available for manifold analysis" + + except Exception as e: + return f"Error in manifold analysis: {str(e)}" + + def _local_structure_analysis_with_existing(self, config: Dict, data: Dict) -> str: + """Using existing functions for local structure analysis""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None: + result = analyze_local_structure(X, config) + return self._format_analysis_result("Local Structure Analysis", result) + else: + return "No data available for local structure analysis" + + except Exception as e: + return f"Error in local structure analysis: {str(e)}" + + def _get_model_recommendations_from_existing(self, data: Dict) -> str: + """Obtain model recommendations from existing analysis""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + result = inspect_data_structure(X, Y) + + if "model_recommendations" in result: + recommendations = result["model_recommendations"] + response = "Model Recommendations from Data Analysis:\n" + + for key, value in recommendations.items(): + if key == "feature_weights" and isinstance(value, list): + response += f"{key}: [" + response += ", ".join(f"{w:.3f}" for w in value[:5]) + if len(value) > 5: + response += ", ..." + response += "]\n" + else: + response += f"{key}: {value}\n" + + return response + else: + return "No model recommendations available" + else: + return "No data available for model recommendations" + + except Exception as e: + return f"Error getting model recommendations: {str(e)}" + + + def _configure_model_with_existing(self, config: Dict, data: Dict) -> str: + """Configure the model using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Create a model using configuration + kernel_type = config.get('kernel_type', 'matern') + preprocessing = config.get('preprocessing', 'standard') + acquisition = config.get('acquisition', 'ei') + + # Create Preprocessor + preprocessor = create_preprocessor(preprocessing) + + # Create acquisition function + acq_function = create_acquisition_function(acquisition) + + response = f"Model configured successfully:\n" + response += f"- Kernel type: {kernel_type}\n" + response += f"- Preprocessing: {preprocessing}\n" + response += f"- Acquisition function: {acquisition}\n" + response += f"- Data shape: {X.shape}\n" + + # If the amount of data is sufficient, a model can be created for testing + if len(X) >= 2: + model = create_model(X, Y, kernel_type=kernel_type) + response += f"- Model created successfully with {len(X)} samples\n" + else: + response += f"- Insufficient data for model creation (need at least 2 samples, have {len(X)})\n" + + return response + else: + return "No data available for model configuration" + + except Exception as e: + return f"Error in model configuration: {str(e)}" + + def _evaluate_surrogate_with_existing(self, params: Dict, data: Dict) -> str: + """Evaluate the proxy model using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Extract proxy values (if any) + surrogate_values = None + if 'surrogates' in data.get('metrics', {}): + surrogate_values = np.array(data['metrics']['surrogates']) + + # Use existing functions to process proxy data + if surrogate_values is not None: + X_processed, y_combined, uncertainty = handle_surrogate_data(X, Y, surrogate_values) + + response = "Surrogate Model Evaluation:\n" + response += f"- Original data points: {len(Y)}\n" + response += f"- Valid target values: {np.sum(~np.isnan(Y))}\n" + response += f"- Surrogate values used: {np.sum(np.isnan(Y))}\n" + response += f"- Combined data points: {len(y_combined)}\n" + + if len(uncertainty) > 0: + response += f"- Average surrogate uncertainty: {np.mean(uncertainty):.4f}\n" + + return response + else: + return "No surrogate data available for evaluation" + else: + return "No data available for surrogate evaluation" + + except Exception as e: + return f"Error in surrogate evaluation: {str(e)}" + + def _select_acquisition_with_existing(self, method: str, data: Dict) -> str: + """Use existing functions to select collection functions""" + try: + # Create a collection function using an existing function + acq_function = create_acquisition_function(method) + + response = f"Acquisition function selected: {method.upper()}\n" + + # Provide explanations for different collection functions + explanations = { + 'ei': "Expected Improvement - balances improvement probability and magnitude", + 'ucb': "Upper Confidence Bound - favors exploration of uncertain regions", + 'pi': "Probability of Improvement - focuses on areas likely to improve", + 'augmented_ei': "Augmented EI - combines EI with exploration bonus" + } + + response += f"Explanation: {explanations.get(method, 'No explanation available')}\n" + + # Provide recommendations based on data characteristics + X, Y = self._extract_XY_from_data(data) + if X is not None and Y is not None: + if len(Y) < 10: + response += "Recommendation: With limited data, consider using UCB for better exploration\n" + else: + response += "Recommendation: With sufficient data, EI or Augmented EI are good choices\n" + + return response + + except Exception as e: + return f"Error in acquisition function selection: {str(e)}" + + def _create_surrogate_model_with_existing(self, config: Dict, data: Dict) -> str: + """Create a proxy model using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + kernel_type = config.get('kernel_type', 'matern') + noise_level = config.get('noise_level', 1e-6) + + # Create a model using existing functions + model = create_model(X, Y, noise_level=noise_level, kernel_type=kernel_type) + + response = f"Surrogate Model Created:\n" + response += f"- Kernel: {kernel_type}\n" + response += f"- Data points: {len(X)}\n" + response += f"- Features: {X.shape[1]}\n" + response += f"- Kernel parameters: {model.kernel_}\n" + + # Test model prediction + if len(X) > 0: + predictions, stds = predict_with_model(model, X[:1]) # Test a point + response += f"- Test prediction successful\n" + response += f"- Prediction range: [{predictions[0]:.4f} ± {stds[0]:.4f}]\n" + + return response + else: + return "No data available for model creation" + + except Exception as e: + return f"Error in surrogate model creation: {str(e)}" + + def _evaluate_timing_model_with_existing(self, data: Dict) -> str: + """Evaluate timing models using existing functions""" + try: + # Build context + context = { + 'log_data': data.get('log_data', {}), + 'metrics': data.get('metrics', {}), + 'model_recommendations': data.get('model_recommendations', {}) + } + + # Evaluate timing models using existing functions + results = evaluate_timing_model(context) + + response = "Timing Model Evaluation:\n" + + if 'performance' in results: + for key, value in results['performance'].items(): + response += f"- {key}: {value:.4f}\n" + + if 'suggestions' in results: + response += "\nSuggestions:\n" + for suggestion in results['suggestions']: + response += f"- {suggestion}\n" + + if 'recommendations' in results: + response += "\nRecommendations:\n" + for key, value in results['recommendations'].items(): + response += f"- {key}: {value}\n" + + return response + + except Exception as e: + return f"Error in timing model evaluation: {str(e)}" + + def _evaluate_wirelength_model_with_existing(self, data: Dict) -> str: + """Evaluate the wire length model using existing functions""" + try: + # Build context + context = { + 'log_data': data.get('log_data', {}), + 'metrics': data.get('metrics', {}), + 'model_recommendations': data.get('model_recommendations', {}) + } + + # Evaluate the wire length model using existing functions + results = evaluate_wirelength_model(context) + + response = "Wirelength Model Evaluation:\n" + + if 'performance' in results: + for key, value in results['performance'].items(): + response += f"- {key}: {value:.4f}\n" + + if 'suggestions' in results: + response += "\nSuggestions:\n" + for suggestion in results['suggestions']: + response += f"- {suggestion}\n" + + if 'recommendations' in results: + response += "\nRecommendations:\n" + for key, value in results['recommendations'].items(): + response += f"- {key}: {value}\n" + + return response + + except Exception as e: + return f"Error in wirelength model evaluation: {str(e)}" + + def _generate_parameters_with_existing(self, count: int, data: Dict) -> str: + """Generate parameters using existing functions""" + try: + if count <= 0 or count > 50: + return "Error: count must be between 1 and 50" + + # Obtain parameter dimensions + n_dims = len(self.parameter_names) + + # Use existing Latin hypercube sampling + samples = latin_hypercube(count, n_dims) + + response = f"Parameter Generation using Latin Hypercube:\n" + response += f"- Samples generated: {count}\n" + response += f"- Parameter dimensions: {n_dims}\n" + response += f"- Sampling method: Latin Hypercube\n" + + # Display parameter range information + response += "\nParameter Ranges:\n" + for i, param in enumerate(self.parameter_names): + constraint = self.param_constraints[param] + min_val, max_val = constraint['range'] + response += f"- {param}: [{min_val}, {max_val}] ({constraint['type']})\n" + + return response + + except Exception as e: + return f"Error in parameter generation: {str(e)}" + + def _latin_hypercube_sampling_with_existing(self, config: Dict, data: Dict) -> str: + """Using existing functions for Latin hypercube sampling""" + try: + n_points = config.get('n_points', 10) + n_dims = len(self.parameter_names) + + # Use the existing Latin hypercube sampling function + samples = latin_hypercube(n_points, n_dims) + + response = f"Latin Hypercube Sampling:\n" + response += f"- Points: {n_points}\n" + response += f"- Dimensions: {n_dims}\n" + response += f"- Sample shape: {samples.shape}\n" + + # Display sampling statistics + response += f"- Sample range: [{samples.min():.3f}, {samples.max():.3f}]\n" + response += f"- Sample mean: {samples.mean():.3f}\n" + response += f"- Sample std: {samples.std():.3f}\n" + + return response + + except Exception as e: + return f"Error in Latin hypercube sampling: {str(e)}" + + def _configure_selection_with_existing(self, config: Dict, data: Dict) -> str: + """Configure selection strategy using existing functions""" + try: + method = config.get('method', 'hybrid') + quality_weight = config.get('quality_weight', 0.7) + uncertainty_bonus = config.get('uncertainty_bonus', 0.2) + n_points = config.get('n_points', 10) + + response = f"Selection Strategy Configured:\n" + response += f"- Method: {method}\n" + response += f"- Quality weight: {quality_weight}\n" + response += f"- Uncertainty bonus: {uncertainty_bonus}\n" + response += f"- Points to select: {n_points}\n" + + # Provide explanations for different methods + method_descriptions = { + "kmeans": "K-means clustering - selects best point from each cluster", + "hybrid": "Hybrid approach - balances quality and diversity", + "entropy": "Entropy-based - maximizes information diversity", + "graph": "Graph-based - uses network centrality measures" + } + + response += f"Method description: {method_descriptions.get(method, 'No description')}\n" + + return response + + except Exception as e: + return f"Error in selection configuration: {str(e)}" + + + def _create_quality_scores_with_existing(self, config: Dict, data: Dict) -> str: + """Create a quality score using an existing function""" + try: + # Extract necessary information from data + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Simulation model predictions and uncertainties (in practical use, these should come from real models) + model_predictions = Y # Using real values as a proxy for prediction + model_uncertainties = np.ones_like(Y) * 0.1 # Simulate uncertainty + + # Create a quality score using an existing function + quality_scores = create_quality_scores(X, Y, model_predictions, model_uncertainties) + + response = "Quality Scores Created:\n" + response += f"- Data points: {len(X)}\n" + response += f"- Quality score range: [{quality_scores.min():.4f}, {quality_scores.max():.4f}]\n" + response += f"- Quality score mean: {quality_scores.mean():.4f}\n" + response += f"- Quality score std: {quality_scores.std():.4f}\n" + + response += f"- First 5 quality scores: {quality_scores[:5].tolist()}\n" + + if 'selection_data' not in data: + data['selection_data'] = {} + data['selection_data']['quality_scores'] = quality_scores + data['selection_data']['X'] = X + data['selection_data']['Y'] = Y + + return response + else: + return "No data available for quality score creation" + + except Exception as e: + return f"Error in quality score creation: {str(e)}" + + def _select_points_with_existing(self, config: Dict, data: Dict) -> str: + """_select_points_with_existing""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + method = config.get('method', 'hybrid') + n_points = config.get('n_points', 10) + quality_weight = config.get('quality_weight', 0.7) + + selection_config = { + "quality_weight": quality_weight, + "uncertainty_bonus": config.get('uncertainty_bonus', 0.2) + } + + selected_indices = select_points( + X, quality_scores, + method=method, + n_points=n_points, + config=selection_config + ) + + response = f"Points Selected using {method.upper()} method:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Selected quality scores: {selected_qualities.tolist()}\n" + response += f"- Average quality of selected: {selected_qualities.mean():.4f}\n" + + # store selection data + data['selection_data']['selected_indices'] = selected_indices + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in point selection: {str(e)}" + + def _compare_selection_methods_with_existing(self, config: Dict, data: Dict) -> str: + """compare selection methods with existing(""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 5) + methods = ['kmeans', 'hybrid', 'entropy', 'graph'] + + response = "Selection Method Comparison:\n" + response += f"- Comparing {len(methods)} methods\n" + response += f"- Points to select: {n_points}\n\n" + + for method in methods: + try: + selected_indices = select_points( + X, quality_scores, + method=method, + n_points=n_points + ) + + selected_qualities = quality_scores[selected_indices] + + response += f"**{method.upper()}**:\n" + response += f" - Selected indices: {selected_indices.tolist()}\n" + response += f" - Avg quality: {selected_qualities.mean():.4f}\n" + response += f" - Quality range: [{selected_qualities.min():.4f}, {selected_qualities.max():.4f}]\n" + + except Exception as e: + response += f"**{method.upper()}**: Error - {str(e)}\n" + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in method comparison: {str(e)}" + + def _kmeans_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using K-means selection method""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + + # using K-means selecting function + selected_indices = kmeans_select(X, quality_scores, n_points) + + response = "K-means Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + response += f"- Quality diversity: {selected_qualities.std():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'kmeans' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in K-means selection: {str(e)}" + + def _hybrid_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using existing hybrid selection method""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + quality_weight = config.get('quality_weight', 0.7) + + distance_matrix = cdist(X, X) + + # using hybrid_select function + selected_indices = hybrid_select( + X, quality_scores, distance_matrix, + n_points, quality_weight + ) + + response = "Hybrid Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Quality weight: {quality_weight}\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + + selected_points = X[selected_indices] + min_distances = np.min(cdist(selected_points, selected_points) + np.eye(len(selected_points)) * 1e6, axis=1) + response += f"- Minimum inter-point distance: {min_distances.mean():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'hybrid' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in hybrid selection: {str(e)}" + + def _entropy_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using existing entropy selecting methods""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + + # using entropy selecting function + selected_indices = entropy_select(X, quality_scores, n_points) + + response = "Entropy-based Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'entropy' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in entropy selection: {str(e)}" + + def _graph_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using existing graph selection method""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + + # using graph selecting function + selected_indices = graph_select(X, quality_scores, n_points) + + response = "Graph-based Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'graph' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in graph selection: {str(e)}" + + + def _validate_parameters_tool(self, params: Dict) -> str: + validation_results = [] + + for param_name, value in params.items(): + if param_name in self.param_constraints: + constraint = self.param_constraints[param_name] + min_val, max_val = constraint['range'] + param_type = constraint['type'] + + if value < min_val or value > max_val: + validation_results.append(f" {param_name}={value} outside range [{min_val}, {max_val}]") + else: + validation_results.append(f" {param_name}={value} within valid range") + + if self._validate_domain_constraints(params): + validation_results.append("Domain constraints satisfied") + else: + validation_results.append("Domain constraints violated") + + return "Parameter Validation:\n" + "\n".join(validation_results) + def _load_config(self) -> Dict[str, Any]: """Load the configuration from 'opt_config.json'.""" @@ -249,41 +1423,40 @@ def _load_sdc_context(self) -> Dict[str, Any]: return sdc_context + def _generate_llm_prompt(self, stage: str, data: Dict[str, Any]) -> str: - """Generate LLM prompt for different stages""" - # Include parameter constraints in the prompt constraints_text = "Parameter Constraints:\n" for param, info in self.param_constraints.items(): param_type = info['type'] param_range = info['range'] constraints_text += f"- {param} ({param_type}, range: {param_range})\n" - # Construct the prompt based on the stage - if stage == 'inspect': - prompt = ( + tool_instructions = { + 'inspect': ( f"**Stage: Inspect**\n" "In this stage, we analyze the data from previous optimization runs to identify patterns, trends, and insights.\n\n" - f"Data to analyze:\n{json.dumps(data, indent=2)}\n\n" + f"Data to analyze:\n{json.dumps(data, indent=2, default=str)}\n\n" "Please analyze the data and provide insights on:\n" "1. Key patterns in successful vs unsuccessful runs.\n" "2. Parameter ranges that appear promising.\n" "3. Any timing or wirelength trends.\n" "4. Recommendations for subsequent runs.\n" - ) - elif stage == 'model': - prompt = ( + "5. We hope to further reduce the total wirelength.\n" + ), + + 'model': ( f"**Stage: Model**\n" "In this stage, we decide how to model the optimization problem based on the data analysis.\n\n" - f"Data for modeling:\n{json.dumps(data, indent=2)}\n\n" + f"Data for modeling:\n{json.dumps(data, indent=2, default=str)}\n\n" "Please suggest:\n" "1. Appropriate modeling techniques.\n" "2. Key parameters to focus on.\n" "3. Surrogate model recommendations.\n" "4. Acquisition function choices.\n" - ) - elif stage == 'agglomerate': - prompt = ( + ), + + 'agglomerate': ( f"**Stage: Agglomerate**\n" "In this stage, we generate new parameter combinations to explore in the next optimization runs.\n\n" "Please provide a list of new parameter sets to try, ensuring they respect the domain constraints below.\n\n" @@ -291,181 +1464,394 @@ def _generate_llm_prompt(self, stage: str, data: Dict[str, Any]) -> str: "Each parameter set should be a dictionary with parameter names and their suggested values.\n" "**Important:** Make sure all parameter sets satisfy the domain constraints before suggesting them.\n" ) - else: - prompt = ( - f"**Stage: {stage.capitalize()}**\n" - f"Data:\n{json.dumps(data, indent=2)}\n\n" - "Please provide guidance based on the above data.\n" - ) + } + + stage_contexts = { + 'inspect': ( + f"metrics analyze: Total runs={data.get('log_data', {}).get('summary', {}).get('total_runs', 0)}, " + f"successful runs ={data.get('log_data', {}).get('summary', {}).get('successful_runs', 0)}" + ), + 'model': "Configure modeling methods based on inspection results", + 'agglomerate': "Configure parameter selection strategy based on modeling results" + } + + prompt = f"""**stages:{stage.upper()}** - return prompt + {stage_contexts.get(stage, '')} + + {tool_instructions.get(stage, '')} + + **Important: Use only tool calls and do not generate text replies!** + """ + + # ========= Splicing RAG ========= + rag_context = "" + if self.rag_model is not None and self.rag_embeddings is not None: + try: + print("[DEBUG] RAG: Starting retrieval...") + + # Step 1: Extract error information + error_summary = "" + if "log_data" in data: + all_errors = [] + for run in data["log_data"].get("runs", []): + if run.get("errors"): + all_errors.extend(run["errors"]) + if all_errors: + # Retrieve the most recent or frequent errors + top_errors = all_errors[-3:] # Last 3 posts + error_summary = "\n".join(top_errors) + print(f"[DEBUG] Detected {len(all_errors)} error messages. Sample:\n{error_summary}") + + # Step 2: Construct RAG query + if error_summary: + query = ( + f"Stage: {stage}. Objective: {self.objective}. " + f"The recent optimization runs failed with errors:\n{error_summary}\n\n" + "Retrieve relevant OpenROAD documentation, known failure modes, and " + "potential parameter tuning suggestions that may fix these issues." + ) + else: + query = ( + f"Stage: {stage}. Objective: {self.objective}. " + f"Focus on analyzing {stage}-related optimization results. " + f"Important metrics include wirelength, timing, area, and success rate. " + f"Find relevant OpenROAD documentation, parameter tuning guides, and failure pattern examples." + ) + + # Step 3: Execute search + rag_context = answerWithRAG( + query, + self.rag_embeddings, + self.rag_model, + self.rag_docs, + self.rag_docsDict, + ) + + if isinstance(rag_context, dict): # If returning dict + print(f"[DEBUG] RAG Retrieved {len(rag_context.get('docs', []))} related entries.") + for doc in rag_context.get("docs", [])[:3]: + print(f" ↳ {doc['title']} (score={doc['score']:.3f}) from {doc['source']}") + retrieved_text = rag_context.get("content", "") + else: + retrieved_text = rag_context + + # Step 4: add to prompt + if retrieved_text.strip(): + prompt += ( + "\n\n=== Retrieved OpenROAD Documentation (via RAG) ===\n" + f"{retrieved_text}\n" + "==============================================" + ) + print("[DEBUG] RAG: Context successfully added to prompt.") + else: + print("[DEBUG] RAG: Empty context retrieved.") + except Exception as e: + prompt += f"\n\n[WARN] RAG retrieval failed: {e}" + + if "log_data" in data: + all_errors = [] + for run in data["log_data"].get("runs", []): + if run.get("errors"): + all_errors.extend(run["errors"]) + + if all_errors: + error_summary = "\n".join(all_errors[-5:]) # The last 5 errors + prompt += f""" + + ### Detected Run Errors + {error_summary} + + The model must now act as an **EDA Debugging Assistant**. + Using the retrieved documentation and knowledge, analyze the errors above and: + 1. Identify the root causes of each error (e.g., tool misconfiguration, parameter overflow, timing issues, etc.) + 2. Suggest **specific parameter changes or flow adjustments** to prevent these errors. + 3. Indicate whether the error is likely due to constraints, routing congestion, or timing margin. + 4. Provide a short explanation for each suggestion. + + Output format: + Error Diagnosis: + - Root Cause: ... + - Recommended Fix: ... + - Suggested Parameter Change: ... + - Reason: ... + + """ + print("[DEBUG] Added error-fix section to prompt.") + def _collect_recent_errors(self, data: Dict[str, Any], max_errors=5) -> str: + errors = [] + for run in data.get("log_data", {}).get("runs", []): + if run.get("errors"): + errors.extend(run["errors"]) + print(f"[DEBUG] Found total {len(errors)} errors in all runs.") + return "\n".join(errors[-max_errors:]) if errors else "No errors detected." def _call_llm(self, stage: str, data: Dict[str, Any]) -> Dict[str, Any]: - """Call Claude to get recommendations for optimization parameters""" - print(f"\n=== Calling LLM for {stage} stage ===") - - # Hardcode API key - api_key = #PUT YOUR KEY HERE - - client = anthropic.Anthropic(api_key=api_key) - - tools = [ - { - "name": "configure_inspection", - "description": "Configure data inspection parameters", - "input_schema": { - "type": "object", - "properties": { - "n_clusters": { - "type": "integer", - "description": "Number of clusters for structure analysis", - "minimum": 2, - "maximum": 10 - }, - "correlation_threshold": { - "type": "number", - "description": "Threshold for considering correlations significant", - "minimum": 0, - "maximum": 1 - } - }, - "required": ["n_clusters", "correlation_threshold"] - } - }, - { - "name": "configure_model", - "description": "Configure modeling approach", - "input_schema": { - "type": "object", - "properties": { - "kernel_type": { - "type": "string", - "enum": ["rbf", "matern", "rational"], - "description": "Type of kernel to use" - }, - "preprocessing": { - "type": "string", - "enum": ["standard", "robust", "none"], - "description": "Type of preprocessing to apply" - }, - "acquisition": { - "type": "string", - "enum": ["ei", "ucb", "pi"], - "description": "Acquisition function to use" - }, - "surrogate_weight": { - "type": "number", - "description": "Weight to give surrogate values", - "minimum": 0, - "maximum": 1 - } - }, - "required": ["kernel_type", "preprocessing", "acquisition", "surrogate_weight"] - } - }, - { - "name": "configure_selection", - "description": "Configure point selection strategy", - "input_schema": { - "type": "object", - "properties": { - "method": { - "type": "string", - "enum": ["entropy", "kmeans", "hybrid", "graph"], - "description": "Selection method to use" - }, - "quality_weight": { - "type": "number", - "description": "Weight between quality and diversity", - "minimum": 0, - "maximum": 1 - }, - "uncertainty_bonus": { - "type": "number", - "description": "Weight for uncertainty in quality scores", - "minimum": 0, - "maximum": 1 - } - }, - "required": ["method", "quality_weight", "uncertainty_bonus"] - } + # """Call Claude to get recommendations for optimization parameters""" + # print(f"\n=== Calling LLM for {stage} stage ===") + """Call LLM to get recommendations for optimization parameters using react framework""" + print(f"\n=== Calling LLM with ReAct framework for {stage} stage ===") + + try: + react_prompt = self._generate_react_prompt(stage, data) + print(f"Generated prompt with context for {stage}") + print("=== Context Message ===") + print(react_prompt) + print("========================") + available_tools = self._create_react_tools(stage, data) + + react_result = self.react_framework.run_react_cycle( + initial_prompt=react_prompt, + available_tools=available_tools, + max_steps=3, + temperature=0.1 + ) + # === If an error occurs, enter Debug mode === + if "log_data" in data and any(run.get("errors") for run in data["log_data"].get("runs", [])): + print("\n[DEBUG] Detected errors in previous runs. Invoking Debug Assistant mode...") + + # Collect error information + all_errors = [] + for run in data["log_data"]["runs"]: + if run.get("errors"): + all_errors.extend(run["errors"]) + error_text = "\n".join(all_errors[-5:]) # Recent entries + + # Construct a Debug Prompt + debug_prompt = f""" + You are now an **EDA Debugging Expert**. + Based on the following OpenROAD errors and RAG documentation, analyze and provide concrete repair suggestions. + + Errors Detected: + {error_text} + + Please identify: + 1. Root cause of each error. + 2. Specific parameter changes (e.g., in floorplan, CTS, or routing stages) that could fix the issue. + 3. Whether this issue is due to timing, congestion, or setup misconfiguration. + 4. One short explanation per fix. + + Return your answer in **JSON format** like: + {{ + "error_analysis": [ + {{ + "error": "...", + "cause": "...", + "fix": "...", + "params_to_adjust": {{"param_name": "new_value"}} + }} + ] + }} + """ + + # Call LLM to output repair suggestions + debug_result = self.react_framework.run_react_cycle( + initial_prompt=debug_prompt, + available_tools=available_tools, + max_steps=2, + temperature=0.2 + ) + + print("\n[DEBUG] LLM Debug Assistant Result:") + print(debug_result.get("final_answer", "")) + + # Save repair suggestions to the main results + react_result["error_fix_suggestions"] = debug_result.get("final_answer", "") + # Write files for manual viewing + with open("logs/error_fix_suggestions.json", "w") as f: + f.write(debug_result.get("final_answer", "")) + print(f"\n=== ReAct Cycle Completed ===") + print(f"Completed steps: {react_result.get('completed_steps', 0)}/{react_result.get('max_steps', 8)}") + print(f"Final Answer: {react_result['final_answer']}") + + configs = self._parse_react_final_answer(react_result["final_answer"], stage) + + if react_result.get('reasoning_history'): + print(f"\n=== Reasoning History ({len(react_result['reasoning_history'])} steps) ===") + for step in react_result['reasoning_history']: + print(f"Step {step['step']}: {step.get('thought', 'No thought')}") + + print(f"Returning config for stage '{stage}': {configs}") + return configs + + except Exception as e: + print(f"Error in LLM call for stage {stage}: {e}") + default_config = { + 'inspect': {"n_clusters": 5, "correlation_threshold": 0.5}, + 'model': {"kernel_type": "matern", "preprocessing": "robust", + "acquisition": "ei", "surrogate_weight": 0.8}, + 'agglomerate': {"method": "hybrid", "quality_weight": 0.7, + "uncertainty_bonus": 0.2} } - ] + return default_config.get(stage, {}) + - # Get data summaries - if stage == 'inspect': - print("Generating data distribution and structure summaries...") - # Extract X and Y from successful runs if available - X = [] - Y = [] - if 'log_data' in data and 'runs' in data['log_data']: - for run in data['log_data']['runs']: - if run['success'] and 'metrics' in run: - obj = self._calculate_objective(run) - if obj['value'] is not None or obj['surrogate'] is not None: - # Use parameters as X - params = [] - for param in self.param_constraints.keys(): - params.append(float(run.get('parameters', {}).get(param, 0))) - X.append(params) - # Use objective as Y - Y.append(obj['value'] if obj['value'] is not None else obj['surrogate']) - - if X and Y: - dist_summary = inspect_data_distribution(np.array(X), np.array(Y)) - struct_summary = inspect_data_structure(np.array(X)) - else: - print("No successful runs found, using empty summaries") - dist_summary = {} - struct_summary = {} + def _generate_react_prompt(self, stage: str, data: Dict[str, Any]) -> str: + """generate prompts of ReAct framework""" + + stage_descriptions = { + 'inspect': ( + "You are an expert EDA optimization analyst. Analyze the optimization run data to identify patterns " + "and insights. Use the available tools to examine data distributions, correlations, and successful " + "parameter ranges. Your goal is to understand what makes runs successful and provide recommendations " + "for the modeling stage." + ), + 'model': ( + "You are an expert machine learning engineer for EDA optimization. Based on the inspection results, " + "configure the modeling approach for Bayesian optimization. Consider kernel selection, acquisition " + "functions, and surrogate modeling strategies. Balance exploration and exploitation based on the data." + ), + 'agglomerate': ( + "You are an expert parameter optimization specialist. Generate new parameter combinations for the " + "next optimization iteration. Use insights from previous stages to focus on promising regions while " + "maintaining diversity. Ensure all parameters satisfy the domain constraints." + ) + } + + constraints_text = "Parameter Constraints:\n" + for param, info in self.param_constraints.items(): + constraints_text += f"- {param} ({info['type']}, range: {info['range']})\n" + + react_format_instructions = """ +**ReAct Framework Instructions - MUST FOLLOW THIS FORMAT:** + +1. **Thought**: Analyze the current situation and decide what to do next +2. **Action**: Choose one tool from the available tools +3. **Action Input**: Provide the appropriate input for the chosen tool +4. **Observation**: Wait for the tool's response, then continue reasoning + +**Available Tools**: You have access to various analysis tools. Use them to gather information before making decisions. + +**DO NOT include Final Answer until you have completed all necessary analysis.** +**DO NOT predict or simulate tool observations.** +**You will receive actual Observation from tools before continuing.** + +Only after proper analysis: +**Final Answer Format**: Only when you have completed your analysis, provide: +Final Answer: {your_configuration_here} + +**Example**: +Thought: I need to understand the data patterns first. Let me analyze the success rates. +Action: analyze_data_patterns +Action Input: {} +Observation: [Tool response...] +Thought: Now I need to check parameter correlations... +Action: analyze_correlations +Action Input: {} +Observation: [Tool response...] +Final Answer: {"n_clusters": 5, "correlation_threshold": 0.7} +""" + + prompt = f""" + {stage_descriptions[stage]} + + **Current Stage**: {stage.upper()} + **Objective**: {self.objective} + **Platform**: {self.platform} + **Design**: {self.design} + + **Available Data**: + - Total runs: {data.get('log_data', {}).get('summary', {}).get('total_runs', 0)} + - Successful runs: {data.get('log_data', {}).get('summary', {}).get('successful_runs', 0)} + - Failed runs: {data.get('log_data', {}).get('summary', {}).get('failed_runs', 0)} + + {constraints_text} + {react_format_instructions} + + Begin your analysis: + """ + + rag_context = "" + # ======== extract errors ======== + error_summary = self._collect_recent_errors(data) + if error_summary and "No errors" not in error_summary: + print("[DEBUG] RAG: Detected error summary, adding error analysis prompt...") + prompt += f""" + + ### Detected Run Errors + {error_summary} + + You are now acting as an **EDA Debugging Assistant**. + Analyze the errors above and: + 1. Identify the root causes. + 2. Suggest specific parameter changes. + 3. Indicate whether the error is due to timing, routing, or constraints. + 4. Provide short explanations for each. + + Output format: + Error Diagnosis: + - Root Cause: ... + - Recommended Fix: ... + - Suggested Parameter Change: ... + - Reason: ... + """ else: - dist_summary = {} - struct_summary = {} - - # Generate context message - context_message = self._generate_llm_prompt(stage, data) - print(f"Generated prompt with context for {stage}") - - print("Making LLM API call...") - response = client.messages.create( - model="claude-3-sonnet-20240229", - max_tokens=2048, - tools=tools, - messages=[{ - "role": "user", - "content": context_message - }] - ) + print("[DEBUG] No errors found in logs for this stage.") + if self.rag_model is not None and self.rag_embeddings is not None: + try: + print("[DEBUG] RAG: Starting retrieval...") + query = ( + f"Stage: {stage}. Objective: {self.objective}. " + f"Focus on analyzing {stage}-related optimization results. " + f"Important metrics include wirelength, timing, area, and success rate. " + f"Find relevant OpenROAD documentation, parameter tuning guides, and failure pattern examples." + ) + rag_context = answerWithRAG( + query, + self.rag_embeddings, + self.rag_model, + self.rag_docs, + self.rag_docsDict + ) + print(f"[DEBUG] RAG: Retrieved context length = {len(rag_context)}") + if rag_context.strip(): + prompt += ( + "\n\n=== Retrieved OpenROAD Documentation (via RAG) ===\n" + f"{rag_context}\n" + "==============================================" + ) + print("[DEBUG] RAG: Context successfully added to prompt.") + else: + print("[DEBUG] RAG: Empty context retrieved.") + except Exception as e: + prompt += f"\n\n[WARN] RAG retrieval failed: {e}" - # Extract configurations + return prompt + + def _parse_react_final_answer(self, final_answer: str, stage: str) -> Dict[str, Any]: + """parse react final answer""" + + default_configs = { + 'inspect': {"n_clusters": 5, "correlation_threshold": 0.5}, + 'model': {"kernel_type": "matern", "preprocessing": "robust", + "acquisition": "ei", "surrogate_weight": 0.8}, + 'selection': {"method": "hybrid", "quality_weight": 0.7, + "uncertainty_bonus": 0.2} + } + configs = {} - print("\nReceived tool calls from LLM:") - for block in response.content: - if block.type == 'tool_use': - print(f"- {block.name}: {block.input}") - if block.name == 'configure_inspection': - configs['inspection'] = block.input - elif block.name == 'configure_model': - configs['model'] = block.input - elif block.name == 'configure_selection': - configs['selection'] = block.input - - # Add default configs if missing - for key, default in [ - ('inspection', {"n_clusters": 5, "correlation_threshold": 0.5}), - ('model', {"kernel_type": "matern", "preprocessing": "robust", - "acquisition": "ei", "surrogate_weight": 0.8}), - ('selection', {"method": "hybrid", "quality_weight": 0.7, - "uncertainty_bonus": 0.2}) - ]: - if key not in configs: - print(f"Warning: No {key} config from LLM, using defaults: {default}") - configs[key] = default + + if final_answer and "Reached maximum steps" not in final_answer: + try: + json_match = re.search(r'\{.*\}', final_answer, re.DOTALL) + if json_match: + extracted_config = json.loads(json_match.group()) + configs[stage] = extracted_config + print(f"✓ Extracted configuration from ReAct response: {extracted_config}") + else: + configs[stage] = default_configs.get(stage, {}) + print(f"⚠ Using default configuration for {stage} stage") + except Exception as e: + print(f"Error parsing ReAct final answer: {e}") + configs[stage] = default_configs.get(stage, {}) + else: + configs[stage] = default_configs.get(stage, {}) + print(f"ReAct failed to produce answer, using default for {stage}") return configs def run_iteration(self, num_runs: int) -> None: - """Run a complete iteration of the optimization workflow""" + """Run a complete iteration of the optimization workflow using react framework""" print(f"\n=== Starting optimization iteration for {self.platform}/{self.design} ===") print(f"Objective: {self.objective}") print(f"Number of runs requested: {num_runs}") @@ -477,25 +1863,29 @@ def run_iteration(self, num_runs: int) -> None: f"{log_data['summary']['successful_runs']} successful") # Get LLM recommendations for inspection and analysis - print("\nGetting LLM recommendations for inspection...") + # print("\nGetting LLM recommendations for inspection...") + print("\nGetting LLM recommendations with ReAct framework for inspection...") inspect_configs = self._call_llm('inspect', { 'log_data': log_data, 'initial_params': self.initial_params, 'sdc_context': self.sdc_context }) - print(f"LLM inspection config: {inspect_configs['inspection']}") + inspection_config = inspect_configs.get('inspect', {}) + print(f"React inspection config: {inspection_config}") # Step 2: Analyze metrics with LLM config - print("\nStep 2: Analyzing metrics...") + print("\nStep 2: Analyzing metrics ...") metrics = self.analyze_metrics( log_data, - n_clusters=inspect_configs['inspection']['n_clusters'], - correlation_threshold=inspect_configs['inspection']['correlation_threshold'] + # n_clusters=inspect_configs['inspection']['n_clusters'], + n_clusters=inspection_config.get('n_clusters', 5), + # correlation_threshold=inspect_configs['inspection']['correlation_threshold'] + correlation_threshold=inspection_config.get('correlation_threshold', 0.5) ) print(f"Processed metrics for {len(metrics.get('objectives', []))} successful runs") - # Get LLM recommendations for modeling based on inspection results - print("\nGetting LLM recommendations for modeling...") + # Get LLM recommendations for modeling based on inspection results with ReAct framework + print("\nGetting LLM recommendations with ReAct framework for modeling...") model_configs = self._call_llm('model', { 'log_data': log_data, 'metrics': metrics, @@ -503,20 +1893,25 @@ def run_iteration(self, num_runs: int) -> None: 'sdc_context': self.sdc_context, 'inspection_results': inspect_configs }) - print(f"LLM model config: {model_configs['model']}") + model_config = model_configs.get('model', {}) + print(f"LLM model config: {model_config}") # Step 3: Evaluate models with LLM config print("\nStep 3: Evaluating models...") model_results = self.evaluate_models( log_data, metrics, - kernel_type=model_configs['model']['kernel_type'], - preprocessing=model_configs['model']['preprocessing'], - acquisition=model_configs['model']['acquisition'], - surrogate_weight=model_configs['model']['surrogate_weight'] + # kernel_type=model_configs['model']['kernel_type'], + model_config.get('kernel_type', 'matern'), + # preprocessing=model_configs['model']['preprocessing'], + preprocessing=model_config.get('preprocessing', 'robust'), + # acquisition=model_configs['model']['acquisition'], + acquisition=model_config.get('acquisition', 'ei'), + # surrogate_weight=model_configs['model']['surrogate_weight'] + surrogate_weight=model_config.get('surrogate_weight', 0.8) ) - # Get LLM recommendations for parameter selection based on all previous results - print("\nGetting LLM recommendations for parameter selection...") + # Get LLM recommendations for parameter selection based on all previous results with ReAct framework + print("\nGetting LLM recommendations with ReAct framework for parameter selection...") selection_configs = self._call_llm('agglomerate', { 'log_data': log_data, 'metrics': metrics, @@ -526,20 +1921,26 @@ def run_iteration(self, num_runs: int) -> None: 'inspection_results': inspect_configs, 'model_configs': model_configs }) - print(f"LLM selection config: {selection_configs['selection']}") + selection_config = selection_configs.get('agglomerate', {}) + print(f"LLM selection config: {selection_config}") # Step 4: Generate parameters with LLM config print("\nStep 4: Generating parameters...") self.generate_parameters( log_data, metrics, model_results, num_runs, - selection_method=selection_configs['selection']['method'], - quality_weight=selection_configs['selection']['quality_weight'], - uncertainty_bonus=selection_configs['selection']['uncertainty_bonus'] + # selection_method=selection_configs['selection']['method'], + # quality_weight=selection_configs['selection']['quality_weight'], + # uncertainty_bonus=selection_configs['selection']['uncertainty_bonus'] + selection_method=selection_config.get('method', 'hybrid'), + quality_weight=selection_config.get('quality_weight', 0.7), + uncertainty_bonus=selection_config.get('uncertainty_bonus', 0.2) ) - + def inspect_logs(self) -> Dict[str, Any]: - """Step 1: Inspect all logs so far""" - log_dir = f"logs/{self.platform}/{self.design}" + """Step 1: Inspect all .log and .json logs recursively""" + log_dir = "logs" + pattern = f"{self.platform}_{self.design}_run" + log_data = { 'runs': [], 'summary': { @@ -548,25 +1949,62 @@ def inspect_logs(self) -> Dict[str, Any]: 'failed_runs': 0 } } - - # Ensure log directory exists + if not os.path.exists(log_dir): return log_data - - # Process each log file - for log_file in os.listdir(log_dir): - if log_file.endswith('.log'): - run_data = process_log_file(os.path.join(log_dir, log_file)) - log_data['runs'].append(run_data) - - # Update summary - log_data['summary']['total_runs'] += 1 - if run_data['success']: - log_data['summary']['successful_runs'] += 1 - else: - log_data['summary']['failed_runs'] += 1 - + + run_groups = {} + + for root, _, files in os.walk(log_dir): + for log_file in files: + if log_file.endswith(('.log', '.json')): + log_path = os.path.join(root, log_file) + + if log_file.startswith(pattern) or (self.platform in root and self.design in root): + + run_id = "main" + m = re.search(r'_run(\d+)\.log$', log_file) + if m: + run_id = f"base_{m.group(1)}" + + elif 'base_' in root: + run_id = os.path.basename(root) + + run_data = process_log_file(log_path) + + if run_id not in run_groups: + run_groups[run_id] = { + 'run_id': run_id, + 'success': True, + 'metrics': {}, + 'errors': [], + 'files': [] + } + + run_groups[run_id]['success'] &= run_data.get('success', True) + run_groups[run_id]['files'].append(log_path) + + if 'metrics' in run_data and run_data['metrics']: + run_groups[run_id]['metrics'].update(run_data['metrics']) + + if 'errors' in run_data and run_data['errors']: + run_groups[run_id]['errors'].extend(run_data['errors']) + + for run_id, run_data in run_groups.items(): + print(f"DEBUG: Run {run_id} success: {run_data['success']}") + print(f"DEBUG: Run {run_id} metrics: {run_data['metrics']}") + print(f"DEBUG: Run {run_id} errors: {run_data['errors']}") + print(f"DEBUG: Run {run_id} files: {run_data['files']}") + + log_data['runs'].append(run_data) + log_data['summary']['total_runs'] += 1 + if run_data['success']: + log_data['summary']['successful_runs'] += 1 + else: + log_data['summary']['failed_runs'] += 1 + return log_data + def analyze_metrics(self, log_data: Dict[str, Any], n_clusters: int, correlation_threshold: float) -> Dict[str, Any]: """Step 2: Analyze metrics from log data with improved analysis""" @@ -658,6 +2096,7 @@ def analyze_metrics(self, log_data: Dict[str, Any], n_clusters: int, correlation return metrics + def evaluate_models(self, log_data: Dict[str, Any], metrics: Dict[str, Any], kernel_type: str, preprocessing: str, acquisition: str, surrogate_weight: float) -> Dict[str, Any]: """Step 3: Use improved model functions to evaluate parameter quality""" @@ -1053,4 +2492,4 @@ def main(): workflow.run_iteration(num_runs) # Use the run_iteration method instead of individual steps if __name__ == "__main__": - main() \ No newline at end of file + main() diff --git a/flow-Agent/optimize_dual.py b/flow-Agent/optimize_dual.py new file mode 100644 index 0000000..f762ed1 --- /dev/null +++ b/flow-Agent/optimize_dual.py @@ -0,0 +1,2593 @@ +#!/usr/bin/env python3 +import json +import os +import sys +import re +import numpy as np +from typing import Dict, List, Any, Tuple, Optional +import anthropic +import csv +import random +from rag.util import answerWithRAG +from rag.index import load_embeddings_and_docs, build_and_save_embeddings +from sentence_transformers import SentenceTransformer +import torch +from pathlib import Path +from openai import OpenAI +from inspectfuncs import * +from modelfuncs import * +from agglomfuncs import * +import warnings +warnings.filterwarnings("ignore", category=RuntimeWarning) + +print("Python executable:", sys.executable) +print("sys.path:", sys.path[:3]) +print("Current working dir:", os.getcwd()) + +for pkg in ["anthropic", "sentence_transformers", "torch", "openai"]: + try: + __import__(pkg) + print(f" Imported {pkg}") + except ImportError as e: + print(f" Failed to import {pkg}: {e}") + +def process_log_file(log_path: str) -> Dict[str, Any]: + """Process a single log file to extract relevant metrics""" + run_data = { + 'file': os.path.basename(log_path), + 'success': False, + 'metrics': {}, + 'errors': [] + } + + with open(log_path, 'r') as f: + content = f.read() + print(f"File size: {len(content)} characters") + + # Extract timing information + timing_metrics = extract_timing_metrics(content) + run_data['metrics'].update(timing_metrics) + + # Extract wirelength information + wl_metrics = extract_wirelength_metrics(content) + run_data['metrics'].update(wl_metrics) + + # Extract any errors + errors = extract_errors(content) + run_data['errors'].extend(errors) + # === Inject a simulated error for testing RAG debugging === + # if "run3" in log_path: # 👈 你可以换成任意 run，比如 run1 或 run2 + # fake_error = "[ERROR] TEST_SIM: Simulated routing congestion failure" + # print(f"[DEBUG] Injected simulated error in {log_path}: {fake_error}") + # run_data['errors'].append(fake_error) + # run_data['success'] = False + + run_data['success'] = is_run_successful(content, errors) + + return run_data + +def extract_timing_metrics(log_content: str) -> Dict[str, float]: + """Extract timing-related metrics from log content""" + metrics = {} + + # Extract worst slack (final) + slack_match = re.search(r'(?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + if slack_match: + metrics['worst_slack'] = float(slack_match.group(1)) + + # Extract CTS worst slack + # cts_slack_match = re.search(r'(?:CTS|Clock Tree) (?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + cts_slack_match = re.search(r'Timing-driven:\s*(?:worst slack|WNS)\s+([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_slack_match: + metrics['cts_ws'] = float(cts_slack_match.group(1)) + + # Extract clock period + # period_match = re.search(r'[Cc]lock period:\s*([\d.]+)', log_content) + period_match = re.search(r'clock period to\s*([\d.]+)', log_content) + if period_match: + metrics['clock_period'] = float(period_match.group(1)) + + # Extract TNS + # tns_match = re.search(r'(?:Total negative slack|TNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + tns_match = re.search(r'"finish__timing__setup__tns"\s*:\s*([-\d.eE]+)', log_content) + if tns_match: + metrics['tns'] = float(tns_match.group(1)) + + return metrics + +def extract_wirelength_metrics(log_content: str) -> Dict[str, float]: + """Extract wirelength-related metrics from log content""" + metrics = {} + + # Extract total wirelength + wl_match = re.search(r'Total wirelength: ([\d.]+)', log_content) + if wl_match: + metrics['total_wirelength'] = float(wl_match.group(1)) + + # Extract estimated wirelength after CTS + # cts_wl_match = re.search(r'Estimated wirelength: ([\d.]+)', log_content) + cts_wl_match = re.search(r'"?cts__route__wirelength__estimated"?\s*[:=]\s*([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_wl_match: + metrics['cts_wirelength'] = float(cts_wl_match.group(1)) + + return metrics + +def extract_errors(log_content: str) -> List[str]: + """Extract error messages from log content""" + errors = [] + + # Look for common error patterns + error_patterns = [ + r'Error: .*', + r'ERROR: .*', + r'FATAL: .*', + r'Failed: .*' + ] + + for pattern in error_patterns: + matches = re.finditer(pattern, log_content, re.MULTILINE) + errors.extend(match.group(0) for match in matches) + + return errors + +def is_run_successful(log_content: str, errors: List[str], filename: str = "") -> bool: + """Determine if a run was successful based on log content and errors""" + if errors: + # If any real error lines were found, this file is a failure indicator + return False + + # Look for completion markers + completion_markers = [ + 'Flow complete', + 'Finished successfully', + 'Writing out GDS/OAS', + '6_report' + ] + + return any(marker in log_content for marker in completion_markers) + + +class ReActFramework: + """ReAct framework implementation""" + + def __init__(self, client, model_name="DeepSeek-V3"): + self.client = client + self.model_name = model_name + self.conversation_history = [] + + def add_to_history(self, role: str, content: str): + """add conversation history""" + self.conversation_history.append({"role": role, "content": content}) + + def clear_history(self): + """clear conversation history""" + self.conversation_history = [] + + def extract_thought_action(self, response: str) -> Tuple[str, str, str]: + """ + Extract Thought, Action, and Action Input from LLM responses + Format: Thought:... Action:... Action Input: ... + """ + thought = "" + action = "" + action_input = "" + + # Extract Thought + thought_match = re.search(r'Thought:\s*(.*?)(?=\nAction:|$)', response, re.DOTALL) + if thought_match: + thought = thought_match.group(1).strip() + + # Extract Action + action_match = re.search(r'Action:\s*(\w+)', response) + if action_match: + action = action_match.group(1).strip() + + # Extract Action Input + action_input_match = re.search(r'Action Input:\s*(.*?)(?=\nObservation:|$)', response, re.DOTALL) + if action_input_match: + action_input = action_input_match.group(1).strip() + # Try to parse JSON + try: + if action_input.startswith('{') or action_input.startswith('['): + action_input = json.loads(action_input) + except: + pass # Maintain the string format + + if "Final Answer:" in response and ("Action:" in response or "Observation:" in response): + + response = response.split("Final Answer:")[0] + print("Removed premature Final Answer from response") + + return thought, action, action_input + + def execute_action(self, action: str, action_input: Any, available_tools: Dict) -> str: + """Execute tool call and return observation results""" + if action in available_tools: + try: + result = available_tools[action](action_input) + return f"Action executed successfully. Result: {result}" + except Exception as e: + return f"Action execution failed: {str(e)}" + else: + return f"Unknown action: {action}. Available actions: {list(available_tools.keys())}" + + def run_react_cycle(self, + initial_prompt: str, + available_tools: Dict, + max_steps: int = 5, + temperature: float = 0.1) -> Dict[str, Any]: + """ + Run ReAct loop + + Args: + initial_prompt: Initial prompt + available_tools: Available tool function dictionary + max_steps: Maximum reasoning steps + temperature: temperature parameter + + Returns: + a dictionary containing the final result and the reasoning history + """ + self.clear_history() + self.add_to_history("user", initial_prompt) + + history = [] + final_answer = None + completed_steps = 0 + + for step in range(max_steps): + print(f"\n=== ReAct Step {step + 1}/{max_steps} ===") + completed_steps = step + 1 + + # Call LLM to obtain response + try: + response = self.client.chat.completions.create( + model=self.model_name, + messages=self.conversation_history, + temperature=temperature, + max_tokens=1024 + ) + + llm_response = response.choices[0].message.content + print(f"LLM Response: {llm_response}") + except Exception as e: + print(f"Error calling LLM: {e}") + llm_response = f"Error in LLM call: {e}" + + # Extract Thought, Action, Action Input + thought, action, action_input = self.extract_thought_action(llm_response) + + step_data = { + "step": step + 1, + "thought": thought, + "action": action, + "action_input": action_input, + "llm_response": llm_response + } + + # Check if it is the final answer + final_answer_detected = False + if "Final Answer:" in llm_response: + final_answer_match = re.search(r'Final Answer:\s*(.*?)$', llm_response, re.DOTALL) + if final_answer_match: + final_answer = final_answer_match.group(1).strip() + step_data["final_answer"] = final_answer + final_answer_detected = True + print(f"✓ Final answer detected at step {step + 1}") + + observation = "" + # Execute actions and obtain observation results + if action and not final_answer_detected: + observation = self.execute_action(action, action_input, available_tools) + step_data["observation"] = observation + + # Update conversation history + self.add_to_history("assistant", llm_response) + self.add_to_history("user", f"Observation: {observation}") + + print(f"Thought: {thought}") + print(f"Action: {action}") + print(f"Action Input: {action_input}") + print(f"Observation: {observation}") + else: + if not final_answer_detected: + # If there is no clear action, it may be during the reasoning process + self.add_to_history("assistant", llm_response) + step_data["observation"] = "No action taken - continuing reasoning" + observation = "No action taken" + else: + # If it is the final answer, no further action is required + step_data["observation"] = "Final answer provided - cycle complete" + observation = "Final answer provided" + + history.append(step_data) + + if final_answer_detected: + print(f" ReAct cycle completed at step {step + 1} with final answer") + break + + # Check if it should end early + if step >= max_steps - 1: + final_answer = f"Reached maximum steps ({max_steps}) without final answer" + print(f" Reached maximum steps without final answer") + break + + if final_answer is None: + final_answer = "No final answer produced" + + return { + "final_answer": final_answer, + "reasoning_history": history, + "success": final_answer is not None and "Reached maximum steps" not in final_answer and "No final answer" not in final_answer, + "completed_steps": completed_steps, + "max_steps": max_steps + } + + +class OptimizationWorkflow: + def __init__(self, platform: str, design: str, objective: str): + self.platform = platform + self.design = design + self.objective = objective.upper() # Convert to uppercase + + # Load configuration + self.config = self._load_config() + + # Find the design configuration + configurations = self.config.get('configurations', []) + for config in configurations: + if ( + config['platform'].lower() == self.platform.lower() + and config['design'].lower() == self.design.lower() + and config['goal'].upper() == self.objective + ): + self.design_config = config + break + else: + raise ValueError( + f"No configuration found for platform={self.platform}, design={self.design}, objective={self.objective}" + ) + + # Define initial clock periods for each design and platform + initial_clock_periods = { + ('asap7', 'aes'): 400, # in picoseconds + ('asap7', 'ibex'): 1260, # in picoseconds + ('asap7', 'jpeg'): 1100, # in picoseconds + ('sky130hd', 'aes'): 4.5, # in nanoseconds + ('sky130hd', 'ibex'): 10.0,# in nanoseconds + ('sky130hd', 'jpeg'): 8.0, # in nanoseconds + } + + # Get the initial clock period for the current platform and design + key = (self.platform.lower(), self.design.lower()) + if key in initial_clock_periods: + self.initial_clk_period = initial_clock_periods[key] + else: + raise ValueError(f"Initial clock period not defined for platform={self.platform}, design={self.design}") + + # Calculate clock period range + min_clk = self.initial_clk_period * 0.7 + max_clk = self.initial_clk_period * 1.3 + + # Define parameter names in the expected order + self.parameter_names = [ + 'core_util', + 'cell_pad_global', + 'cell_pad_detail', + 'synth_flatten', + 'pin_layer', + 'above_layer', + 'tns', + 'lb_addon', + 'cts_size', + 'cts_diameter', + 'enable_dpo', + 'clk_period' + ] + + # Set all parameter constraints including clock period range + self.param_constraints = { + 'core_util': {'type': 'int', 'range': [20, 99]}, + 'cell_pad_global': {'type': 'int', 'range': [0, 4]}, + 'cell_pad_detail': {'type': 'int', 'range': [0, 4]}, + 'synth_flatten': {'type': 'int', 'range': [0, 1]}, + 'pin_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'above_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'tns': {'type': 'int', 'range': [70, 100]}, + 'lb_addon': {'type': 'float', 'range': [0.00, 0.99]}, + 'cts_size': {'type': 'int', 'range': [10, 40]}, + 'cts_diameter': {'type': 'int', 'range': [80, 120]}, + 'enable_dpo': {'type': 'int', 'range': [0, 1]}, + 'clk_period': {'type': 'float', 'range': [min_clk, max_clk]} + } + + # Load initial parameters and SDC context + self.initial_params = self._load_initial_params() + self.sdc_context = self._load_sdc_context() + + emb_np, docs, docsDict = load_embeddings_and_docs() + self.rag_embeddings = torch.tensor(emb_np).cpu() + self.rag_docs = docs + self.rag_docsDict = docsDict + print("[INFO] Loading embedding model...") + model_path = Path(__file__).parent / "models" / "mxbai-embed-large-v1" + model_path = model_path.resolve() + # self.rag_model = SentenceTransformer(str(model_path)) + self.rag_model = SentenceTransformer(str(model_path), device='cpu') + + self.react_framework = ReActFramework( + client=OpenAI( + base_url="https://ai.gitee.com/v1", + # api_key=" ", + api_key=" ", + ), + model_name="DeepSeek-V3" + ) + # Secondary supervisor model for dual-LLM flow. All values can be overridden via env variables. + self.supervisor_client = OpenAI( + base_url=os.environ.get("SUPERVISOR_BASE_URL", "https://ai.gitee.com/v1"), + api_key=os.environ.get("SUPERVISOR_API_KEY", " "), + ) + self.supervisor_model_name = os.environ.get("SUPERVISOR_MODEL", "DeepSeek-V3") + self.supervision_feedback: str = "" + + def _create_react_tools(self, stage: str, data: Dict[str, Any]) -> Dict: + """Create available utility functions for different stages""" + + base_tools = { + "analyze_data_distribution": lambda x: self._call_existing_distribution_analysis(data), + "analyze_data_structure": lambda x: self._call_existing_structure_analysis(data), + "evaluate_parameter_ranges": lambda x: self._evaluate_parameter_ranges(data), + "check_constraints": lambda x: self._check_constraints_compliance(data), + "suggest_improvements": lambda x: self._suggest_improvements(stage, data), + } + + if stage == 'inspect': + inspection_tools = { + "configure_inspection": lambda config: self._configure_inspection_with_existing(config, data), + "analyze_correlations": lambda params: self._analyze_correlations_with_existing(params, data), + "cluster_analysis": lambda config: self._cluster_analysis_with_existing(config, data), + "manifold_analysis": lambda config: self._manifold_analysis_with_existing(config, data), + "local_structure_analysis": lambda config: self._local_structure_analysis_with_existing(config, data), + } + base_tools.update(inspection_tools) + + elif stage == 'model': + modeling_tools = { + "configure_model": lambda config: self._configure_model_with_existing(config, data), + "evaluate_surrogate": lambda params: self._evaluate_surrogate_with_existing(params, data), + "select_acquisition": lambda method: self._select_acquisition_with_existing(method, data), + "create_surrogate_model": lambda config: self._create_surrogate_model_with_existing(config, data), + "evaluate_timing_model": lambda x: self._evaluate_timing_model_with_existing(data), + "evaluate_wirelength_model": lambda x: self._evaluate_wirelength_model_with_existing(data), + "get_model_recommendations": lambda x: self._get_model_recommendations_from_existing(data), + } + base_tools.update(modeling_tools) + + elif stage == 'agglomerate': + selection_tools = { + "configure_selection": lambda config: self._configure_selection_with_existing(config, data), + "generate_parameters": lambda count: self._generate_parameters_with_existing(count, data), + "validate_parameters": lambda params: self._validate_parameters_tool(params), + "latin_hypercube_sampling": lambda config: self._latin_hypercube_sampling_with_existing(config, data), + "create_quality_scores": lambda config: self._create_quality_scores_with_existing(config, data), + "select_points": lambda config: self._select_points_with_existing(config, data), + "compare_selection_methods": lambda config: self._compare_selection_methods_with_existing(config, data), + "kmeans_selection": lambda config: self._kmeans_selection_with_existing(config, data), + "hybrid_selection": lambda config: self._hybrid_selection_with_existing(config, data), + "entropy_selection": lambda config: self._entropy_selection_with_existing(config, data), + "graph_selection": lambda config: self._graph_selection_with_existing(config, data), + } + base_tools.update(selection_tools) + + return base_tools + + + def _call_existing_distribution_analysis(self, data: Dict) -> str: + """Call existing data distribution analysis functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + result = inspect_data_distribution(X, Y) + return self._format_analysis_result("Data Distribution Analysis", result) + else: + return "Insufficient data for distribution analysis" + + except Exception as e: + return f"Error in distribution analysis: {str(e)}" + + def _call_existing_structure_analysis(self, data: Dict) -> str: + """Call existing data structure analysis functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Use default configuration or retrieve configuration from data + config = { + "n_clusters": 5, + "correlation_threshold": 0.5, + "n_neighbors": 20, + "perplexity": 30 + } + + result = inspect_data_structure(X, Y, config) + return self._format_analysis_result("Data Structure Analysis", result) + else: + return "Insufficient data for structure analysis" + + except Exception as e: + return f"Error in structure analysis: {str(e)}" + + def _evaluate_parameter_ranges(self, data: Dict) -> str: + """Evaluation Parameter Range Tool - Implementation""" + constraints_info = "Parameter Constraints Evaluation:\n" + + # Analyze the current usage of parameters + param_usage = {} + for run in data.get('log_data', {}).get('runs', []): + if run.get('parameters'): + for param, value in run['parameters'].items(): + if param not in param_usage: + param_usage[param] = [] + param_usage[param].append(float(value)) + + for param, info in self.param_constraints.items(): + min_val, max_val = info['range'] + param_type = info['type'] + + constraints_info += f"\n- {param} ({param_type}): range [{min_val}, {max_val}]" + + if param in param_usage: + values = param_usage[param] + used_min = min(values) + used_max = max(values) + constraints_info += f"\n Currently used: [{used_min:.2f}, {used_max:.2f}]" + + # Check if the parameter space has been fully explored + range_used = (used_max - used_min) / (max_val - min_val) + if range_used < 0.5: + constraints_info += f" (Only {range_used*100:.1f}% of range explored)" + + return constraints_info + + def _check_constraints_compliance(self, data: Dict) -> str: + """Check Constraint Compliance Tool - Implementation""" + violations = [] + constraint_checks = [] + + for run in data.get('log_data', {}).get('runs', []): + if run.get('success') and run.get('parameters'): + params = run['parameters'] + + # Check the basic scope constraints + for param, value in params.items(): + if param in self.param_constraints: + constraint = self.param_constraints[param] + min_val, max_val = constraint['range'] + if value < min_val or value > max_val: + violations.append(f"{param}={value} not in [{min_val}, {max_val}]") + + # Check domain constraints + if not self._validate_domain_constraints(params): + violations.append(f"Domain constraints violated for run with params: {params}") + + if violations: + constraint_checks.append(f"Constraint violations found in {len(violations)} cases:") + constraint_checks.extend(violations[:5]) # Only display the first 5 + else: + constraint_checks.append("All parameters comply with constraints") + + # Check the effectiveness of parameter combinations + successful_count = sum(1 for run in data.get('log_data', {}).get('runs', []) + if run.get('success') and run.get('parameters')) + total_with_params = sum(1 for run in data.get('log_data', {}).get('runs', []) + if run.get('parameters')) + + if total_with_params > 0: + success_rate = successful_count / total_with_params * 100 + constraint_checks.append(f"\nParameter success rate: {success_rate:.1f}%") + + return "\n".join(constraint_checks) + + def _suggest_improvements(self, stage: str, data: Dict) -> str: + """Provide improvement suggestions based on stages - implementation""" + suggestions = [] + + if stage == 'inspect': + successful_runs = data.get('log_data', {}).get('summary', {}).get('successful_runs', 0) + total_runs = data.get('log_data', {}).get('summary', {}).get('total_runs', 0) + + suggestions.append(f"Inspection Suggestions for {successful_runs}/{total_runs} successful runs:") + + if successful_runs < total_runs * 0.3: + suggestions.append("- Focus on identifying why runs are failing") + suggestions.append("- Check for common parameter ranges in failed runs") + else: + suggestions.append("- Analyze correlations between parameters and objectives") + suggestions.append("- Identify optimal parameter ranges from successful runs") + + elif stage == 'model': + suggestions.append("Modeling Suggestions:") + suggestions.append("- Use surrogate models for early prediction of results") + suggestions.append("- Balance exploration (trying new regions) and exploitation (refining good regions)") + + # Suggest modeling methods based on data volume + successful_runs = data.get('log_data', {}).get('summary', {}).get('successful_runs', 0) + if successful_runs < 10: + suggestions.append("- With limited data, use simpler models and focus on exploration") + else: + suggestions.append("- With sufficient data, use more complex models and balance exploration/exploitation") + + elif stage == 'agglomerate': + suggestions.append("Parameter Generation Suggestions:") + suggestions.append("- Generate diverse parameter sets to explore different regions") + suggestions.append("- Focus on promising parameter ranges identified in previous stages") + suggestions.append("- Ensure all generated parameters satisfy domain constraints") + + # Suggest strategies based on goals + if self.objective == 'ECP': + suggestions.append("- For ECP, prioritize timing-critical parameters like clk_period and cell padding") + elif self.objective == 'DWL': + suggestions.append("- For DWL, focus on placement and routing parameters") + + return "\n".join(suggestions) + + def _extract_XY_from_data(self, data: Dict) -> Tuple[Optional[np.ndarray], Optional[np.ndarray]]: + """Extracting X and Y arrays from data - Reusing logic in analyze_stetrics""" + feature_vectors = [] + objective_values = [] + + for run in data.get('log_data', {}).get('runs', []): + if run.get('success') and 'metrics' in run: + obj_values = self._calculate_objective(run) + + if obj_values['value'] is not None or obj_values['surrogate'] is not None: + # Extract parameter values as features + params = [] + for param in self.parameter_names: + params.append(float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0)))) + feature_vectors.append(params) + + # Use real values, if not available, use proxy values + objective_values.append(obj_values['value'] if obj_values['value'] is not None else obj_values['surrogate']) + + if feature_vectors and objective_values: + return np.array(feature_vectors), np.array(objective_values) + else: + return None, None + + def _format_analysis_result(self, title: str, result: Dict) -> str: + """Format the analysis result as a readable string""" + formatted = f"=== {title} ===\n" + + for key, value in result.items(): + if key == "model_recommendations": + formatted += "\n--- Model Recommendations ---\n" + for rec_key, rec_value in value.items(): + formatted += f"{rec_key}: {rec_value}\n" + elif isinstance(value, (int, float)): + formatted += f"{key}: {value:.4f}\n" + elif isinstance(value, list) and len(value) > 0 and isinstance(value[0], (int, float)): + # Format numerical list + formatted += f"{key}: [{', '.join(f'{v:.4f}' for v in value[:5])}{'...' if len(value) > 5 else ''}]\n" + else: + formatted += f"{key}: {value}\n" + + return formatted + + def _configure_inspection_with_existing(self, config: Dict, data: Dict) -> str: + """Use existing function configuration to check parameters""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Using configuration to run structural analysis + result = inspect_data_structure(X, Y, config) + + response = f"Inspection configured with: {config}\n" + response += "Key findings:\n" + + # Extract key findings + if "linearity_score" in result: + response += f"- Linearity: {result['linearity_score']:.3f}\n" + if "is_nonlinear" in result: + response += f"- Nonlinear: {result['is_nonlinear']}\n" + if "needs_local_models" in result: + response += f"- Needs local models: {result['needs_local_models']}\n" + if "cluster_sizes" in result: + response += f"- Cluster sizes: {result['cluster_sizes']}\n" + + return response + else: + return "No data available for inspection configuration" + + except Exception as e: + return f"Error in inspection configuration: {str(e)}" + + def _analyze_correlations_with_existing(self, params: Dict, data: Dict) -> str: + """Analyze correlation using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Perform structural analysis to obtain relevant information + config = {"correlation_threshold": params.get('threshold', 0.5)} + result = inspect_data_structure(X, Y, config) + + response = "Feature Correlations Analysis:\n" + + if "feature_importance" in result: + response += "Feature importance (correlation with objective):\n" + for i, importance in enumerate(result["feature_importance"]): + response += f"- {self.parameter_names[i]}: {importance:.3f}\n" + + if "has_correlated_features" in result: + response += f"Has highly correlated features: {result['has_correlated_features']}\n" + if "high_correlation_pairs" in result: + response += f"High correlation pairs: {result['high_correlation_pairs']}\n" + + return response + else: + return "No data available for correlation analysis" + + except Exception as e: + return f"Error in correlation analysis: {str(e)}" + + def _cluster_analysis_with_existing(self, config: Dict, data: Dict) -> str: + """Cluster analysis using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Perform structural analysis to obtain clustering information + result = inspect_data_structure(X, Y, config) + + response = "Cluster Analysis:\n" + + if "cluster_sizes" in result: + response += f"Cluster sizes: {result['cluster_sizes']}\n" + if "cluster_balance" in result: + response += f"Cluster balance: {result['cluster_balance']:.3f}\n" + if "cluster_y_means" in result: + response += "Cluster objective means:\n" + for i, mean in enumerate(result["cluster_y_means"]): + response += f"- Cluster {i}: {mean:.4f}\n" + if "needs_local_models" in result: + response += f"Recommend local models: {result['needs_local_models']}\n" + + return response + else: + return "No data available for cluster analysis" + + except Exception as e: + return f"Error in cluster analysis: {str(e)}" + + def _manifold_analysis_with_existing(self, config: Dict, data: Dict) -> str: + """Perform manifold analysis using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None: + result = analyze_manifold_structure(X, config) + return self._format_analysis_result("Manifold Structure Analysis", result) + else: + return "No data available for manifold analysis" + + except Exception as e: + return f"Error in manifold analysis: {str(e)}" + + def _local_structure_analysis_with_existing(self, config: Dict, data: Dict) -> str: + """Using existing functions for local structure analysis""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None: + result = analyze_local_structure(X, config) + return self._format_analysis_result("Local Structure Analysis", result) + else: + return "No data available for local structure analysis" + + except Exception as e: + return f"Error in local structure analysis: {str(e)}" + + def _get_model_recommendations_from_existing(self, data: Dict) -> str: + """Obtain model recommendations from existing analysis""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + result = inspect_data_structure(X, Y) + + if "model_recommendations" in result: + recommendations = result["model_recommendations"] + response = "Model Recommendations from Data Analysis:\n" + + for key, value in recommendations.items(): + if key == "feature_weights" and isinstance(value, list): + response += f"{key}: [" + response += ", ".join(f"{w:.3f}" for w in value[:5]) + if len(value) > 5: + response += ", ..." + response += "]\n" + else: + response += f"{key}: {value}\n" + + return response + else: + return "No model recommendations available" + else: + return "No data available for model recommendations" + + except Exception as e: + return f"Error getting model recommendations: {str(e)}" + + + def _configure_model_with_existing(self, config: Dict, data: Dict) -> str: + """Configure the model using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Create a model using configuration + kernel_type = config.get('kernel_type', 'matern') + preprocessing = config.get('preprocessing', 'standard') + acquisition = config.get('acquisition', 'ei') + + # Create Preprocessor + preprocessor = create_preprocessor(preprocessing) + + # Create acquisition function + acq_function = create_acquisition_function(acquisition) + + response = f"Model configured successfully:\n" + response += f"- Kernel type: {kernel_type}\n" + response += f"- Preprocessing: {preprocessing}\n" + response += f"- Acquisition function: {acquisition}\n" + response += f"- Data shape: {X.shape}\n" + + # If the amount of data is sufficient, a model can be created for testing + if len(X) >= 2: + model = create_model(X, Y, kernel_type=kernel_type) + response += f"- Model created successfully with {len(X)} samples\n" + else: + response += f"- Insufficient data for model creation (need at least 2 samples, have {len(X)})\n" + + return response + else: + return "No data available for model configuration" + + except Exception as e: + return f"Error in model configuration: {str(e)}" + + def _evaluate_surrogate_with_existing(self, params: Dict, data: Dict) -> str: + """Evaluate the proxy model using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Extract proxy values (if any) + surrogate_values = None + if 'surrogates' in data.get('metrics', {}): + surrogate_values = np.array(data['metrics']['surrogates']) + + # Use existing functions to process proxy data + if surrogate_values is not None: + X_processed, y_combined, uncertainty = handle_surrogate_data(X, Y, surrogate_values) + + response = "Surrogate Model Evaluation:\n" + response += f"- Original data points: {len(Y)}\n" + response += f"- Valid target values: {np.sum(~np.isnan(Y))}\n" + response += f"- Surrogate values used: {np.sum(np.isnan(Y))}\n" + response += f"- Combined data points: {len(y_combined)}\n" + + if len(uncertainty) > 0: + response += f"- Average surrogate uncertainty: {np.mean(uncertainty):.4f}\n" + + return response + else: + return "No surrogate data available for evaluation" + else: + return "No data available for surrogate evaluation" + + except Exception as e: + return f"Error in surrogate evaluation: {str(e)}" + + def _select_acquisition_with_existing(self, method: str, data: Dict) -> str: + """Use existing functions to select collection functions""" + try: + # Create a collection function using an existing function + acq_function = create_acquisition_function(method) + + response = f"Acquisition function selected: {method.upper()}\n" + + # Provide explanations for different collection functions + explanations = { + 'ei': "Expected Improvement - balances improvement probability and magnitude", + 'ucb': "Upper Confidence Bound - favors exploration of uncertain regions", + 'pi': "Probability of Improvement - focuses on areas likely to improve", + 'augmented_ei': "Augmented EI - combines EI with exploration bonus" + } + + response += f"Explanation: {explanations.get(method, 'No explanation available')}\n" + + # Provide recommendations based on data characteristics + X, Y = self._extract_XY_from_data(data) + if X is not None and Y is not None: + if len(Y) < 10: + response += "Recommendation: With limited data, consider using UCB for better exploration\n" + else: + response += "Recommendation: With sufficient data, EI or Augmented EI are good choices\n" + + return response + + except Exception as e: + return f"Error in acquisition function selection: {str(e)}" + + def _create_surrogate_model_with_existing(self, config: Dict, data: Dict) -> str: + """Create a proxy model using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + kernel_type = config.get('kernel_type', 'matern') + noise_level = config.get('noise_level', 1e-6) + + # Create a model using existing functions + model = create_model(X, Y, noise_level=noise_level, kernel_type=kernel_type) + + response = f"Surrogate Model Created:\n" + response += f"- Kernel: {kernel_type}\n" + response += f"- Data points: {len(X)}\n" + response += f"- Features: {X.shape[1]}\n" + response += f"- Kernel parameters: {model.kernel_}\n" + + # Test model prediction + if len(X) > 0: + predictions, stds = predict_with_model(model, X[:1]) # Test a point + response += f"- Test prediction successful\n" + response += f"- Prediction range: [{predictions[0]:.4f} ± {stds[0]:.4f}]\n" + + return response + else: + return "No data available for model creation" + + except Exception as e: + return f"Error in surrogate model creation: {str(e)}" + + def _evaluate_timing_model_with_existing(self, data: Dict) -> str: + """Evaluate timing models using existing functions""" + try: + # Build context + context = { + 'log_data': data.get('log_data', {}), + 'metrics': data.get('metrics', {}), + 'model_recommendations': data.get('model_recommendations', {}) + } + + # Evaluate timing models using existing functions + results = evaluate_timing_model(context) + + response = "Timing Model Evaluation:\n" + + if 'performance' in results: + for key, value in results['performance'].items(): + response += f"- {key}: {value:.4f}\n" + + if 'suggestions' in results: + response += "\nSuggestions:\n" + for suggestion in results['suggestions']: + response += f"- {suggestion}\n" + + if 'recommendations' in results: + response += "\nRecommendations:\n" + for key, value in results['recommendations'].items(): + response += f"- {key}: {value}\n" + + return response + + except Exception as e: + return f"Error in timing model evaluation: {str(e)}" + + def _evaluate_wirelength_model_with_existing(self, data: Dict) -> str: + """Evaluate the wire length model using existing functions""" + try: + # Build context + context = { + 'log_data': data.get('log_data', {}), + 'metrics': data.get('metrics', {}), + 'model_recommendations': data.get('model_recommendations', {}) + } + + # Evaluate the wire length model using existing functions + results = evaluate_wirelength_model(context) + + response = "Wirelength Model Evaluation:\n" + + if 'performance' in results: + for key, value in results['performance'].items(): + response += f"- {key}: {value:.4f}\n" + + if 'suggestions' in results: + response += "\nSuggestions:\n" + for suggestion in results['suggestions']: + response += f"- {suggestion}\n" + + if 'recommendations' in results: + response += "\nRecommendations:\n" + for key, value in results['recommendations'].items(): + response += f"- {key}: {value}\n" + + return response + + except Exception as e: + return f"Error in wirelength model evaluation: {str(e)}" + + def _generate_parameters_with_existing(self, count: int, data: Dict) -> str: + """Generate parameters using existing functions""" + try: + if count <= 0 or count > 50: + return "Error: count must be between 1 and 50" + + # Obtain parameter dimensions + n_dims = len(self.parameter_names) + + # Use existing Latin hypercube sampling + samples = latin_hypercube(count, n_dims) + + response = f"Parameter Generation using Latin Hypercube:\n" + response += f"- Samples generated: {count}\n" + response += f"- Parameter dimensions: {n_dims}\n" + response += f"- Sampling method: Latin Hypercube\n" + + # Display parameter range information + response += "\nParameter Ranges:\n" + for i, param in enumerate(self.parameter_names): + constraint = self.param_constraints[param] + min_val, max_val = constraint['range'] + response += f"- {param}: [{min_val}, {max_val}] ({constraint['type']})\n" + + return response + + except Exception as e: + return f"Error in parameter generation: {str(e)}" + + def _latin_hypercube_sampling_with_existing(self, config: Dict, data: Dict) -> str: + """Using existing functions for Latin hypercube sampling""" + try: + n_points = config.get('n_points', 10) + n_dims = len(self.parameter_names) + + # Use the existing Latin hypercube sampling function + samples = latin_hypercube(n_points, n_dims) + + response = f"Latin Hypercube Sampling:\n" + response += f"- Points: {n_points}\n" + response += f"- Dimensions: {n_dims}\n" + response += f"- Sample shape: {samples.shape}\n" + + # Display sampling statistics + response += f"- Sample range: [{samples.min():.3f}, {samples.max():.3f}]\n" + response += f"- Sample mean: {samples.mean():.3f}\n" + response += f"- Sample std: {samples.std():.3f}\n" + + return response + + except Exception as e: + return f"Error in Latin hypercube sampling: {str(e)}" + + def _configure_selection_with_existing(self, config: Dict, data: Dict) -> str: + """Configure selection strategy using existing functions""" + try: + method = config.get('method', 'hybrid') + quality_weight = config.get('quality_weight', 0.7) + uncertainty_bonus = config.get('uncertainty_bonus', 0.2) + n_points = config.get('n_points', 10) + + response = f"Selection Strategy Configured:\n" + response += f"- Method: {method}\n" + response += f"- Quality weight: {quality_weight}\n" + response += f"- Uncertainty bonus: {uncertainty_bonus}\n" + response += f"- Points to select: {n_points}\n" + + # Provide explanations for different methods + method_descriptions = { + "kmeans": "K-means clustering - selects best point from each cluster", + "hybrid": "Hybrid approach - balances quality and diversity", + "entropy": "Entropy-based - maximizes information diversity", + "graph": "Graph-based - uses network centrality measures" + } + + response += f"Method description: {method_descriptions.get(method, 'No description')}\n" + + return response + + except Exception as e: + return f"Error in selection configuration: {str(e)}" + + + def _create_quality_scores_with_existing(self, config: Dict, data: Dict) -> str: + """Create a quality score using an existing function""" + try: + # Extract necessary information from data + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Simulation model predictions and uncertainties (in practical use, these should come from real models) + model_predictions = Y # Using real values as a proxy for prediction + model_uncertainties = np.ones_like(Y) * 0.1 # Simulate uncertainty + + # Create a quality score using an existing function + quality_scores = create_quality_scores(X, Y, model_predictions, model_uncertainties) + + response = "Quality Scores Created:\n" + response += f"- Data points: {len(X)}\n" + response += f"- Quality score range: [{quality_scores.min():.4f}, {quality_scores.max():.4f}]\n" + response += f"- Quality score mean: {quality_scores.mean():.4f}\n" + response += f"- Quality score std: {quality_scores.std():.4f}\n" + + response += f"- First 5 quality scores: {quality_scores[:5].tolist()}\n" + + if 'selection_data' not in data: + data['selection_data'] = {} + data['selection_data']['quality_scores'] = quality_scores + data['selection_data']['X'] = X + data['selection_data']['Y'] = Y + + return response + else: + return "No data available for quality score creation" + + except Exception as e: + return f"Error in quality score creation: {str(e)}" + + def _select_points_with_existing(self, config: Dict, data: Dict) -> str: + """_select_points_with_existing""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + method = config.get('method', 'hybrid') + n_points = config.get('n_points', 10) + quality_weight = config.get('quality_weight', 0.7) + + selection_config = { + "quality_weight": quality_weight, + "uncertainty_bonus": config.get('uncertainty_bonus', 0.2) + } + + selected_indices = select_points( + X, quality_scores, + method=method, + n_points=n_points, + config=selection_config + ) + + response = f"Points Selected using {method.upper()} method:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Selected quality scores: {selected_qualities.tolist()}\n" + response += f"- Average quality of selected: {selected_qualities.mean():.4f}\n" + + # store selection data + data['selection_data']['selected_indices'] = selected_indices + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in point selection: {str(e)}" + + def _compare_selection_methods_with_existing(self, config: Dict, data: Dict) -> str: + """compare selection methods with existing(""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 5) + methods = ['kmeans', 'hybrid', 'entropy', 'graph'] + + response = "Selection Method Comparison:\n" + response += f"- Comparing {len(methods)} methods\n" + response += f"- Points to select: {n_points}\n\n" + + for method in methods: + try: + selected_indices = select_points( + X, quality_scores, + method=method, + n_points=n_points + ) + + selected_qualities = quality_scores[selected_indices] + + response += f"**{method.upper()}**:\n" + response += f" - Selected indices: {selected_indices.tolist()}\n" + response += f" - Avg quality: {selected_qualities.mean():.4f}\n" + response += f" - Quality range: [{selected_qualities.min():.4f}, {selected_qualities.max():.4f}]\n" + + except Exception as e: + response += f"**{method.upper()}**: Error - {str(e)}\n" + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in method comparison: {str(e)}" + + def _kmeans_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using K-means selection method""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + + # using K-means selecting function + selected_indices = kmeans_select(X, quality_scores, n_points) + + response = "K-means Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + response += f"- Quality diversity: {selected_qualities.std():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'kmeans' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in K-means selection: {str(e)}" + + def _hybrid_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using existing hybrid selection method""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + quality_weight = config.get('quality_weight', 0.7) + + distance_matrix = cdist(X, X) + + # using hybrid_select function + selected_indices = hybrid_select( + X, quality_scores, distance_matrix, + n_points, quality_weight + ) + + response = "Hybrid Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Quality weight: {quality_weight}\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + + selected_points = X[selected_indices] + min_distances = np.min(cdist(selected_points, selected_points) + np.eye(len(selected_points)) * 1e6, axis=1) + response += f"- Minimum inter-point distance: {min_distances.mean():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'hybrid' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in hybrid selection: {str(e)}" + + def _entropy_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using existing entropy selecting methods""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + + # using entropy selecting function + selected_indices = entropy_select(X, quality_scores, n_points) + + response = "Entropy-based Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'entropy' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in entropy selection: {str(e)}" + + def _graph_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using existing graph selection method""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + + # using graph selecting function + selected_indices = graph_select(X, quality_scores, n_points) + + response = "Graph-based Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'graph' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in graph selection: {str(e)}" + + + def _validate_parameters_tool(self, params: Dict) -> str: + validation_results = [] + + for param_name, value in params.items(): + if param_name in self.param_constraints: + constraint = self.param_constraints[param_name] + min_val, max_val = constraint['range'] + param_type = constraint['type'] + + if value < min_val or value > max_val: + validation_results.append(f" {param_name}={value} outside range [{min_val}, {max_val}]") + else: + validation_results.append(f" {param_name}={value} within valid range") + + if self._validate_domain_constraints(params): + validation_results.append("Domain constraints satisfied") + else: + validation_results.append("Domain constraints violated") + + return "Parameter Validation:\n" + "\n".join(validation_results) + + + def _load_config(self) -> Dict[str, Any]: + """Load the configuration from 'opt_config.json'.""" + with open('opt_config.json', 'r') as f: + config = json.load(f) + return config + + def _load_initial_params(self) -> Dict[str, Any]: + """Load initial parameters from the design's config.mk file""" + config_path = f"designs/{self.platform}/{self.design}/config.mk" + params = {} + with open(config_path, 'r') as f: + for line in f: + if line.startswith('export'): + parts = line.strip().split('=', 1) + if len(parts) == 2: + key = parts[0].replace('export', '').strip() + value = parts[1].strip() + params[key] = value + return params + + def _load_sdc_context(self) -> Dict[str, Any]: + """Load SDC context including special case for JPEG""" + sdc_context = {} + + # Determine SDC filename based on platform/design + if self.platform.lower() == 'asap7' and self.design.lower() == 'jpeg': + sdc_file = 'jpeg_encoder15_7nm.sdc' + else: + sdc_file = 'constraint.sdc' + + sdc_path = f"designs/{self.platform}/{self.design}/{sdc_file}" + + # Read SDC file + try: + with open(sdc_path, 'r') as f: + sdc_content = f.read() + + # Extract clock period + clock_period_match = re.search(r'set clk_period\s+([\d.]+)', sdc_content) + if clock_period_match: + sdc_context['clock_period'] = float(clock_period_match.group(1)) + + # Store full content for context + sdc_context['content'] = sdc_content + sdc_context['filename'] = sdc_file + + except Exception as e: + print(f"Warning: Could not load SDC file {sdc_path}: {str(e)}") + sdc_context['error'] = str(e) + + return sdc_context + + + def _generate_llm_prompt(self, stage: str, data: Dict[str, Any]) -> str: + + constraints_text = "Parameter Constraints:\n" + for param, info in self.param_constraints.items(): + param_type = info['type'] + param_range = info['range'] + constraints_text += f"- {param} ({param_type}, range: {param_range})\n" + + tool_instructions = { + 'inspect': ( + f"**Stage: Inspect**\n" + "In this stage, we analyze the data from previous optimization runs to identify patterns, trends, and insights.\n\n" + f"Data to analyze:\n{json.dumps(data, indent=2, default=str)}\n\n" + "Please analyze the data and provide insights on:\n" + "1. Key patterns in successful vs unsuccessful runs.\n" + "2. Parameter ranges that appear promising.\n" + "3. Any timing or wirelength trends.\n" + "4. Recommendations for subsequent runs.\n" + "5. We hope to further reduce the total wirelength.\n" + ), + + 'model': ( + f"**Stage: Model**\n" + "In this stage, we decide how to model the optimization problem based on the data analysis.\n\n" + f"Data for modeling:\n{json.dumps(data, indent=2, default=str)}\n\n" + "Please suggest:\n" + "1. Appropriate modeling techniques.\n" + "2. Key parameters to focus on.\n" + "3. Surrogate model recommendations.\n" + "4. Acquisition function choices.\n" + ), + + 'agglomerate': ( + f"**Stage: Agglomerate**\n" + "In this stage, we generate new parameter combinations to explore in the next optimization runs.\n\n" + "Please provide a list of new parameter sets to try, ensuring they respect the domain constraints below.\n\n" + f"{constraints_text}\n" + "Each parameter set should be a dictionary with parameter names and their suggested values.\n" + "**Important:** Make sure all parameter sets satisfy the domain constraints before suggesting them.\n" + ) + } + + stage_contexts = { + 'inspect': ( + f"metrics analyze: Total runs={data.get('log_data', {}).get('summary', {}).get('total_runs', 0)}, " + f"successful runs ={data.get('log_data', {}).get('summary', {}).get('successful_runs', 0)}" + ), + 'model': "Configure modeling methods based on inspection results", + 'agglomerate': "Configure parameter selection strategy based on modeling results" + } + + prompt = f"""**stages:{stage.upper()}** + + {stage_contexts.get(stage, '')} + + {tool_instructions.get(stage, '')} + + **Important: Use only tool calls and do not generate text replies!** + """ + + # ========= Splicing RAG ========= + rag_context = "" + if self.rag_model is not None and self.rag_embeddings is not None: + try: + print("[DEBUG] RAG: Starting retrieval...") + + # Step 1: Extract error information + error_summary = "" + if "log_data" in data: + all_errors = [] + for run in data["log_data"].get("runs", []): + if run.get("errors"): + all_errors.extend(run["errors"]) + if all_errors: + # Retrieve the most recent or frequent errors + top_errors = all_errors[-3:] # Last 3 posts + error_summary = "\n".join(top_errors) + print(f"[DEBUG] Detected {len(all_errors)} error messages. Sample:\n{error_summary}") + + # Step 2: Construct RAG query + if error_summary: + query = ( + f"Stage: {stage}. Objective: {self.objective}. " + f"The recent optimization runs failed with errors:\n{error_summary}\n\n" + "Retrieve relevant OpenROAD documentation, known failure modes, and " + "potential parameter tuning suggestions that may fix these issues." + ) + else: + query = ( + f"Stage: {stage}. Objective: {self.objective}. " + f"Focus on analyzing {stage}-related optimization results. " + f"Important metrics include wirelength, timing, area, and success rate. " + f"Find relevant OpenROAD documentation, parameter tuning guides, and failure pattern examples." + ) + + # Step 3: Execute search + rag_context = answerWithRAG( + query, + self.rag_embeddings, + self.rag_model, + self.rag_docs, + self.rag_docsDict, + ) + + if isinstance(rag_context, dict): # If returning dict + print(f"[DEBUG] RAG Retrieved {len(rag_context.get('docs', []))} related entries.") + for doc in rag_context.get("docs", [])[:3]: + print(f" ↳ {doc['title']} (score={doc['score']:.3f}) from {doc['source']}") + retrieved_text = rag_context.get("content", "") + else: + retrieved_text = rag_context + + # Step 4: add to prompt + if retrieved_text.strip(): + prompt += ( + "\n\n=== Retrieved OpenROAD Documentation (via RAG) ===\n" + f"{retrieved_text}\n" + "==============================================" + ) + print("[DEBUG] RAG: Context successfully added to prompt.") + else: + print("[DEBUG] RAG: Empty context retrieved.") + except Exception as e: + prompt += f"\n\n[WARN] RAG retrieval failed: {e}" + + if "log_data" in data: + all_errors = [] + for run in data["log_data"].get("runs", []): + if run.get("errors"): + all_errors.extend(run["errors"]) + + if all_errors: + error_summary = "\n".join(all_errors[-5:]) # The last 5 errors + prompt += f""" + + ### Detected Run Errors + {error_summary} + + The model must now act as an **EDA Debugging Assistant**. + Using the retrieved documentation and knowledge, analyze the errors above and: + 1. Identify the root causes of each error (e.g., tool misconfiguration, parameter overflow, timing issues, etc.) + 2. Suggest **specific parameter changes or flow adjustments** to prevent these errors. + 3. Indicate whether the error is likely due to constraints, routing congestion, or timing margin. + 4. Provide a short explanation for each suggestion. + + Output format: + Error Diagnosis: + - Root Cause: ... + - Recommended Fix: ... + - Suggested Parameter Change: ... + - Reason: ... + + """ + print("[DEBUG] Added error-fix section to prompt.") + def _collect_recent_errors(self, data: Dict[str, Any], max_errors=5) -> str: + errors = [] + for run in data.get("log_data", {}).get("runs", []): + if run.get("errors"): + errors.extend(run["errors"]) + print(f"[DEBUG] Found total {len(errors)} errors in all runs.") + return "\n".join(errors[-max_errors:]) if errors else "No errors detected." + + def _call_llm(self, stage: str, data: Dict[str, Any]) -> Dict[str, Any]: + # """Call Claude to get recommendations for optimization parameters""" + # print(f"\n=== Calling LLM for {stage} stage ===") + """Call LLM to get recommendations for optimization parameters using react framework""" + print(f"\n=== Calling LLM with ReAct framework for {stage} stage ===") + + try: + react_prompt = self._generate_react_prompt(stage, data) + print(f"Generated prompt with context for {stage}") + print("=== Context Message ===") + print(react_prompt) + print("========================") + available_tools = self._create_react_tools(stage, data) + + react_result = self.react_framework.run_react_cycle( + initial_prompt=react_prompt, + available_tools=available_tools, + max_steps=3, + temperature=0.1 + ) + # === If an error occurs, enter Debug mode === + if "log_data" in data and any(run.get("errors") for run in data["log_data"].get("runs", [])): + print("\n[DEBUG] Detected errors in previous runs. Invoking Debug Assistant mode...") + + # Collect error information + all_errors = [] + for run in data["log_data"]["runs"]: + if run.get("errors"): + all_errors.extend(run["errors"]) + error_text = "\n".join(all_errors[-5:]) # Recent entries + + # Construct a Debug Prompt + debug_prompt = f""" + You are now an **EDA Debugging Expert**. + Based on the following OpenROAD errors and RAG documentation, analyze and provide concrete repair suggestions. + + Errors Detected: + {error_text} + + Please identify: + 1. Root cause of each error. + 2. Specific parameter changes (e.g., in floorplan, CTS, or routing stages) that could fix the issue. + 3. Whether this issue is due to timing, congestion, or setup misconfiguration. + 4. One short explanation per fix. + + Return your answer in **JSON format** like: + {{ + "error_analysis": [ + {{ + "error": "...", + "cause": "...", + "fix": "...", + "params_to_adjust": {{"param_name": "new_value"}} + }} + ] + }} + """ + + # Call LLM to output repair suggestions + debug_result = self.react_framework.run_react_cycle( + initial_prompt=debug_prompt, + available_tools=available_tools, + max_steps=1, + temperature=0.2 + ) + + print("\n[DEBUG] LLM Debug Assistant Result:") + print(debug_result.get("final_answer", "")) + + # Save repair suggestions to the main results + react_result["error_fix_suggestions"] = debug_result.get("final_answer", "") + # Write files for manual viewing + with open("logs/error_fix_suggestions.json", "w") as f: + f.write(debug_result.get("final_answer", "")) + print(f"\n=== ReAct Cycle Completed ===") + print(f"Completed steps: {react_result.get('completed_steps', 0)}/{react_result.get('max_steps', 8)}") + print(f"Final Answer: {react_result['final_answer']}") + + configs = self._parse_react_final_answer(react_result["final_answer"], stage) + + if react_result.get('reasoning_history'): + print(f"\n=== Reasoning History ({len(react_result['reasoning_history'])} steps) ===") + for step in react_result['reasoning_history']: + print(f"Step {step['step']}: {step.get('thought', 'No thought')}") + + print(f"Returning config for stage '{stage}': {configs}") + return configs + + except Exception as e: + print(f"Error in LLM call for stage {stage}: {e}") + default_config = { + 'inspect': {"n_clusters": 5, "correlation_threshold": 0.5}, + 'model': {"kernel_type": "matern", "preprocessing": "robust", + "acquisition": "ei", "surrogate_weight": 0.8}, + 'agglomerate': {"method": "hybrid", "quality_weight": 0.7, + "uncertainty_bonus": 0.2} + } + return default_config.get(stage, {}) + + + def _generate_react_prompt(self, stage: str, data: Dict[str, Any]) -> str: + """generate prompts of ReAct framework""" + + stage_descriptions = { + 'inspect': ( + "You are an expert EDA optimization analyst. Analyze the optimization run data to identify patterns " + "and insights. Use the available tools to examine data distributions, correlations, and successful " + "parameter ranges. Your goal is to understand what makes runs successful and provide recommendations " + "for the modeling stage." + ), + 'model': ( + "You are an expert machine learning engineer for EDA optimization. Based on the inspection results, " + "configure the modeling approach for Bayesian optimization. Consider kernel selection, acquisition " + "functions, and surrogate modeling strategies. Balance exploration and exploitation based on the data." + ), + 'agglomerate': ( + "You are an expert parameter optimization specialist. Generate new parameter combinations for the " + "next optimization iteration. Use insights from previous stages to focus on promising regions while " + "maintaining diversity. Ensure all parameters satisfy the domain constraints." + ) + } + + constraints_text = "Parameter Constraints:\n" + for param, info in self.param_constraints.items(): + constraints_text += f"- {param} ({info['type']}, range: {info['range']})\n" + + react_format_instructions = """ +**ReAct Framework Instructions - MUST FOLLOW THIS FORMAT:** + +1. **Thought**: Analyze the current situation and decide what to do next +2. **Action**: Choose one tool from the available tools +3. **Action Input**: Provide the appropriate input for the chosen tool +4. **Observation**: Wait for the tool's response, then continue reasoning + +**Available Tools**: You have access to various analysis tools. Use them to gather information before making decisions. + +**DO NOT include Final Answer until you have completed all necessary analysis.** +**DO NOT predict or simulate tool observations.** +**You will receive actual Observation from tools before continuing.** + +Only after proper analysis: +**Final Answer Format**: Only when you have completed your analysis, provide: +Final Answer: {your_configuration_here} + +**Example**: +Thought: I need to understand the data patterns first. Let me analyze the success rates. +Action: analyze_data_patterns +Action Input: {} +Observation: [Tool response...] +Thought: Now I need to check parameter correlations... +Action: analyze_correlations +Action Input: {} +Observation: [Tool response...] +Final Answer: {"n_clusters": 5, "correlation_threshold": 0.7} +""" + + prompt = f""" + {stage_descriptions[stage]} + + **Current Stage**: {stage.upper()} + **Objective**: {self.objective} + **Platform**: {self.platform} + **Design**: {self.design} + + **Available Data**: + - Total runs: {data.get('log_data', {}).get('summary', {}).get('total_runs', 0)} + - Successful runs: {data.get('log_data', {}).get('summary', {}).get('successful_runs', 0)} + - Failed runs: {data.get('log_data', {}).get('summary', {}).get('failed_runs', 0)} + + {constraints_text} + {react_format_instructions} + + Begin your analysis: + """ + + rag_context = "" + # ======== extract errors ======== + error_summary = self._collect_recent_errors(data) + if error_summary and "No errors" not in error_summary: + print("[DEBUG] RAG: Detected error summary, adding error analysis prompt...") + prompt += f""" + + ### Detected Run Errors + {error_summary} + + You are now acting as an **EDA Debugging Assistant**. + Analyze the errors above and: + 1. Identify the root causes. + 2. Suggest specific parameter changes. + 3. Indicate whether the error is due to timing, routing, or constraints. + 4. Provide short explanations for each. + + Output format: + Error Diagnosis: + - Root Cause: ... + - Recommended Fix: ... + - Suggested Parameter Change: ... + - Reason: ... + """ + else: + print("[DEBUG] No errors found in logs for this stage.") + if getattr(self, "supervision_feedback", ""): + prompt += f""" + + ### Supervisor Feedback + {self.supervision_feedback} + + Please prioritize these supervisor notes when making decisions in this stage. + """ + print("[SUPERVISOR][DEBUG] Added supervisor feedback into prompt.") + if self.rag_model is not None and self.rag_embeddings is not None: + try: + print("[DEBUG] RAG: Starting retrieval...") + query = ( + f"Stage: {stage}. Objective: {self.objective}. " + f"Focus on analyzing {stage}-related optimization results. " + f"Important metrics include wirelength, timing, area, and success rate. " + f"Find relevant OpenROAD documentation, parameter tuning guides, and failure pattern examples." + ) + rag_context = answerWithRAG( + query, + self.rag_embeddings, + self.rag_model, + self.rag_docs, + self.rag_docsDict + ) + print(f"[DEBUG] RAG: Retrieved context length = {len(rag_context)}") + if rag_context.strip(): + prompt += ( + "\n\n=== Retrieved OpenROAD Documentation (via RAG) ===\n" + f"{rag_context}\n" + "==============================================" + ) + print("[DEBUG] RAG: Context successfully added to prompt.") + else: + print("[DEBUG] RAG: Empty context retrieved.") + except Exception as e: + prompt += f"\n\n[WARN] RAG retrieval failed: {e}" + + return prompt + + def _parse_react_final_answer(self, final_answer: str, stage: str) -> Dict[str, Any]: + """parse react final answer""" + + default_configs = { + 'inspect': {"n_clusters": 5, "correlation_threshold": 0.5}, + 'model': {"kernel_type": "matern", "preprocessing": "robust", + "acquisition": "ei", "surrogate_weight": 0.8}, + 'selection': {"method": "hybrid", "quality_weight": 0.7, + "uncertainty_bonus": 0.2} + } + + configs = {} + + if final_answer and "Reached maximum steps" not in final_answer: + try: + json_match = re.search(r'\{.*\}', final_answer, re.DOTALL) + if json_match: + extracted_config = json.loads(json_match.group()) + configs[stage] = extracted_config + print(f"✓ Extracted configuration from ReAct response: {extracted_config}") + else: + configs[stage] = default_configs.get(stage, {}) + print(f"Using default configuration for {stage} stage") + except Exception as e: + print(f"Error parsing ReAct final answer: {e}") + configs[stage] = default_configs.get(stage, {}) + else: + configs[stage] = default_configs.get(stage, {}) + print(f"ReAct failed to produce answer, using default for {stage}") + + return configs + + def run_iteration(self, num_runs: int) -> Dict[str, Any]: + """Run a single inspect-optimize-agglomerate flow and return its summary.""" + return self._execute_inspect_optimize_flow(num_runs, flow_index=0) + + def run_dual_supervised_iterations(self, num_runs: int, num_flows: int) -> None: + """ + Run multiple inspect-optimize-agglomerate flows with supervisor feedback injected + into the next flow's prompt. + """ + if num_flows <= 0: + print("[WARN] num_flows must be >= 1, skipping execution.") + return + + self.supervision_feedback = "" + for flow_index in range(num_flows): + print(f"\n=== Dual-Supervised Flow {flow_index + 1}/{num_flows} ===") + flow_summary = self._execute_inspect_optimize_flow(num_runs, flow_index=flow_index) + supervisor_feedback = self._run_supervisor_review(flow_summary, flow_index) + if supervisor_feedback: + self.supervision_feedback = supervisor_feedback + print("[SUPERVISOR] Stored feedback for the next flow iteration.") + else: + print("[SUPERVISOR] Supervisor produced no feedback; continuing without updates.") + + def _execute_inspect_optimize_flow(self, num_runs: int, flow_index: int = 0) -> Dict[str, Any]: + """Internal helper containing the original inspect-optimize-agglomerate flow.""" + print(f"\n=== Starting optimization iteration #{flow_index + 1} for {self.platform}/{self.design} ===") + print(f"Objective: {self.objective}") + print(f"Number of runs requested: {num_runs}") + + # Step 1: Inspect logs + print("\nStep 1: Inspecting logs...") + log_data = self.inspect_logs() + print(f"Found {log_data['summary']['total_runs']} total runs, " + f"{log_data['summary']['successful_runs']} successful") + + # Get LLM recommendations for inspection and analysis + print("\nGetting LLM recommendations with ReAct framework for inspection...") + inspect_configs = self._call_llm('inspect', { + 'log_data': log_data, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context + }) + inspection_config = inspect_configs.get('inspect', {}) + print(f"React inspection config: {inspection_config}") + + # Step 2: Analyze metrics with LLM config + print("\nStep 2: Analyzing metrics ...") + metrics = self.analyze_metrics( + log_data, + n_clusters=inspection_config.get('n_clusters', 5), + correlation_threshold=inspection_config.get('correlation_threshold', 0.5) + ) + print(f"Processed metrics for {len(metrics.get('objectives', []))} successful runs") + + # Get LLM recommendations for modeling based on inspection results with ReAct framework + print("\nGetting LLM recommendations with ReAct framework for modeling...") + model_configs = self._call_llm('model', { + 'log_data': log_data, + 'metrics': metrics, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs + }) + model_config = model_configs.get('model', {}) + print(f"LLM model config: {model_config}") + + # Step 3: Evaluate models with LLM config + print("\nStep 3: Evaluating models...") + model_results = self.evaluate_models( + log_data, metrics, + model_config.get('kernel_type', 'matern'), + preprocessing=model_config.get('preprocessing', 'robust'), + acquisition=model_config.get('acquisition', 'ei'), + surrogate_weight=model_config.get('surrogate_weight', 0.8) + ) + + # Get LLM recommendations for parameter selection based on all previous results with ReAct framework + print("\nGetting LLM recommendations with ReAct framework for parameter selection...") + selection_configs = self._call_llm('agglomerate', { + 'log_data': log_data, + 'metrics': metrics, + 'model_results': model_results, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs, + 'model_configs': model_configs + }) + selection_config = selection_configs.get('agglomerate', {}) + print(f"LLM selection config: {selection_config}") + + # Step 4: Generate parameters with LLM config + print("\nStep 4: Generating parameters...") + self.generate_parameters( + log_data, metrics, model_results, num_runs, + selection_method=selection_config.get('method', 'hybrid'), + quality_weight=selection_config.get('quality_weight', 0.7), + uncertainty_bonus=selection_config.get('uncertainty_bonus', 0.2) + ) + + flow_summary = { + "flow_index": flow_index, + "log_data": log_data, + "metrics": metrics, + "model_results": model_results, + "inspection_config": inspection_config, + "model_config": model_config, + "selection_config": selection_config, + "num_runs": num_runs, + "recent_errors": self._collect_recent_errors({"log_data": log_data}) + } + return flow_summary + + def _run_supervisor_review(self, flow_summary: Dict[str, Any], flow_index: int) -> str: + """ + Use a secondary model to critique the previous flow and return feedback + for the next prompt. + """ + flow_snapshot = { + "log_summary": flow_summary.get("log_data", {}).get("summary", {}), + "inspection_config": flow_summary.get("inspection_config", {}), + "model_config": flow_summary.get("model_config", {}), + "selection_config": flow_summary.get("selection_config", {}), + "recent_errors": flow_summary.get("recent_errors", ""), + "objective": self.objective, + "platform": self.platform, + "design": self.design, + } + + supervisor_prompt = ( + "You are the supervisor model for an EDA optimization agent.\n" + "The primary agent just finished an inspect-optimize-agglomerate flow.\n" + "Provide concise feedback (<=300 words) to guide the next flow. " + "Focus on:\n" + "1) What to adjust in inspection/model/selection configs,\n" + "2) Specific parameter or constraint reminders,\n" + "3) Warnings about errors or data issues.\n" + "Return plain text; start the message with 'Supervisor Feedback:'.\n" + f"Flow #{flow_index + 1} summary (JSON):\n{json.dumps(flow_snapshot, ensure_ascii=False, indent=2)}" + ) + print(f"[SUPERVISOR] Supervisor prompt: {supervisor_prompt}") + + try: + response = self.supervisor_client.chat.completions.create( + model=self.supervisor_model_name, + messages=[ + { + "role": "system", + "content": "You are a senior EDA optimization reviewer. Be concise and actionable.", + }, + {"role": "user", "content": supervisor_prompt}, + ], + temperature=0.2, + max_tokens=2048, + ) + feedback = response.choices[0].message.content.strip() + print(f"[SUPERVISOR] Feedback generated (len={len(feedback)}).") + return feedback + except Exception as e: + print(f"[SUPERVISOR] Failed to generate feedback: {e}") + return "" + + def inspect_logs(self) -> Dict[str, Any]: + """Step 1: Inspect all .log and .json logs recursively""" + log_dir = "logs" + pattern = f"{self.platform}_{self.design}_run" + + log_data = { + 'runs': [], + 'summary': { + 'total_runs': 0, + 'successful_runs': 0, + 'failed_runs': 0 + } + } + + if not os.path.exists(log_dir): + return log_data + + run_groups = {} + + for root, _, files in os.walk(log_dir): + for log_file in files: + if log_file.endswith(('.log', '.json')): + log_path = os.path.join(root, log_file) + + if log_file.startswith(pattern) or (self.platform in root and self.design in root): + + run_id = "main" + m = re.search(r'_run(\d+)\.log$', log_file) + if m: + run_id = f"base_{m.group(1)}" + + elif 'base_' in root: + run_id = os.path.basename(root) + + run_data = process_log_file(log_path) + + if run_id not in run_groups: + run_groups[run_id] = { + 'run_id': run_id, + 'success': True, + 'metrics': {}, + 'errors': [], + 'files': [] + } + + run_groups[run_id]['success'] &= run_data.get('success', True) + run_groups[run_id]['files'].append(log_path) + + if 'metrics' in run_data and run_data['metrics']: + run_groups[run_id]['metrics'].update(run_data['metrics']) + + if 'errors' in run_data and run_data['errors']: + run_groups[run_id]['errors'].extend(run_data['errors']) + + for run_id, run_data in run_groups.items(): + print(f"DEBUG: Run {run_id} success: {run_data['success']}") + print(f"DEBUG: Run {run_id} metrics: {run_data['metrics']}") + print(f"DEBUG: Run {run_id} errors: {run_data['errors']}") + print(f"DEBUG: Run {run_id} files: {run_data['files']}") + + log_data['runs'].append(run_data) + log_data['summary']['total_runs'] += 1 + if run_data['success']: + log_data['summary']['successful_runs'] += 1 + else: + log_data['summary']['failed_runs'] += 1 + + return log_data + + + def analyze_metrics(self, log_data: Dict[str, Any], n_clusters: int, correlation_threshold: float) -> Dict[str, Any]: + """Step 2: Analyze metrics from log data with improved analysis""" + metrics = { + 'objectives': [], + 'surrogates': [], + 'correlations': {}, + 'structure_analysis': {} + } + + # Extract feature vectors and objectives + feature_vectors = [] + objective_values = [] + surrogate_values = [] + + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + run_metrics = run['metrics'] + obj_values = self._calculate_objective(run) + + if obj_values['value'] is not None or obj_values['surrogate'] is not None: + # Extract parameter values as features + params = [] + for param in self.parameter_names: + params.append(float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0)))) + feature_vectors.append(params) + + objective_values.append(obj_values['value'] if obj_values['value'] is not None else np.nan) + surrogate_values.append(obj_values['surrogate'] if obj_values['surrogate'] is not None else np.nan) + + # Track correlations and other metrics + if obj_values['value'] is not None: + metrics['objectives'].append(obj_values['value']) + if obj_values['surrogate'] is not None: + metrics['surrogates'].append(obj_values['surrogate']) + + if obj_values['value'] is not None and obj_values['surrogate'] is not None: + if 'real_vs_surrogate' not in metrics['correlations']: + metrics['correlations']['real_vs_surrogate'] = [] + metrics['correlations']['real_vs_surrogate'].append({ + 'real': obj_values['value'], + 'surrogate': obj_values['surrogate'] + }) + + if feature_vectors: + X = np.array(feature_vectors) + Y = np.array(objective_values) + Y_surrogate = np.array(surrogate_values) + + # Use improved inspection functions + metrics['distribution_analysis'] = inspect_data_distribution(X, Y, Y_surrogate) + metrics['structure_analysis'] = inspect_data_structure(X, Y, { + 'n_clusters': n_clusters, + 'correlation_threshold': correlation_threshold + }) + + # Extract model recommendations if available (from new functions) + if 'model_recommendations' in metrics['structure_analysis']: + metrics['model_recommendations'] = metrics['structure_analysis']['model_recommendations'] + + # Add objective-specific metrics + if self.objective == 'ECP': + metrics['clock_period_impact'] = {} + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + period = float(run['metrics'].get('clock_period', 0)) + if period > 0: + if period not in metrics['clock_period_impact']: + metrics['clock_period_impact'][period] = { + 'final_slack': [], + 'cts_slack': [] + } + if 'worst_slack' in run['metrics']: + metrics['clock_period_impact'][period]['final_slack'].append( + float(run['metrics']['worst_slack'])) + if 'cts_ws' in run['metrics']: + metrics['clock_period_impact'][period]['cts_slack'].append( + float(run['metrics']['cts_ws'])) + + elif self.objective == 'DWL': + metrics['wirelength_progression'] = [] + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + if 'cts_wirelength' in run['metrics'] and 'total_wirelength' in run['metrics']: + metrics['wirelength_progression'].append({ + 'cts': float(run['metrics']['cts_wirelength']), + 'final': float(run['metrics']['total_wirelength']) + }) + + return metrics + + + def evaluate_models(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + kernel_type: str, preprocessing: str, acquisition: str, surrogate_weight: float) -> Dict[str, Any]: + """Step 3: Use improved model functions to evaluate parameter quality""" + model_results = {} + + # Build context from log data and metrics + context = { + 'log_data': log_data, + 'metrics': metrics, + 'design_config': self.design_config, + 'initial_params': self.initial_params, + 'model_recommendations': metrics.get('model_recommendations', {}) + } + + # Use model recommendations if available (from new functions) + if 'model_recommendations' in metrics: + kernel_type = metrics['model_recommendations'].get('kernel_type', kernel_type) + preprocessing = 'robust' if metrics['model_recommendations'].get('needs_feature_scaling', True) else 'none' + + # Call appropriate model functions with improved modeling + if self.objective == 'ECP': + model_results = evaluate_timing_model(context) + elif self.objective == 'DWL': + model_results = evaluate_wirelength_model(context) + + # Add model configuration used + model_results['configuration'] = { + 'kernel_type': kernel_type, + 'preprocessing': preprocessing, + 'acquisition': acquisition, + 'surrogate_weight': surrogate_weight + } + + return model_results + + def generate_parameters(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + model_results: Dict[str, Any], num_runs: int, + selection_method: str = 'hybrid', quality_weight: float = 0.7, + uncertainty_bonus: float = 0.2, model_config: Dict[str, Any] = None) -> None: + """Step 4: Generate parameter combinations and write to CSV""" + # Get list of parameters to optimize from constraints + param_names = list(self.param_constraints.keys()) + print(f"\nGenerating parameters for {len(param_names)} variables:") + for name in param_names: + print(f" - {name}: {self.param_constraints[name]}") + + # Extract successful runs for training data + successful_params = [] + successful_objectives = [] + for run in log_data.get('runs', []): + if run.get('success', False) and 'metrics' in run: + params = {} + for param in param_names: + params[param] = float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0))) + successful_params.append(params) + + obj = self._calculate_objective(run) + successful_objectives.append(obj['value'] if obj['value'] is not None else obj['surrogate']) + + print(f"Using {len(successful_params)} successful runs as training data") + + # Convert to numpy arrays + if successful_params: + X = np.array([[params[name] for name in param_names] for params in successful_params]) + y = np.array(successful_objectives) + else: + print("Warning: No successful runs, using initial parameters as base") + X = np.array([[float(self.initial_params.get(name, 0)) for name in param_names]]) + y = np.array([0.0]) + + # Get kernel type from model config + kernel_type = model_config.get('kernel_type', 'matern') if model_config else 'matern' + print(f"\nCreating surrogate model with {kernel_type} kernel") + model = create_model(X, y, kernel_type=kernel_type) + + # Generate candidates + n_candidates = num_runs * 10 + print(f"Generating {n_candidates} candidate points") + candidates = latin_hypercube(n_candidates, len(param_names)) + + # Scale candidates to parameter ranges + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + candidates[:, i] = candidates[:, i] * (max_val - min_val) + min_val + + # Get predictions + predictions, uncertainties = model.predict(candidates, return_std=True) + + # Select points + print(f"\nSelecting points using {selection_method} method") + print(f"Quality weight: {quality_weight}, Uncertainty bonus: {uncertainty_bonus}") + quality_scores = create_quality_scores(candidates, y, predictions, uncertainties) + selected_indices = select_points( + candidates, quality_scores, + method=selection_method, + n_points=num_runs, + config={"quality_weight": quality_weight, + "uncertainty_bonus": uncertainty_bonus} + ) + + selected_params = candidates[selected_indices] + + # Validate domain constraints + print("\nValidating domain constraints...") + valid_params = [] + for params in selected_params: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + else: + print("Warning: Parameter set failed domain constraints") + + print(f"Found {len(valid_params)} valid parameter sets out of {len(selected_params)}") + + # Generate more if needed + while len(valid_params) < num_runs: + needed = num_runs - len(valid_params) + print(f"Generating {needed} additional parameter sets...") + new_candidates = latin_hypercube(needed, len(param_names)) + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + new_candidates[:, i] = new_candidates[:, i] * (max_val - min_val) + min_val + + for params in new_candidates: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + if len(valid_params) >= num_runs: + break + + # Write to CSV + print(f"\nWriting {num_runs} parameter sets to CSV...") + self._write_params_to_csv(valid_params[:num_runs]) + + def _calculate_objective(self, run: Dict[str, Any]) -> Dict[str, float]: + """Calculate objective value and surrogate from run metrics""" + metrics = run.get('metrics', {}) + result = {'value': None, 'surrogate': None} + + if self.objective == 'ECP': + if 'clock_period' in metrics: + period = float(metrics['clock_period']) + # Real ECP from final worst slack + if 'worst_slack' in metrics: + result['value'] = period - float(metrics['worst_slack']) + # Surrogate ECP from CTS worst slack + if 'cts_ws' in metrics: + result['surrogate'] = period - float(metrics['cts_ws']) + + elif self.objective == 'DWL': + # Real wirelength from detailed route + if 'total_wirelength' in metrics: + result['value'] = float(metrics['total_wirelength']) + # Surrogate wirelength from CTS + if 'cts_wirelength' in metrics: + result['surrogate'] = float(metrics['cts_wirelength']) + + elif self.objective == 'COMBO': + # Get weights from environment variables + try: + ecp_weight = float(os.environ.get('ECP_WEIGHT')) + wl_weight = float(os.environ.get('WL_WEIGHT')) + ecp_weight_surrogate = float(os.environ.get('ECP_WEIGHT_SURROGATE')) + wl_weight_surrogate = float(os.environ.get('WL_WEIGHT_SURROGATE')) + except (ValueError, TypeError): + raise ValueError("Weights not properly set in environment variables.") + + # Calculate real ECP and WL values + ecp_value = None + wl_value = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'worst_slack' in metrics: + ecp_value = clock_period - float(metrics['worst_slack']) + if 'total_wirelength' in metrics: + wl_value = float(metrics['total_wirelength']) + + # Calculate surrogate ECP and WL values + ecp_surrogate = None + wl_surrogate = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'cts_ws' in metrics: + ecp_surrogate = clock_period - float(metrics['cts_ws']) + if 'cts_wirelength' in metrics: + wl_surrogate = float(metrics['cts_wirelength']) + + # Calculate weighted objective for real values + if ecp_value is not None and wl_value is not None: + result['value'] = ecp_weight * ecp_value + wl_weight * wl_value + elif ecp_value is not None: + result['value'] = ecp_weight * ecp_value + elif wl_value is not None: + result['value'] = wl_weight * wl_value + + # Calculate weighted surrogate objective + if ecp_surrogate is not None and wl_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + wl_weight_surrogate * wl_surrogate + elif ecp_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + elif wl_surrogate is not None: + result['surrogate'] = wl_weight_surrogate * wl_surrogate + + return result + + def _validate_domain_constraints(self, params: Dict[str, Any]) -> bool: + """Validate parameter combinations against domain constraints""" + # 1. Core utilization vs cell padding + core_util = float(params.get('core_util', 0)) + gp_pad = float(params.get('cell_pad_global', 0)) + dp_pad = float(params.get('cell_pad_detail', 0)) + + if core_util > 80 and (gp_pad > 2 or dp_pad > 2): + print(f"Domain constraint failed: core_util > 80 and gp_pad > 2 or dp_pad > 2") + return False + + # 2. TNS end percent vs place density + tns_end = float(params.get('tns', 0)) + place_density = float(params.get('lb_addon', 0)) + + if tns_end < 70 and place_density > 0.7: + print(f"Domain constraint failed: tns_end < 70 and place_density > 0.7") + return False + + # 3. CTS cluster constraints + cts_size = float(params.get('cts_size', 0)) + cts_diameter = float(params.get('cts_diameter', 0)) + + if cts_size > 30 and cts_diameter < 100: + print(f"Domain constraint failed: cts_size > 30 and cts_diameter < 100") + return False + + return True + + def _write_params_to_csv(self, params_list: List[Dict[str, Any]]) -> None: + """Write the new parameter sets to the expected CSV file for the next iteration""" + csv_file = f"designs/{self.platform}/{self.design}/{self.platform}_{self.design}.csv" + + # Ensure parameters are in correct order and properly typed + with open(csv_file, 'w', newline='\n') as f: # Explicitly use Unix line endings + writer = csv.writer(f) + # Write header in correct order + writer.writerow(self.parameter_names) + + # Write parameter rows + for params in params_list: + row = [] + for param_name in self.parameter_names: + value = params.get(param_name) + if value is None: + print(f"Warning: Missing value for parameter {param_name}") + continue + + # Apply type constraints + constraint = self.param_constraints[param_name] + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param_name} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + + except (ValueError, TypeError) as e: + print(f"Error converting {param_name} value '{value}' to {param_type}: {e}") + continue + + row.append(value) + + if len(row) == len(self.parameter_names): + writer.writerow(row) + else: + print(f"Warning: Skipping incomplete parameter set") + + print(f"New parameter sets written to {csv_file}") + + def _parse_llm_output(self, llm_response: str) -> List[Dict[str, Any]]: + """Parse the LLM's response and enforce parameter constraints""" + try: + param_sets = json.loads(llm_response) + except json.JSONDecodeError as e: + print(f"Error parsing LLM response: {e}") + return [] + + constrained_params = [] + for param_set in param_sets: + ordered_params = {} + valid = True + for param in self.parameter_names: + value = param_set.get(param) + if value is None: + print(f"Parameter '{param}' is missing in the LLM output.") + valid = False + break + + constraint = self.param_constraints.get(param) + if constraint: + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + elif param_type != 'float': + raise ValueError(f"Unsupported parameter type: {param_type}") + + ordered_params[param] = value + except (ValueError, TypeError) as e: + print(f"Parameter '{param}' has invalid value '{value}': {e}") + valid = False + break + else: + print(f"Unknown parameter '{param}' in parameter set.") + valid = False + break + + if valid and self._validate_domain_constraints(ordered_params): + constrained_params.append(ordered_params) + else: + print(f"Parameter set {ordered_params} failed validation and will be discarded.") + + return constrained_params + + def generate_initial_parameters(self, num_runs: int) -> None: + """Generate initial random parameters and write them to CSV using the same method as subsequent iterations""" + params_list = [] + for _ in range(num_runs): + params = {} + for param in self.parameter_names: + info = self.param_constraints[param] + param_type = info['type'] + min_value, max_value = info['range'] + if param_type == 'int': + value = random.randint(int(min_value), int(max_value)) + elif param_type == 'float': + value = random.uniform(min_value, max_value) + else: + continue # Skip unsupported types + params[param] = value + params_list.append(params) + + # Use the same method to write parameters to CSV + self._write_params_to_csv(params_list) + +def main(): + if len(sys.argv) not in (5, 6): + print("Usage: optimize_dual.py []") + sys.exit(1) + + platform = sys.argv[1] + design = sys.argv[2] + objective = sys.argv[3] + num_runs = int(sys.argv[4]) + num_flows = int(sys.argv[5]) if len(sys.argv) == 6 else 1 + + workflow = OptimizationWorkflow(platform, design, objective) + # Keep backward compatibility: a single flow behaves like the legacy run_iteration. + workflow.run_dual_supervised_iterations(num_runs, num_flows) + +if __name__ == "__main__": + main() diff --git a/flow-Agent/optimize_textgrad.py b/flow-Agent/optimize_textgrad.py new file mode 100644 index 0000000..2588209 --- /dev/null +++ b/flow-Agent/optimize_textgrad.py @@ -0,0 +1,2699 @@ +#!/usr/bin/env python3 +import json +import os +import sys +import re +import numpy as np +from typing import Dict, List, Any, Tuple, Optional +import anthropic +import csv +import random +from rag.util import answerWithRAG +from rag.index import load_embeddings_and_docs, build_and_save_embeddings +from sentence_transformers import SentenceTransformer +import torch +from pathlib import Path +from openai import OpenAI +from inspectfuncs import * +from modelfuncs import * +from agglomfuncs import * +import warnings +warnings.filterwarnings("ignore", category=RuntimeWarning) + +print("Python executable:", sys.executable) +print("sys.path:", sys.path[:3]) +print("Current working dir:", os.getcwd()) + +for pkg in ["anthropic", "sentence_transformers", "torch", "openai"]: + try: + __import__(pkg) + print(f" Imported {pkg}") + except ImportError as e: + print(f" Failed to import {pkg}: {e}") + +def process_log_file(log_path: str) -> Dict[str, Any]: + """Process a single log file to extract relevant metrics""" + run_data = { + 'file': os.path.basename(log_path), + 'success': False, + 'metrics': {}, + 'errors': [] + } + + with open(log_path, 'r') as f: + content = f.read() + print(f"File size: {len(content)} characters") + + # Extract timing information + timing_metrics = extract_timing_metrics(content) + run_data['metrics'].update(timing_metrics) + + # Extract wirelength information + wl_metrics = extract_wirelength_metrics(content) + run_data['metrics'].update(wl_metrics) + + # Extract any errors + errors = extract_errors(content) + run_data['errors'].extend(errors) + # === Inject a simulated error for testing RAG debugging === + # if "run3" in log_path: # 👈 你可以换成任意 run，比如 run1 或 run2 + # fake_error = "[ERROR] TEST_SIM: Simulated routing congestion failure" + # print(f"[DEBUG] Injected simulated error in {log_path}: {fake_error}") + # run_data['errors'].append(fake_error) + # run_data['success'] = False + + run_data['success'] = is_run_successful(content, errors) + + return run_data + +def extract_timing_metrics(log_content: str) -> Dict[str, float]: + """Extract timing-related metrics from log content""" + metrics = {} + + # Extract worst slack (final) + slack_match = re.search(r'(?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + if slack_match: + metrics['worst_slack'] = float(slack_match.group(1)) + + # Extract CTS worst slack + # cts_slack_match = re.search(r'(?:CTS|Clock Tree) (?:worst slack|WNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + cts_slack_match = re.search(r'Timing-driven:\s*(?:worst slack|WNS)\s+([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_slack_match: + metrics['cts_ws'] = float(cts_slack_match.group(1)) + + # Extract clock period + # period_match = re.search(r'[Cc]lock period:\s*([\d.]+)', log_content) + period_match = re.search(r'clock period to\s*([\d.]+)', log_content) + if period_match: + metrics['clock_period'] = float(period_match.group(1)) + + # Extract TNS + # tns_match = re.search(r'(?:Total negative slack|TNS):\s*([-\d.]+)', log_content, re.IGNORECASE) + tns_match = re.search(r'"finish__timing__setup__tns"\s*:\s*([-\d.eE]+)', log_content) + if tns_match: + metrics['tns'] = float(tns_match.group(1)) + + return metrics + +def extract_wirelength_metrics(log_content: str) -> Dict[str, float]: + """Extract wirelength-related metrics from log content""" + metrics = {} + + # Extract total wirelength + wl_match = re.search(r'Total wirelength: ([\d.]+)', log_content) + if wl_match: + metrics['total_wirelength'] = float(wl_match.group(1)) + + # Extract estimated wirelength after CTS + # cts_wl_match = re.search(r'Estimated wirelength: ([\d.]+)', log_content) + cts_wl_match = re.search(r'"?cts__route__wirelength__estimated"?\s*[:=]\s*([-\d.eE]+)', log_content, re.IGNORECASE) + if cts_wl_match: + metrics['cts_wirelength'] = float(cts_wl_match.group(1)) + + return metrics + +def extract_errors(log_content: str) -> List[str]: + """Extract error messages from log content""" + errors = [] + + # Look for common error patterns + error_patterns = [ + r'Error: .*', + r'ERROR: .*', + r'FATAL: .*', + r'Failed: .*' + ] + + for pattern in error_patterns: + matches = re.finditer(pattern, log_content, re.MULTILINE) + errors.extend(match.group(0) for match in matches) + + return errors + +def is_run_successful(log_content: str, errors: List[str], filename: str = "") -> bool: + """Determine if a run was successful based on log content and errors""" + if errors: + # If any real error lines were found, this file is a failure indicator + return False + + # Look for completion markers + completion_markers = [ + 'Flow complete', + 'Finished successfully', + 'Writing out GDS/OAS', + '6_report' + ] + + return any(marker in log_content for marker in completion_markers) + + +class ReActFramework: + """ReAct framework implementation""" + + def __init__(self, client, model_name="DeepSeek-R1"): + self.client = client + self.model_name = model_name + self.conversation_history = [] + + def add_to_history(self, role: str, content: str): + """add conversation history""" + self.conversation_history.append({"role": role, "content": content}) + + def clear_history(self): + """clear conversation history""" + self.conversation_history = [] + + def extract_thought_action(self, response: str) -> Tuple[str, str, str]: + """ + Extract Thought, Action, and Action Input from LLM responses + Format: Thought:... Action:... Action Input: ... + """ + thought = "" + action = "" + action_input = "" + + # Extract Thought + thought_match = re.search(r'Thought:\s*(.*?)(?=\nAction:|$)', response, re.DOTALL) + if thought_match: + thought = thought_match.group(1).strip() + + # Extract Action + action_match = re.search(r'Action:\s*(\w+)', response) + if action_match: + action = action_match.group(1).strip() + + # Extract Action Input + action_input_match = re.search(r'Action Input:\s*(.*?)(?=\nObservation:|$)', response, re.DOTALL) + if action_input_match: + action_input = action_input_match.group(1).strip() + # Try to parse JSON + try: + if action_input.startswith('{') or action_input.startswith('['): + action_input = json.loads(action_input) + except: + pass # Maintain the string format + + if "Final Answer:" in response and ("Action:" in response or "Observation:" in response): + + response = response.split("Final Answer:")[0] + print("Removed premature Final Answer from response") + + return thought, action, action_input + + def execute_action(self, action: str, action_input: Any, available_tools: Dict) -> str: + """Execute tool call and return observation results""" + if action in available_tools: + try: + result = available_tools[action](action_input) + return f"Action executed successfully. Result: {result}" + except Exception as e: + return f"Action execution failed: {str(e)}" + else: + return f"Unknown action: {action}. Available actions: {list(available_tools.keys())}" + + def run_react_cycle(self, + initial_prompt: str, + available_tools: Dict, + max_steps: int = 5, + temperature: float = 0.1) -> Dict[str, Any]: + """ + Run ReAct loop + + Args: + initial_prompt: Initial prompt + available_tools: Available tool function dictionary + max_steps: Maximum reasoning steps + temperature: temperature parameter + + Returns: + a dictionary containing the final result and the reasoning history + """ + self.clear_history() + self.add_to_history("user", initial_prompt) + + history = [] + final_answer = None + completed_steps = 0 + + for step in range(max_steps): + print(f"\n=== ReAct Step {step + 1}/{max_steps} ===") + completed_steps = step + 1 + + # Call LLM to obtain response + try: + response = self.client.chat.completions.create( + model=self.model_name, + messages=self.conversation_history, + temperature=temperature, + max_tokens=1024 + ) + + llm_response = response.choices[0].message.content + print(f"LLM Response: {llm_response}") + except Exception as e: + print(f"Error calling LLM: {e}") + llm_response = f"Error in LLM call: {e}" + + # Extract Thought, Action, Action Input + thought, action, action_input = self.extract_thought_action(llm_response) + + step_data = { + "step": step + 1, + "thought": thought, + "action": action, + "action_input": action_input, + "llm_response": llm_response + } + + # Check if it is the final answer + final_answer_detected = False + if "Final Answer:" in llm_response: + final_answer_match = re.search(r'Final Answer:\s*(.*?)$', llm_response, re.DOTALL) + if final_answer_match: + final_answer = final_answer_match.group(1).strip() + step_data["final_answer"] = final_answer + final_answer_detected = True + print(f"✓ Final answer detected at step {step + 1}") + + observation = "" + # Execute actions and obtain observation results + if action and not final_answer_detected: + observation = self.execute_action(action, action_input, available_tools) + step_data["observation"] = observation + + # Update conversation history + self.add_to_history("assistant", llm_response) + self.add_to_history("user", f"Observation: {observation}") + + print(f"Thought: {thought}") + print(f"Action: {action}") + print(f"Action Input: {action_input}") + print(f"Observation: {observation}") + else: + if not final_answer_detected: + # If there is no clear action, it may be during the reasoning process + self.add_to_history("assistant", llm_response) + step_data["observation"] = "No action taken - continuing reasoning" + observation = "No action taken" + else: + # If it is the final answer, no further action is required + step_data["observation"] = "Final answer provided - cycle complete" + observation = "Final answer provided" + + history.append(step_data) + + if final_answer_detected: + print(f" ReAct cycle completed at step {step + 1} with final answer") + break + + # Check if it should end early + if step >= max_steps - 1: + final_answer = f"Reached maximum steps ({max_steps}) without final answer" + print(f" Reached maximum steps without final answer") + break + + if final_answer is None: + final_answer = "No final answer produced" + + return { + "final_answer": final_answer, + "reasoning_history": history, + "success": final_answer is not None and "Reached maximum steps" not in final_answer and "No final answer" not in final_answer, + "completed_steps": completed_steps, + "max_steps": max_steps + } + + +class OptimizationWorkflow: + def __init__(self, platform: str, design: str, objective: str): + self.platform = platform + self.design = design + self.objective = objective.upper() # Convert to uppercase + + # Load configuration + self.config = self._load_config() + + # [TextGrad Integration] 1. Convert static Prompts into Optimizable State Variables + self.tool_instructions = { + 'inspect': ( + f"**Stage: Inspect**\n" + "In this stage, we analyze the data from previous optimization runs to identify patterns, trends, and insights.\n\n" + "Please analyze the data and provide insights on:\n" + "1. Key patterns in successful vs unsuccessful runs.\n" + "2. Parameter ranges that appear promising.\n" + "3. Any timing or wirelength trends.\n" + "4. Recommendations for subsequent runs.\n" + "5. We hope to further reduce the total wirelength.\n" + ), + + 'model': ( + f"**Stage: Model**\n" + "In this stage, we decide how to model the optimization problem based on the data analysis.\n\n" + "Please suggest:\n" + "1. Appropriate modeling techniques.\n" + "2. Key parameters to focus on.\n" + "3. Surrogate model recommendations.\n" + "4. Acquisition function choices.\n" + ), + + 'agglomerate': ( + f"**Stage: Agglomerate**\n" + "In this stage, we generate new parameter combinations to explore in the next optimization runs.\n\n" + "Please provide a list of new parameter sets to try, ensuring they respect the domain constraints below.\n\n" + "Each parameter set should be a dictionary with parameter names and their suggested values.\n" + "**Important:** Make sure all parameter sets satisfy the domain constraints before suggesting them.\n" + ) + } + + # Find the design configuration + configurations = self.config.get('configurations', []) + for config in configurations: + if ( + config['platform'].lower() == self.platform.lower() + and config['design'].lower() == self.design.lower() + and config['goal'].upper() == self.objective + ): + self.design_config = config + break + else: + raise ValueError( + f"No configuration found for platform={self.platform}, design={self.design}, objective={self.objective}" + ) + + # Define initial clock periods for each design and platform + initial_clock_periods = { + ('asap7', 'aes'): 400, # in picoseconds + ('asap7', 'ibex'): 1260, # in picoseconds + ('asap7', 'jpeg'): 1100, # in picoseconds + ('sky130hd', 'aes'): 4.5, # in nanoseconds + ('sky130hd', 'ibex'): 10.0,# in nanoseconds + ('sky130hd', 'jpeg'): 8.0, # in nanoseconds + } + + # Get the initial clock period for the current platform and design + key = (self.platform.lower(), self.design.lower()) + if key in initial_clock_periods: + self.initial_clk_period = initial_clock_periods[key] + else: + raise ValueError(f"Initial clock period not defined for platform={self.platform}, design={self.design}") + + # Calculate clock period range + min_clk = self.initial_clk_period * 0.7 + max_clk = self.initial_clk_period * 1.3 + + # Define parameter names in the expected order + self.parameter_names = [ + 'core_util', + 'cell_pad_global', + 'cell_pad_detail', + 'synth_flatten', + 'pin_layer', + 'above_layer', + 'tns', + 'lb_addon', + 'cts_size', + 'cts_diameter', + 'enable_dpo', + 'clk_period' + ] + + # Set all parameter constraints including clock period range + self.param_constraints = { + 'core_util': {'type': 'int', 'range': [20, 99]}, + 'cell_pad_global': {'type': 'int', 'range': [0, 4]}, + 'cell_pad_detail': {'type': 'int', 'range': [0, 4]}, + 'synth_flatten': {'type': 'int', 'range': [0, 1]}, + 'pin_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'above_layer': {'type': 'float', 'range': [0.2, 0.7]}, + 'tns': {'type': 'int', 'range': [70, 100]}, + 'lb_addon': {'type': 'float', 'range': [0.00, 0.99]}, + 'cts_size': {'type': 'int', 'range': [10, 40]}, + 'cts_diameter': {'type': 'int', 'range': [80, 120]}, + 'enable_dpo': {'type': 'int', 'range': [0, 1]}, + 'clk_period': {'type': 'float', 'range': [min_clk, max_clk]} + } + + # Load initial parameters and SDC context + self.initial_params = self._load_initial_params() + self.sdc_context = self._load_sdc_context() + + emb_np, docs, docsDict = load_embeddings_and_docs() + self.rag_embeddings = torch.tensor(emb_np).cpu() + self.rag_docs = docs + self.rag_docsDict = docsDict + print("[INFO] Loading embedding model...") + model_path = Path(__file__).parent / "models" / "mxbai-embed-large-v1" + model_path = model_path.resolve() + # self.rag_model = SentenceTransformer(str(model_path)) + self.rag_model = SentenceTransformer(str(model_path), device='cpu') + + self.react_framework = ReActFramework( + client=OpenAI( + base_url="https://ai.gitee.com/v1", + # api_key="X7NJOWYHJX7A1BDACXRLWC1ZMCUWM4FX0Q6FHJ1Q", + api_key="MZ1RSHGF7QPGC8HHBOSPBQTDAZ6QD9NBCHROSZ1B", + ), + model_name="DeepSeek-R1" + ) + # Secondary supervisor model for dual-LLM flow. All values can be overridden via env variables. + self.supervisor_client = OpenAI( + base_url=os.environ.get("SUPERVISOR_BASE_URL", "https://ai.gitee.com/v1"), + api_key=os.environ.get("SUPERVISOR_API_KEY", "MZ1RSHGF7QPGC8HHBOSPBQTDAZ6QD9NBCHROSZ1B"), + ) + self.supervisor_model_name = os.environ.get("SUPERVISOR_MODEL", "DeepSeek-R1") + self.supervision_feedback: str = "" + + def _optimize_prompt_with_textgrad(self, stage: str, feedback: str): + """ + [TextGrad Integration] Core function: Optimize Prompt(Variable) based on feedback (Gradient). + """ + print(f"\n[TextGrad] Optimizing '{stage}' instructions based on feedback...") + + current_instruction = self.tool_instructions.get(stage, "") + + # This is a meta-prompt used to make LLM act as an "optimizer". + optimizer_prompt = f""" + You are a Prompt Optimizer for an EDA Logic Synthesis Agent. + + **Current System Instruction**: + {current_instruction} + + **Critique/Gradient (Feedback from Supervisor)**: + {feedback} + + **Task**: + Rewrite the "Current System Instruction" to explicitly address the Critique. + - If the critic says the agent ignored errors, strengthen the error-handling instructions. + - If the critic says the agent explored too little, emphasize exploration in the instructions. + - Keep the format consistent, but change the content to be more effective. + + Return ONLY the new instruction text. + """ + + try: + response = self.supervisor_client.chat.completions.create( + model=self.supervisor_model_name, + messages=[{"role": "user", "content": optimizer_prompt}], + temperature=0.2 + ) + new_instruction = response.choices[0].message.content.strip() + + # Variable Update + self.tool_instructions[stage] = new_instruction + print(f"[TextGrad] Successfully updated instructions for stage '{stage}'.") + + except Exception as e: + print(f"[TextGrad] Failed to optimize prompt: {e}") + + def _create_react_tools(self, stage: str, data: Dict[str, Any]) -> Dict: + """Create available utility functions for different stages""" + + base_tools = { + "analyze_data_distribution": lambda x: self._call_existing_distribution_analysis(data), + "analyze_data_structure": lambda x: self._call_existing_structure_analysis(data), + "evaluate_parameter_ranges": lambda x: self._evaluate_parameter_ranges(data), + "check_constraints": lambda x: self._check_constraints_compliance(data), + "suggest_improvements": lambda x: self._suggest_improvements(stage, data), + } + + if stage == 'inspect': + inspection_tools = { + "configure_inspection": lambda config: self._configure_inspection_with_existing(config, data), + "analyze_correlations": lambda params: self._analyze_correlations_with_existing(params, data), + "cluster_analysis": lambda config: self._cluster_analysis_with_existing(config, data), + "manifold_analysis": lambda config: self._manifold_analysis_with_existing(config, data), + "local_structure_analysis": lambda config: self._local_structure_analysis_with_existing(config, data), + } + base_tools.update(inspection_tools) + + elif stage == 'model': + modeling_tools = { + "configure_model": lambda config: self._configure_model_with_existing(config, data), + "evaluate_surrogate": lambda params: self._evaluate_surrogate_with_existing(params, data), + "select_acquisition": lambda method: self._select_acquisition_with_existing(method, data), + "create_surrogate_model": lambda config: self._create_surrogate_model_with_existing(config, data), + "evaluate_timing_model": lambda x: self._evaluate_timing_model_with_existing(data), + "evaluate_wirelength_model": lambda x: self._evaluate_wirelength_model_with_existing(data), + "get_model_recommendations": lambda x: self._get_model_recommendations_from_existing(data), + } + base_tools.update(modeling_tools) + + elif stage == 'agglomerate': + selection_tools = { + "configure_selection": lambda config: self._configure_selection_with_existing(config, data), + "generate_parameters": lambda count: self._generate_parameters_with_existing(count, data), + "validate_parameters": lambda params: self._validate_parameters_tool(params), + "latin_hypercube_sampling": lambda config: self._latin_hypercube_sampling_with_existing(config, data), + "create_quality_scores": lambda config: self._create_quality_scores_with_existing(config, data), + "select_points": lambda config: self._select_points_with_existing(config, data), + "compare_selection_methods": lambda config: self._compare_selection_methods_with_existing(config, data), + "kmeans_selection": lambda config: self._kmeans_selection_with_existing(config, data), + "hybrid_selection": lambda config: self._hybrid_selection_with_existing(config, data), + "entropy_selection": lambda config: self._entropy_selection_with_existing(config, data), + "graph_selection": lambda config: self._graph_selection_with_existing(config, data), + } + base_tools.update(selection_tools) + + return base_tools + + + def _call_existing_distribution_analysis(self, data: Dict) -> str: + """Call existing data distribution analysis functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + result = inspect_data_distribution(X, Y) + return self._format_analysis_result("Data Distribution Analysis", result) + else: + return "Insufficient data for distribution analysis" + + except Exception as e: + return f"Error in distribution analysis: {str(e)}" + + def _call_existing_structure_analysis(self, data: Dict) -> str: + """Call existing data structure analysis functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Use default configuration or retrieve configuration from data + config = { + "n_clusters": 5, + "correlation_threshold": 0.5, + "n_neighbors": 20, + "perplexity": 30 + } + + result = inspect_data_structure(X, Y, config) + return self._format_analysis_result("Data Structure Analysis", result) + else: + return "Insufficient data for structure analysis" + + except Exception as e: + return f"Error in structure analysis: {str(e)}" + + def _evaluate_parameter_ranges(self, data: Dict) -> str: + """Evaluation Parameter Range Tool - Implementation""" + constraints_info = "Parameter Constraints Evaluation:\n" + + # Analyze the current usage of parameters + param_usage = {} + for run in data.get('log_data', {}).get('runs', []): + if run.get('parameters'): + for param, value in run['parameters'].items(): + if param not in param_usage: + param_usage[param] = [] + param_usage[param].append(float(value)) + + for param, info in self.param_constraints.items(): + min_val, max_val = info['range'] + param_type = info['type'] + + constraints_info += f"\n- {param} ({param_type}): range [{min_val}, {max_val}]" + + if param in param_usage: + values = param_usage[param] + used_min = min(values) + used_max = max(values) + constraints_info += f"\n Currently used: [{used_min:.2f}, {used_max:.2f}]" + + # Check if the parameter space has been fully explored + range_used = (used_max - used_min) / (max_val - min_val) + if range_used < 0.5: + constraints_info += f" (Only {range_used*100:.1f}% of range explored)" + + return constraints_info + + def _check_constraints_compliance(self, data: Dict) -> str: + """Check Constraint Compliance Tool - Implementation""" + violations = [] + constraint_checks = [] + + for run in data.get('log_data', {}).get('runs', []): + if run.get('success') and run.get('parameters'): + params = run['parameters'] + + # Check the basic scope constraints + for param, value in params.items(): + if param in self.param_constraints: + constraint = self.param_constraints[param] + min_val, max_val = constraint['range'] + if value < min_val or value > max_val: + violations.append(f"{param}={value} not in [{min_val}, {max_val}]") + + # Check domain constraints + if not self._validate_domain_constraints(params): + violations.append(f"Domain constraints violated for run with params: {params}") + + if violations: + constraint_checks.append(f"Constraint violations found in {len(violations)} cases:") + constraint_checks.extend(violations[:5]) # Only display the first 5 + else: + constraint_checks.append("All parameters comply with constraints") + + # Check the effectiveness of parameter combinations + successful_count = sum(1 for run in data.get('log_data', {}).get('runs', []) + if run.get('success') and run.get('parameters')) + total_with_params = sum(1 for run in data.get('log_data', {}).get('runs', []) + if run.get('parameters')) + + if total_with_params > 0: + success_rate = successful_count / total_with_params * 100 + constraint_checks.append(f"\nParameter success rate: {success_rate:.1f}%") + + return "\n".join(constraint_checks) + + def _suggest_improvements(self, stage: str, data: Dict) -> str: + """Provide improvement suggestions based on stages - implementation""" + suggestions = [] + + if stage == 'inspect': + successful_runs = data.get('log_data', {}).get('summary', {}).get('successful_runs', 0) + total_runs = data.get('log_data', {}).get('summary', {}).get('total_runs', 0) + + suggestions.append(f"Inspection Suggestions for {successful_runs}/{total_runs} successful runs:") + + if successful_runs < total_runs * 0.3: + suggestions.append("- Focus on identifying why runs are failing") + suggestions.append("- Check for common parameter ranges in failed runs") + else: + suggestions.append("- Analyze correlations between parameters and objectives") + suggestions.append("- Identify optimal parameter ranges from successful runs") + + elif stage == 'model': + suggestions.append("Modeling Suggestions:") + suggestions.append("- Use surrogate models for early prediction of results") + suggestions.append("- Balance exploration (trying new regions) and exploitation (refining good regions)") + + # Suggest modeling methods based on data volume + successful_runs = data.get('log_data', {}).get('summary', {}).get('successful_runs', 0) + if successful_runs < 10: + suggestions.append("- With limited data, use simpler models and focus on exploration") + else: + suggestions.append("- With sufficient data, use more complex models and balance exploration/exploitation") + + elif stage == 'agglomerate': + suggestions.append("Parameter Generation Suggestions:") + suggestions.append("- Generate diverse parameter sets to explore different regions") + suggestions.append("- Focus on promising parameter ranges identified in previous stages") + suggestions.append("- Ensure all generated parameters satisfy domain constraints") + + # Suggest strategies based on goals + if self.objective == 'ECP': + suggestions.append("- For ECP, prioritize timing-critical parameters like clk_period and cell padding") + elif self.objective == 'DWL': + suggestions.append("- For DWL, focus on placement and routing parameters") + + return "\n".join(suggestions) + + def _extract_XY_from_data(self, data: Dict) -> Tuple[Optional[np.ndarray], Optional[np.ndarray]]: + """Extracting X and Y arrays from data - Reusing logic in analyze_stetrics""" + feature_vectors = [] + objective_values = [] + + for run in data.get('log_data', {}).get('runs', []): + if run.get('success') and 'metrics' in run: + obj_values = self._calculate_objective(run) + + if obj_values['value'] is not None or obj_values['surrogate'] is not None: + # Extract parameter values as features + params = [] + for param in self.parameter_names: + params.append(float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0)))) + feature_vectors.append(params) + + # Use real values, if not available, use proxy values + objective_values.append(obj_values['value'] if obj_values['value'] is not None else obj_values['surrogate']) + + if feature_vectors and objective_values: + return np.array(feature_vectors), np.array(objective_values) + else: + return None, None + + def _format_analysis_result(self, title: str, result: Dict) -> str: + """Format the analysis result as a readable string""" + formatted = f"=== {title} ===\n" + + for key, value in result.items(): + if key == "model_recommendations": + formatted += "\n--- Model Recommendations ---\n" + for rec_key, rec_value in value.items(): + formatted += f"{rec_key}: {rec_value}\n" + elif isinstance(value, (int, float)): + formatted += f"{key}: {value:.4f}\n" + elif isinstance(value, list) and len(value) > 0 and isinstance(value[0], (int, float)): + # Format numerical list + formatted += f"{key}: [{', '.join(f'{v:.4f}' for v in value[:5])}{'...' if len(value) > 5 else ''}]\n" + else: + formatted += f"{key}: {value}\n" + + return formatted + + def _configure_inspection_with_existing(self, config: Dict, data: Dict) -> str: + """Use existing function configuration to check parameters""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Using configuration to run structural analysis + result = inspect_data_structure(X, Y, config) + + response = f"Inspection configured with: {config}\n" + response += "Key findings:\n" + + # Extract key findings + if "linearity_score" in result: + response += f"- Linearity: {result['linearity_score']:.3f}\n" + if "is_nonlinear" in result: + response += f"- Nonlinear: {result['is_nonlinear']}\n" + if "needs_local_models" in result: + response += f"- Needs local models: {result['needs_local_models']}\n" + if "cluster_sizes" in result: + response += f"- Cluster sizes: {result['cluster_sizes']}\n" + + return response + else: + return "No data available for inspection configuration" + + except Exception as e: + return f"Error in inspection configuration: {str(e)}" + + def _analyze_correlations_with_existing(self, params: Dict, data: Dict) -> str: + """Analyze correlation using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Perform structural analysis to obtain relevant information + config = {"correlation_threshold": params.get('threshold', 0.5)} + result = inspect_data_structure(X, Y, config) + + response = "Feature Correlations Analysis:\n" + + if "feature_importance" in result: + response += "Feature importance (correlation with objective):\n" + for i, importance in enumerate(result["feature_importance"]): + response += f"- {self.parameter_names[i]}: {importance:.3f}\n" + + if "has_correlated_features" in result: + response += f"Has highly correlated features: {result['has_correlated_features']}\n" + if "high_correlation_pairs" in result: + response += f"High correlation pairs: {result['high_correlation_pairs']}\n" + + return response + else: + return "No data available for correlation analysis" + + except Exception as e: + return f"Error in correlation analysis: {str(e)}" + + def _cluster_analysis_with_existing(self, config: Dict, data: Dict) -> str: + """Cluster analysis using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Perform structural analysis to obtain clustering information + result = inspect_data_structure(X, Y, config) + + response = "Cluster Analysis:\n" + + if "cluster_sizes" in result: + response += f"Cluster sizes: {result['cluster_sizes']}\n" + if "cluster_balance" in result: + response += f"Cluster balance: {result['cluster_balance']:.3f}\n" + if "cluster_y_means" in result: + response += "Cluster objective means:\n" + for i, mean in enumerate(result["cluster_y_means"]): + response += f"- Cluster {i}: {mean:.4f}\n" + if "needs_local_models" in result: + response += f"Recommend local models: {result['needs_local_models']}\n" + + return response + else: + return "No data available for cluster analysis" + + except Exception as e: + return f"Error in cluster analysis: {str(e)}" + + def _manifold_analysis_with_existing(self, config: Dict, data: Dict) -> str: + """Perform manifold analysis using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None: + result = analyze_manifold_structure(X, config) + return self._format_analysis_result("Manifold Structure Analysis", result) + else: + return "No data available for manifold analysis" + + except Exception as e: + return f"Error in manifold analysis: {str(e)}" + + def _local_structure_analysis_with_existing(self, config: Dict, data: Dict) -> str: + """Using existing functions for local structure analysis""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None: + result = analyze_local_structure(X, config) + return self._format_analysis_result("Local Structure Analysis", result) + else: + return "No data available for local structure analysis" + + except Exception as e: + return f"Error in local structure analysis: {str(e)}" + + def _get_model_recommendations_from_existing(self, data: Dict) -> str: + """Obtain model recommendations from existing analysis""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + result = inspect_data_structure(X, Y) + + if "model_recommendations" in result: + recommendations = result["model_recommendations"] + response = "Model Recommendations from Data Analysis:\n" + + for key, value in recommendations.items(): + if key == "feature_weights" and isinstance(value, list): + response += f"{key}: [" + response += ", ".join(f"{w:.3f}" for w in value[:5]) + if len(value) > 5: + response += ", ..." + response += "]\n" + else: + response += f"{key}: {value}\n" + + return response + else: + return "No model recommendations available" + else: + return "No data available for model recommendations" + + except Exception as e: + return f"Error getting model recommendations: {str(e)}" + + + def _configure_model_with_existing(self, config: Dict, data: Dict) -> str: + """Configure the model using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Create a model using configuration + kernel_type = config.get('kernel_type', 'matern') + preprocessing = config.get('preprocessing', 'standard') + acquisition = config.get('acquisition', 'ei') + + # Create Preprocessor + preprocessor = create_preprocessor(preprocessing) + + # Create acquisition function + acq_function = create_acquisition_function(acquisition) + + response = f"Model configured successfully:\n" + response += f"- Kernel type: {kernel_type}\n" + response += f"- Preprocessing: {preprocessing}\n" + response += f"- Acquisition function: {acquisition}\n" + response += f"- Data shape: {X.shape}\n" + + # If the amount of data is sufficient, a model can be created for testing + if len(X) >= 2: + model = create_model(X, Y, kernel_type=kernel_type) + response += f"- Model created successfully with {len(X)} samples\n" + else: + response += f"- Insufficient data for model creation (need at least 2 samples, have {len(X)})\n" + + return response + else: + return "No data available for model configuration" + + except Exception as e: + return f"Error in model configuration: {str(e)}" + + def _evaluate_surrogate_with_existing(self, params: Dict, data: Dict) -> str: + """Evaluate the proxy model using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Extract proxy values (if any) + surrogate_values = None + if 'surrogates' in data.get('metrics', {}): + surrogate_values = np.array(data['metrics']['surrogates']) + + # Use existing functions to process proxy data + if surrogate_values is not None: + X_processed, y_combined, uncertainty = handle_surrogate_data(X, Y, surrogate_values) + + response = "Surrogate Model Evaluation:\n" + response += f"- Original data points: {len(Y)}\n" + response += f"- Valid target values: {np.sum(~np.isnan(Y))}\n" + response += f"- Surrogate values used: {np.sum(np.isnan(Y))}\n" + response += f"- Combined data points: {len(y_combined)}\n" + + if len(uncertainty) > 0: + response += f"- Average surrogate uncertainty: {np.mean(uncertainty):.4f}\n" + + return response + else: + return "No surrogate data available for evaluation" + else: + return "No data available for surrogate evaluation" + + except Exception as e: + return f"Error in surrogate evaluation: {str(e)}" + + def _select_acquisition_with_existing(self, method: str, data: Dict) -> str: + """Use existing functions to select collection functions""" + try: + # Create a collection function using an existing function + acq_function = create_acquisition_function(method) + + response = f"Acquisition function selected: {method.upper()}\n" + + # Provide explanations for different collection functions + explanations = { + 'ei': "Expected Improvement - balances improvement probability and magnitude", + 'ucb': "Upper Confidence Bound - favors exploration of uncertain regions", + 'pi': "Probability of Improvement - focuses on areas likely to improve", + 'augmented_ei': "Augmented EI - combines EI with exploration bonus" + } + + response += f"Explanation: {explanations.get(method, 'No explanation available')}\n" + + # Provide recommendations based on data characteristics + X, Y = self._extract_XY_from_data(data) + if X is not None and Y is not None: + if len(Y) < 10: + response += "Recommendation: With limited data, consider using UCB for better exploration\n" + else: + response += "Recommendation: With sufficient data, EI or Augmented EI are good choices\n" + + return response + + except Exception as e: + return f"Error in acquisition function selection: {str(e)}" + + def _create_surrogate_model_with_existing(self, config: Dict, data: Dict) -> str: + """Create a proxy model using existing functions""" + try: + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + kernel_type = config.get('kernel_type', 'matern') + noise_level = config.get('noise_level', 1e-6) + + # Create a model using existing functions + model = create_model(X, Y, noise_level=noise_level, kernel_type=kernel_type) + + response = f"Surrogate Model Created:\n" + response += f"- Kernel: {kernel_type}\n" + response += f"- Data points: {len(X)}\n" + response += f"- Features: {X.shape[1]}\n" + response += f"- Kernel parameters: {model.kernel_}\n" + + # Test model prediction + if len(X) > 0: + predictions, stds = predict_with_model(model, X[:1]) # Test a point + response += f"- Test prediction successful\n" + response += f"- Prediction range: [{predictions[0]:.4f} ± {stds[0]:.4f}]\n" + + return response + else: + return "No data available for model creation" + + except Exception as e: + return f"Error in surrogate model creation: {str(e)}" + + def _evaluate_timing_model_with_existing(self, data: Dict) -> str: + """Evaluate timing models using existing functions""" + try: + # Build context + context = { + 'log_data': data.get('log_data', {}), + 'metrics': data.get('metrics', {}), + 'model_recommendations': data.get('model_recommendations', {}) + } + + # Evaluate timing models using existing functions + results = evaluate_timing_model(context) + + response = "Timing Model Evaluation:\n" + + if 'performance' in results: + for key, value in results['performance'].items(): + response += f"- {key}: {value:.4f}\n" + + if 'suggestions' in results: + response += "\nSuggestions:\n" + for suggestion in results['suggestions']: + response += f"- {suggestion}\n" + + if 'recommendations' in results: + response += "\nRecommendations:\n" + for key, value in results['recommendations'].items(): + response += f"- {key}: {value}\n" + + return response + + except Exception as e: + return f"Error in timing model evaluation: {str(e)}" + + def _evaluate_wirelength_model_with_existing(self, data: Dict) -> str: + """Evaluate the wire length model using existing functions""" + try: + # Build context + context = { + 'log_data': data.get('log_data', {}), + 'metrics': data.get('metrics', {}), + 'model_recommendations': data.get('model_recommendations', {}) + } + + # Evaluate the wire length model using existing functions + results = evaluate_wirelength_model(context) + + response = "Wirelength Model Evaluation:\n" + + if 'performance' in results: + for key, value in results['performance'].items(): + response += f"- {key}: {value:.4f}\n" + + if 'suggestions' in results: + response += "\nSuggestions:\n" + for suggestion in results['suggestions']: + response += f"- {suggestion}\n" + + if 'recommendations' in results: + response += "\nRecommendations:\n" + for key, value in results['recommendations'].items(): + response += f"- {key}: {value}\n" + + return response + + except Exception as e: + return f"Error in wirelength model evaluation: {str(e)}" + + def _generate_parameters_with_existing(self, count: int, data: Dict) -> str: + """Generate parameters using existing functions""" + try: + if count <= 0 or count > 50: + return "Error: count must be between 1 and 50" + + # Obtain parameter dimensions + n_dims = len(self.parameter_names) + + # Use existing Latin hypercube sampling + samples = latin_hypercube(count, n_dims) + + response = f"Parameter Generation using Latin Hypercube:\n" + response += f"- Samples generated: {count}\n" + response += f"- Parameter dimensions: {n_dims}\n" + response += f"- Sampling method: Latin Hypercube\n" + + # Display parameter range information + response += "\nParameter Ranges:\n" + for i, param in enumerate(self.parameter_names): + constraint = self.param_constraints[param] + min_val, max_val = constraint['range'] + response += f"- {param}: [{min_val}, {max_val}] ({constraint['type']})\n" + + return response + + except Exception as e: + return f"Error in parameter generation: {str(e)}" + + def _latin_hypercube_sampling_with_existing(self, config: Dict, data: Dict) -> str: + """Using existing functions for Latin hypercube sampling""" + try: + n_points = config.get('n_points', 10) + n_dims = len(self.parameter_names) + + # Use the existing Latin hypercube sampling function + samples = latin_hypercube(n_points, n_dims) + + response = f"Latin Hypercube Sampling:\n" + response += f"- Points: {n_points}\n" + response += f"- Dimensions: {n_dims}\n" + response += f"- Sample shape: {samples.shape}\n" + + # Display sampling statistics + response += f"- Sample range: [{samples.min():.3f}, {samples.max():.3f}]\n" + response += f"- Sample mean: {samples.mean():.3f}\n" + response += f"- Sample std: {samples.std():.3f}\n" + + return response + + except Exception as e: + return f"Error in Latin hypercube sampling: {str(e)}" + + def _configure_selection_with_existing(self, config: Dict, data: Dict) -> str: + """Configure selection strategy using existing functions""" + try: + method = config.get('method', 'hybrid') + quality_weight = config.get('quality_weight', 0.7) + uncertainty_bonus = config.get('uncertainty_bonus', 0.2) + n_points = config.get('n_points', 10) + + response = f"Selection Strategy Configured:\n" + response += f"- Method: {method}\n" + response += f"- Quality weight: {quality_weight}\n" + response += f"- Uncertainty bonus: {uncertainty_bonus}\n" + response += f"- Points to select: {n_points}\n" + + # Provide explanations for different methods + method_descriptions = { + "kmeans": "K-means clustering - selects best point from each cluster", + "hybrid": "Hybrid approach - balances quality and diversity", + "entropy": "Entropy-based - maximizes information diversity", + "graph": "Graph-based - uses network centrality measures" + } + + response += f"Method description: {method_descriptions.get(method, 'No description')}\n" + + return response + + except Exception as e: + return f"Error in selection configuration: {str(e)}" + + + def _create_quality_scores_with_existing(self, config: Dict, data: Dict) -> str: + """Create a quality score using an existing function""" + try: + # Extract necessary information from data + X, Y = self._extract_XY_from_data(data) + + if X is not None and Y is not None: + # Simulation model predictions and uncertainties (in practical use, these should come from real models) + model_predictions = Y # Using real values as a proxy for prediction + model_uncertainties = np.ones_like(Y) * 0.1 # Simulate uncertainty + + # Create a quality score using an existing function + quality_scores = create_quality_scores(X, Y, model_predictions, model_uncertainties) + + response = "Quality Scores Created:\n" + response += f"- Data points: {len(X)}\n" + response += f"- Quality score range: [{quality_scores.min():.4f}, {quality_scores.max():.4f}]\n" + response += f"- Quality score mean: {quality_scores.mean():.4f}\n" + response += f"- Quality score std: {quality_scores.std():.4f}\n" + + response += f"- First 5 quality scores: {quality_scores[:5].tolist()}\n" + + if 'selection_data' not in data: + data['selection_data'] = {} + data['selection_data']['quality_scores'] = quality_scores + data['selection_data']['X'] = X + data['selection_data']['Y'] = Y + + return response + else: + return "No data available for quality score creation" + + except Exception as e: + return f"Error in quality score creation: {str(e)}" + + def _select_points_with_existing(self, config: Dict, data: Dict) -> str: + """_select_points_with_existing""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + method = config.get('method', 'hybrid') + n_points = config.get('n_points', 10) + quality_weight = config.get('quality_weight', 0.7) + + selection_config = { + "quality_weight": quality_weight, + "uncertainty_bonus": config.get('uncertainty_bonus', 0.2) + } + + selected_indices = select_points( + X, quality_scores, + method=method, + n_points=n_points, + config=selection_config + ) + + response = f"Points Selected using {method.upper()} method:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Selected quality scores: {selected_qualities.tolist()}\n" + response += f"- Average quality of selected: {selected_qualities.mean():.4f}\n" + + # store selection data + data['selection_data']['selected_indices'] = selected_indices + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in point selection: {str(e)}" + + def _compare_selection_methods_with_existing(self, config: Dict, data: Dict) -> str: + """compare selection methods with existing(""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 5) + methods = ['kmeans', 'hybrid', 'entropy', 'graph'] + + response = "Selection Method Comparison:\n" + response += f"- Comparing {len(methods)} methods\n" + response += f"- Points to select: {n_points}\n\n" + + for method in methods: + try: + selected_indices = select_points( + X, quality_scores, + method=method, + n_points=n_points + ) + + selected_qualities = quality_scores[selected_indices] + + response += f"**{method.upper()}**:\n" + response += f" - Selected indices: {selected_indices.tolist()}\n" + response += f" - Avg quality: {selected_qualities.mean():.4f}\n" + response += f" - Quality range: [{selected_qualities.min():.4f}, {selected_qualities.max():.4f}]\n" + + except Exception as e: + response += f"**{method.upper()}**: Error - {str(e)}\n" + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in method comparison: {str(e)}" + + def _kmeans_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using K-means selection method""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + + # using K-means selecting function + selected_indices = kmeans_select(X, quality_scores, n_points) + + response = "K-means Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + response += f"- Quality diversity: {selected_qualities.std():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'kmeans' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in K-means selection: {str(e)}" + + def _hybrid_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using existing hybrid selection method""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + quality_weight = config.get('quality_weight', 0.7) + + distance_matrix = cdist(X, X) + + # using hybrid_select function + selected_indices = hybrid_select( + X, quality_scores, distance_matrix, + n_points, quality_weight + ) + + response = "Hybrid Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Quality weight: {quality_weight}\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + + selected_points = X[selected_indices] + min_distances = np.min(cdist(selected_points, selected_points) + np.eye(len(selected_points)) * 1e6, axis=1) + response += f"- Minimum inter-point distance: {min_distances.mean():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'hybrid' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in hybrid selection: {str(e)}" + + def _entropy_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using existing entropy selecting methods""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + + # using entropy selecting function + selected_indices = entropy_select(X, quality_scores, n_points) + + response = "Entropy-based Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'entropy' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in entropy selection: {str(e)}" + + def _graph_selection_with_existing(self, config: Dict, data: Dict) -> str: + """using existing graph selection method""" + try: + selection_data = data.get('selection_data', {}) + quality_scores = selection_data.get('quality_scores') + X = selection_data.get('X') + + if X is not None and quality_scores is not None: + n_points = config.get('n_points', 10) + + # using graph selecting function + selected_indices = graph_select(X, quality_scores, n_points) + + response = "Graph-based Selection Results:\n" + response += f"- Selected {len(selected_indices)} points\n" + response += f"- Selected indices: {selected_indices.tolist()}\n" + + selected_qualities = quality_scores[selected_indices] + response += f"- Average quality: {selected_qualities.mean():.4f}\n" + + # store results + data['selection_data']['selected_indices'] = selected_indices + data['selection_data']['method_used'] = 'graph' + + return response + else: + return "No quality scores available. Please run 'create_quality_scores' first." + + except Exception as e: + return f"Error in graph selection: {str(e)}" + + + def _validate_parameters_tool(self, params: Dict) -> str: + validation_results = [] + + for param_name, value in params.items(): + if param_name in self.param_constraints: + constraint = self.param_constraints[param_name] + min_val, max_val = constraint['range'] + param_type = constraint['type'] + + if value < min_val or value > max_val: + validation_results.append(f" {param_name}={value} outside range [{min_val}, {max_val}]") + else: + validation_results.append(f" {param_name}={value} within valid range") + + if self._validate_domain_constraints(params): + validation_results.append("Domain constraints satisfied") + else: + validation_results.append("Domain constraints violated") + + return "Parameter Validation:\n" + "\n".join(validation_results) + + + def _load_config(self) -> Dict[str, Any]: + """Load the configuration from 'opt_config.json'.""" + with open('opt_config.json', 'r') as f: + config = json.load(f) + return config + + def _load_initial_params(self) -> Dict[str, Any]: + """Load initial parameters from the design's config.mk file""" + config_path = f"designs/{self.platform}/{self.design}/config.mk" + params = {} + with open(config_path, 'r') as f: + for line in f: + if line.startswith('export'): + parts = line.strip().split('=', 1) + if len(parts) == 2: + key = parts[0].replace('export', '').strip() + value = parts[1].strip() + params[key] = value + return params + + def _load_sdc_context(self) -> Dict[str, Any]: + """Load SDC context including special case for JPEG""" + sdc_context = {} + + # Determine SDC filename based on platform/design + if self.platform.lower() == 'asap7' and self.design.lower() == 'jpeg': + sdc_file = 'jpeg_encoder15_7nm.sdc' + else: + sdc_file = 'constraint.sdc' + + sdc_path = f"designs/{self.platform}/{self.design}/{sdc_file}" + + # Read SDC file + try: + with open(sdc_path, 'r') as f: + sdc_content = f.read() + + # Extract clock period + clock_period_match = re.search(r'set clk_period\s+([\d.]+)', sdc_content) + if clock_period_match: + sdc_context['clock_period'] = float(clock_period_match.group(1)) + + # Store full content for context + sdc_context['content'] = sdc_content + sdc_context['filename'] = sdc_file + + except Exception as e: + print(f"Warning: Could not load SDC file {sdc_path}: {str(e)}") + sdc_context['error'] = str(e) + + return sdc_context + + + def _generate_llm_prompt(self, stage: str, data: Dict[str, Any]) -> str: + + constraints_text = "Parameter Constraints:\n" + for param, info in self.param_constraints.items(): + param_type = info['type'] + param_range = info['range'] + constraints_text += f"- {param} ({param_type}, range: {param_range})\n" + + # tool_instructions = { + # 'inspect': ( + # f"**Stage: Inspect**\n" + # "In this stage, we analyze the data from previous optimization runs to identify patterns, trends, and insights.\n\n" + # f"Data to analyze:\n{json.dumps(data, indent=2, default=str)}\n\n" + # "Please analyze the data and provide insights on:\n" + # "1. Key patterns in successful vs unsuccessful runs.\n" + # "2. Parameter ranges that appear promising.\n" + # "3. Any timing or wirelength trends.\n" + # "4. Recommendations for subsequent runs.\n" + # "5. We hope to further reduce the total wirelength.\n" + # ), + + # 'model': ( + # f"**Stage: Model**\n" + # "In this stage, we decide how to model the optimization problem based on the data analysis.\n\n" + # f"Data for modeling:\n{json.dumps(data, indent=2, default=str)}\n\n" + # "Please suggest:\n" + # "1. Appropriate modeling techniques.\n" + # "2. Key parameters to focus on.\n" + # "3. Surrogate model recommendations.\n" + # "4. Acquisition function choices.\n" + # ), + + # 'agglomerate': ( + # f"**Stage: Agglomerate**\n" + # "In this stage, we generate new parameter combinations to explore in the next optimization runs.\n\n" + # "Please provide a list of new parameter sets to try, ensuring they respect the domain constraints below.\n\n" + # f"{constraints_text}\n" + # "Each parameter set should be a dictionary with parameter names and their suggested values.\n" + # "**Important:** Make sure all parameter sets satisfy the domain constraints before suggesting them.\n" + # ) + # } + + data_context = "" + if stage == 'inspect': + data_context = f"\nData to analyze:\n{json.dumps(data, indent=2, default=str)}\n" + elif stage == 'model': + data_context = f"\nData for modeling:\n{json.dumps(data, indent=2, default=str)}\n" + elif stage == 'agglomerate': + data_context = f"\nDomain Constraints to respect:\n{constraints_text}\n" + + stage_contexts = { + 'inspect': ( + f"metrics analyze: Total runs={data.get('log_data', {}).get('summary', {}).get('total_runs', 0)}, " + f"successful runs ={data.get('log_data', {}).get('summary', {}).get('successful_runs', 0)}" + ), + 'model': "Configure modeling methods based on inspection results", + 'agglomerate': "Configure parameter selection strategy based on modeling results" + } + + prompt = f"""**stages:{stage.upper()}** + {self.tool_instructions.get(stage, '')} + + {data_context} + + {stage_contexts.get(stage, '')} + + **Important: Use only tool calls and do not generate text replies!** + """ + + # ========= Splicing RAG ========= + rag_context = "" + if self.rag_model is not None and self.rag_embeddings is not None: + try: + print("[DEBUG] RAG: Starting retrieval...") + + # Step 1: Extract error information + error_summary = "" + if "log_data" in data: + all_errors = [] + for run in data["log_data"].get("runs", []): + if run.get("errors"): + all_errors.extend(run["errors"]) + if all_errors: + # Retrieve the most recent or frequent errors + top_errors = all_errors[-3:] # Last 3 posts + error_summary = "\n".join(top_errors) + print(f"[DEBUG] Detected {len(all_errors)} error messages. Sample:\n{error_summary}") + + # Step 2: Construct RAG query + if error_summary: + query = ( + f"Stage: {stage}. Objective: {self.objective}. " + f"The recent optimization runs failed with errors:\n{error_summary}\n\n" + "Retrieve relevant OpenROAD documentation, known failure modes, and " + "potential parameter tuning suggestions that may fix these issues." + ) + else: + query = ( + f"Stage: {stage}. Objective: {self.objective}. " + f"Focus on analyzing {stage}-related optimization results. " + f"Important metrics include wirelength, timing, area, and success rate. " + f"Find relevant OpenROAD documentation, parameter tuning guides, and failure pattern examples." + ) + + # Step 3: Execute search + rag_context = answerWithRAG( + query, + self.rag_embeddings, + self.rag_model, + self.rag_docs, + self.rag_docsDict, + ) + + if isinstance(rag_context, dict): # If returning dict + print(f"[DEBUG] RAG Retrieved {len(rag_context.get('docs', []))} related entries.") + for doc in rag_context.get("docs", [])[:3]: + print(f" ↳ {doc['title']} (score={doc['score']:.3f}) from {doc['source']}") + retrieved_text = rag_context.get("content", "") + else: + retrieved_text = rag_context + + # Step 4: 加入 prompt + if retrieved_text.strip(): + prompt += ( + "\n\n=== Retrieved OpenROAD Documentation (via RAG) ===\n" + f"{retrieved_text}\n" + "==============================================" + ) + print("[DEBUG] RAG: Context successfully added to prompt.") + else: + print("[DEBUG] RAG: Empty context retrieved.") + except Exception as e: + prompt += f"\n\n[WARN] RAG retrieval failed: {e}" + + if "log_data" in data: + all_errors = [] + for run in data["log_data"].get("runs", []): + if run.get("errors"): + all_errors.extend(run["errors"]) + + if all_errors: + error_summary = "\n".join(all_errors[-5:]) # The last 5 errors + prompt += f""" + + ### Detected Run Errors + {error_summary} + + The model must now act as an **EDA Debugging Assistant**. + Using the retrieved documentation and knowledge, analyze the errors above and: + 1. Identify the root causes of each error (e.g., tool misconfiguration, parameter overflow, timing issues, etc.) + 2. Suggest **specific parameter changes or flow adjustments** to prevent these errors. + 3. Indicate whether the error is likely due to constraints, routing congestion, or timing margin. + 4. Provide a short explanation for each suggestion. + + Output format: + Error Diagnosis: + - Root Cause: ... + - Recommended Fix: ... + - Suggested Parameter Change: ... + - Reason: ... + + """ + print("[DEBUG] Added error-fix section to prompt.") + def _collect_recent_errors(self, data: Dict[str, Any], max_errors=5) -> str: + errors = [] + for run in data.get("log_data", {}).get("runs", []): + if run.get("errors"): + errors.extend(run["errors"]) + print(f"[DEBUG] Found total {len(errors)} errors in all runs.") + return "\n".join(errors[-max_errors:]) if errors else "No errors detected." + + def _call_llm(self, stage: str, data: Dict[str, Any]) -> Dict[str, Any]: + # """Call Claude to get recommendations for optimization parameters""" + # print(f"\n=== Calling LLM for {stage} stage ===") + """Call LLM to get recommendations for optimization parameters using react framework""" + print(f"\n=== Calling LLM with ReAct framework for {stage} stage ===") + + try: + react_prompt = self._generate_react_prompt(stage, data) + print(f"Generated prompt with context for {stage}") + print("=== Context Message ===") + print(react_prompt) + print("========================") + available_tools = self._create_react_tools(stage, data) + + react_result = self.react_framework.run_react_cycle( + initial_prompt=react_prompt, + available_tools=available_tools, + max_steps=3, + temperature=0.1 + ) + # === If an error occurs, enter Debug mode === + if "log_data" in data and any(run.get("errors") for run in data["log_data"].get("runs", [])): + print("\n[DEBUG] Detected errors in previous runs. Invoking Debug Assistant mode...") + + # Collect error information + all_errors = [] + for run in data["log_data"]["runs"]: + if run.get("errors"): + all_errors.extend(run["errors"]) + error_text = "\n".join(all_errors[-5:]) # Recent entries + + # Construct a Debug Prompt + debug_prompt = f""" + You are now an **EDA Debugging Expert**. + Based on the following OpenROAD errors and RAG documentation, analyze and provide concrete repair suggestions. + + Errors Detected: + {error_text} + + Please identify: + 1. Root cause of each error. + 2. Specific parameter changes (e.g., in floorplan, CTS, or routing stages) that could fix the issue. + 3. Whether this issue is due to timing, congestion, or setup misconfiguration. + 4. One short explanation per fix. + + Return your answer in **JSON format** like: + {{ + "error_analysis": [ + {{ + "error": "...", + "cause": "...", + "fix": "...", + "params_to_adjust": {{"param_name": "new_value"}} + }} + ] + }} + """ + + # Call LLM to output repair suggestions + debug_result = self.react_framework.run_react_cycle( + initial_prompt=debug_prompt, + available_tools=available_tools, + max_steps=1, + temperature=0.2 + ) + + print("\n[DEBUG] LLM Debug Assistant Result:") + print(debug_result.get("final_answer", "")) + + # Save repair suggestions to the main results + react_result["error_fix_suggestions"] = debug_result.get("final_answer", "") + # Write files for manual viewing + with open("logs/error_fix_suggestions.json", "w") as f: + f.write(debug_result.get("final_answer", "")) + print(f"\n=== ReAct Cycle Completed ===") + print(f"Completed steps: {react_result.get('completed_steps', 0)}/{react_result.get('max_steps', 8)}") + print(f"Final Answer: {react_result['final_answer']}") + + configs = self._parse_react_final_answer(react_result["final_answer"], stage) + + if react_result.get('reasoning_history'): + print(f"\n=== Reasoning History ({len(react_result['reasoning_history'])} steps) ===") + for step in react_result['reasoning_history']: + print(f"Step {step['step']}: {step.get('thought', 'No thought')}") + + print(f"Returning config for stage '{stage}': {configs}") + return configs + + except Exception as e: + print(f"Error in LLM call for stage {stage}: {e}") + default_config = { + 'inspect': {"n_clusters": 5, "correlation_threshold": 0.5}, + 'model': {"kernel_type": "matern", "preprocessing": "robust", + "acquisition": "ei", "surrogate_weight": 0.8}, + 'agglomerate': {"method": "hybrid", "quality_weight": 0.7, + "uncertainty_bonus": 0.2} + } + return default_config.get(stage, {}) + + + def _generate_react_prompt(self, stage: str, data: Dict[str, Any]) -> str: + """generate prompts of ReAct framework""" + + stage_descriptions = { + 'inspect': ( + "You are an expert EDA optimization analyst. Analyze the optimization run data to identify patterns " + "and insights. Use the available tools to examine data distributions, correlations, and successful " + "parameter ranges. Your goal is to understand what makes runs successful and provide recommendations " + "for the modeling stage." + ), + 'model': ( + "You are an expert machine learning engineer for EDA optimization. Based on the inspection results, " + "configure the modeling approach for Bayesian optimization. Consider kernel selection, acquisition " + "functions, and surrogate modeling strategies. Balance exploration and exploitation based on the data." + ), + 'agglomerate': ( + "You are an expert parameter optimization specialist. Generate new parameter combinations for the " + "next optimization iteration. Use insights from previous stages to focus on promising regions while " + "maintaining diversity. Ensure all parameters satisfy the domain constraints." + ) + } + + constraints_text = "Parameter Constraints:\n" + for param, info in self.param_constraints.items(): + constraints_text += f"- {param} ({info['type']}, range: {info['range']})\n" + + react_format_instructions = """ +**ReAct Framework Instructions - MUST FOLLOW THIS FORMAT:** + +1. **Thought**: Analyze the current situation and decide what to do next +2. **Action**: Choose one tool from the available tools +3. **Action Input**: Provide the appropriate input for the chosen tool +4. **Observation**: Wait for the tool's response, then continue reasoning + +**Available Tools**: You have access to various analysis tools. Use them to gather information before making decisions. + +**DO NOT include Final Answer until you have completed all necessary analysis.** +**DO NOT predict or simulate tool observations.** +**You will receive actual Observation from tools before continuing.** + +Only after proper analysis: +**Final Answer Format**: Only when you have completed your analysis, provide: +Final Answer: {your_configuration_here} + +**Example**: +Thought: I need to understand the data patterns first. Let me analyze the success rates. +Action: analyze_data_patterns +Action Input: {} +Observation: [Tool response...] +Thought: Now I need to check parameter correlations... +Action: analyze_correlations +Action Input: {} +Observation: [Tool response...] +Final Answer: {"n_clusters": 5, "correlation_threshold": 0.7} +""" + + prompt = f""" + {stage_descriptions[stage]} + + **Current Stage**: {stage.upper()} + **Objective**: {self.objective} + **Platform**: {self.platform} + **Design**: {self.design} + + **Available Data**: + - Total runs: {data.get('log_data', {}).get('summary', {}).get('total_runs', 0)} + - Successful runs: {data.get('log_data', {}).get('summary', {}).get('successful_runs', 0)} + - Failed runs: {data.get('log_data', {}).get('summary', {}).get('failed_runs', 0)} + + {constraints_text} + {react_format_instructions} + + Begin your analysis: + """ + + rag_context = "" + # ======== extract errors ======== + error_summary = self._collect_recent_errors(data) + if error_summary and "No errors" not in error_summary: + print("[DEBUG] RAG: Detected error summary, adding error analysis prompt...") + prompt += f""" + + ### Detected Run Errors + {error_summary} + + You are now acting as an **EDA Debugging Assistant**. + Analyze the errors above and: + 1. Identify the root causes. + 2. Suggest specific parameter changes. + 3. Indicate whether the error is due to timing, routing, or constraints. + 4. Provide short explanations for each. + + Output format: + Error Diagnosis: + - Root Cause: ... + - Recommended Fix: ... + - Suggested Parameter Change: ... + - Reason: ... + """ + else: + print("[DEBUG] No errors found in logs for this stage.") + if getattr(self, "supervision_feedback", ""): + prompt += f""" + + ### Supervisor Feedback + {self.supervision_feedback} + + Please prioritize these supervisor notes when making decisions in this stage. + """ + print("[SUPERVISOR][DEBUG] Added supervisor feedback into prompt.") + if self.rag_model is not None and self.rag_embeddings is not None: + try: + print("[DEBUG] RAG: Starting retrieval...") + query = ( + f"Stage: {stage}. Objective: {self.objective}. " + f"Focus on analyzing {stage}-related optimization results. " + f"Important metrics include wirelength, timing, area, and success rate. " + f"Find relevant OpenROAD documentation, parameter tuning guides, and failure pattern examples." + ) + rag_context = answerWithRAG( + query, + self.rag_embeddings, + self.rag_model, + self.rag_docs, + self.rag_docsDict + ) + print(f"[DEBUG] RAG: Retrieved context length = {len(rag_context)}") + if rag_context.strip(): + prompt += ( + "\n\n=== Retrieved OpenROAD Documentation (via RAG) ===\n" + f"{rag_context}\n" + "==============================================" + ) + print("[DEBUG] RAG: Context successfully added to prompt.") + else: + print("[DEBUG] RAG: Empty context retrieved.") + except Exception as e: + prompt += f"\n\n[WARN] RAG retrieval failed: {e}" + + return prompt + + def _parse_react_final_answer(self, final_answer: str, stage: str) -> Dict[str, Any]: + """parse react final answer""" + + default_configs = { + 'inspect': {"n_clusters": 5, "correlation_threshold": 0.5}, + 'model': {"kernel_type": "matern", "preprocessing": "robust", + "acquisition": "ei", "surrogate_weight": 0.8}, + 'selection': {"method": "hybrid", "quality_weight": 0.7, + "uncertainty_bonus": 0.2} + } + + configs = {} + + if final_answer and "Reached maximum steps" not in final_answer: + try: + json_match = re.search(r'\{.*\}', final_answer, re.DOTALL) + if json_match: + extracted_config = json.loads(json_match.group()) + configs[stage] = extracted_config + print(f"✓ Extracted configuration from ReAct response: {extracted_config}") + else: + configs[stage] = default_configs.get(stage, {}) + print(f"Using default configuration for {stage} stage") + except Exception as e: + print(f"Error parsing ReAct final answer: {e}") + configs[stage] = default_configs.get(stage, {}) + else: + configs[stage] = default_configs.get(stage, {}) + print(f"ReAct failed to produce answer, using default for {stage}") + + return configs + + def run_iteration(self, num_runs: int) -> Dict[str, Any]: + """Run a single inspect-optimize-agglomerate flow and return its summary.""" + return self._execute_inspect_optimize_flow(num_runs, flow_index=0) + + # def run_dual_supervised_iterations(self, num_runs: int, num_flows: int) -> None: + # """ + # Run multiple inspect-optimize-agglomerate flows with supervisor feedback injected + # into the next flow's prompt. + # """ + # if num_flows <= 0: + # print("[WARN] num_flows must be >= 1, skipping execution.") + # return + + # self.supervision_feedback = "" + # for flow_index in range(num_flows): + # print(f"\n=== Dual-Supervised Flow {flow_index + 1}/{num_flows} ===") + # flow_summary = self._execute_inspect_optimize_flow(num_runs, flow_index=flow_index) + # supervisor_feedback = self._run_supervisor_review(flow_summary, flow_index) + # if supervisor_feedback: + # self.supervision_feedback = supervisor_feedback + # print("[SUPERVISOR] Stored feedback for the next flow iteration.") + # else: + # print("[SUPERVISOR] Supervisor produced no feedback; continuing without updates.") + + def run_dual_supervised_iterations(self, num_runs: int, num_flows: int) -> None: + if num_flows <= 0: + return + + for flow_index in range(num_flows): + print(f"\n=== Dual-Supervised Flow {flow_index + 1}/{num_flows} ===") + + # Run Flow (this will use the latest version from self.tool_instructions). + flow_summary = self._execute_inspect_optimize_flow(num_runs, flow_index=flow_index) + + # Get gradient (Supervisor Feedback) + supervisor_feedback = self._run_supervisor_review(flow_summary, flow_index) + + if supervisor_feedback and flow_index < num_flows - 1: + # [TextGrad Integration] 3. Perform Backpropagation Steps + # Here we assume we need to optimize the Prompt in the 'agglomerate' stage, as this is crucial for parameter generation. + # You can also intelligently decide which stage to optimize based on the feedback content. + print("[TextGrad] Backpropagating feedback to Agent Prompts...") + self._optimize_prompt_with_textgrad('agglomerate', supervisor_feedback) + self._optimize_prompt_with_textgrad('model', supervisor_feedback) + else: + print("[SUPERVISOR] No feedback or final iteration; skipping optimization.") + + def _execute_inspect_optimize_flow(self, num_runs: int, flow_index: int = 0) -> Dict[str, Any]: + """Internal helper containing the original inspect-optimize-agglomerate flow.""" + print(f"\n=== Starting optimization iteration #{flow_index + 1} for {self.platform}/{self.design} ===") + print(f"Objective: {self.objective}") + print(f"Number of runs requested: {num_runs}") + + # Step 1: Inspect logs + print("\nStep 1: Inspecting logs...") + log_data = self.inspect_logs() + print(f"Found {log_data['summary']['total_runs']} total runs, " + f"{log_data['summary']['successful_runs']} successful") + + # Get LLM recommendations for inspection and analysis + print("\nGetting LLM recommendations with ReAct framework for inspection...") + inspect_configs = self._call_llm('inspect', { + 'log_data': log_data, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context + }) + inspection_config = inspect_configs.get('inspect', {}) + print(f"React inspection config: {inspection_config}") + + # Step 2: Analyze metrics with LLM config + print("\nStep 2: Analyzing metrics ...") + metrics = self.analyze_metrics( + log_data, + n_clusters=inspection_config.get('n_clusters', 5), + correlation_threshold=inspection_config.get('correlation_threshold', 0.5) + ) + print(f"Processed metrics for {len(metrics.get('objectives', []))} successful runs") + + # Get LLM recommendations for modeling based on inspection results with ReAct framework + print("\nGetting LLM recommendations with ReAct framework for modeling...") + model_configs = self._call_llm('model', { + 'log_data': log_data, + 'metrics': metrics, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs + }) + model_config = model_configs.get('model', {}) + print(f"LLM model config: {model_config}") + + # Step 3: Evaluate models with LLM config + print("\nStep 3: Evaluating models...") + model_results = self.evaluate_models( + log_data, metrics, + model_config.get('kernel_type', 'matern'), + preprocessing=model_config.get('preprocessing', 'robust'), + acquisition=model_config.get('acquisition', 'ei'), + surrogate_weight=model_config.get('surrogate_weight', 0.8) + ) + + # Get LLM recommendations for parameter selection based on all previous results with ReAct framework + print("\nGetting LLM recommendations with ReAct framework for parameter selection...") + selection_configs = self._call_llm('agglomerate', { + 'log_data': log_data, + 'metrics': metrics, + 'model_results': model_results, + 'initial_params': self.initial_params, + 'sdc_context': self.sdc_context, + 'inspection_results': inspect_configs, + 'model_configs': model_configs + }) + selection_config = selection_configs.get('agglomerate', {}) + print(f"LLM selection config: {selection_config}") + + # Step 4: Generate parameters with LLM config + print("\nStep 4: Generating parameters...") + self.generate_parameters( + log_data, metrics, model_results, num_runs, + selection_method=selection_config.get('method', 'hybrid'), + quality_weight=selection_config.get('quality_weight', 0.7), + uncertainty_bonus=selection_config.get('uncertainty_bonus', 0.2) + ) + + flow_summary = { + "flow_index": flow_index, + "log_data": log_data, + "metrics": metrics, + "model_results": model_results, + "inspection_config": inspection_config, + "model_config": model_config, + "selection_config": selection_config, + "num_runs": num_runs, + "recent_errors": self._collect_recent_errors({"log_data": log_data}) + } + return flow_summary + + def _run_supervisor_review(self, flow_summary: Dict[str, Any], flow_index: int) -> str: + """ + Use a secondary model to critique the previous flow and return feedback + for the next prompt. + """ + flow_snapshot = { + "log_summary": flow_summary.get("log_data", {}).get("summary", {}), + "inspection_config": flow_summary.get("inspection_config", {}), + "model_config": flow_summary.get("model_config", {}), + "selection_config": flow_summary.get("selection_config", {}), + "recent_errors": flow_summary.get("recent_errors", ""), + "objective": self.objective, + "platform": self.platform, + "design": self.design, + } + + supervisor_prompt = ( + "You are the supervisor model for an EDA optimization agent.\n" + "The primary agent just finished an inspect-optimize-agglomerate flow.\n" + "Provide concise feedback (<=300 words) to guide the next flow. " + "Focus on:\n" + "1) What to adjust in inspection/model/selection configs,\n" + "2) Specific parameter or constraint reminders,\n" + "3) Warnings about errors or data issues.\n" + "Return plain text; start the message with 'Supervisor Feedback:'.\n" + f"Flow #{flow_index + 1} summary (JSON):\n{json.dumps(flow_snapshot, ensure_ascii=False, indent=2)}" + ) + print(f"[SUPERVISOR] Supervisor prompt: {supervisor_prompt}") + + try: + response = self.supervisor_client.chat.completions.create( + model=self.supervisor_model_name, + messages=[ + { + "role": "system", + "content": "You are a senior EDA optimization reviewer. Be concise and actionable.", + }, + {"role": "user", "content": supervisor_prompt}, + ], + temperature=0.2, + max_tokens=2048, + ) + feedback = response.choices[0].message.content.strip() + print(f"[SUPERVISOR] Feedback generated (len={len(feedback)}).") + return feedback + except Exception as e: + print(f"[SUPERVISOR] Failed to generate feedback: {e}") + return "" + + def inspect_logs(self) -> Dict[str, Any]: + """Step 1: Inspect all .log and .json logs recursively""" + log_dir = "logs" + pattern = f"{self.platform}_{self.design}_run" + + log_data = { + 'runs': [], + 'summary': { + 'total_runs': 0, + 'successful_runs': 0, + 'failed_runs': 0 + } + } + + if not os.path.exists(log_dir): + return log_data + + run_groups = {} + + for root, _, files in os.walk(log_dir): + for log_file in files: + if log_file.endswith(('.log', '.json')): + log_path = os.path.join(root, log_file) + + if log_file.startswith(pattern) or (self.platform in root and self.design in root): + + run_id = "main" + m = re.search(r'_run(\d+)\.log$', log_file) + if m: + run_id = f"base_{m.group(1)}" + + elif 'base_' in root: + run_id = os.path.basename(root) + + run_data = process_log_file(log_path) + + if run_id not in run_groups: + run_groups[run_id] = { + 'run_id': run_id, + 'success': True, + 'metrics': {}, + 'errors': [], + 'files': [] + } + + run_groups[run_id]['success'] &= run_data.get('success', True) + run_groups[run_id]['files'].append(log_path) + + if 'metrics' in run_data and run_data['metrics']: + run_groups[run_id]['metrics'].update(run_data['metrics']) + + if 'errors' in run_data and run_data['errors']: + run_groups[run_id]['errors'].extend(run_data['errors']) + + for run_id, run_data in run_groups.items(): + print(f"DEBUG: Run {run_id} success: {run_data['success']}") + print(f"DEBUG: Run {run_id} metrics: {run_data['metrics']}") + print(f"DEBUG: Run {run_id} errors: {run_data['errors']}") + print(f"DEBUG: Run {run_id} files: {run_data['files']}") + + log_data['runs'].append(run_data) + log_data['summary']['total_runs'] += 1 + if run_data['success']: + log_data['summary']['successful_runs'] += 1 + else: + log_data['summary']['failed_runs'] += 1 + + return log_data + + + def analyze_metrics(self, log_data: Dict[str, Any], n_clusters: int, correlation_threshold: float) -> Dict[str, Any]: + """Step 2: Analyze metrics from log data with improved analysis""" + metrics = { + 'objectives': [], + 'surrogates': [], + 'correlations': {}, + 'structure_analysis': {} + } + + # Extract feature vectors and objectives + feature_vectors = [] + objective_values = [] + surrogate_values = [] + + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + run_metrics = run['metrics'] + obj_values = self._calculate_objective(run) + + if obj_values['value'] is not None or obj_values['surrogate'] is not None: + # Extract parameter values as features + params = [] + for param in self.parameter_names: + params.append(float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0)))) + feature_vectors.append(params) + + objective_values.append(obj_values['value'] if obj_values['value'] is not None else np.nan) + surrogate_values.append(obj_values['surrogate'] if obj_values['surrogate'] is not None else np.nan) + + # Track correlations and other metrics + if obj_values['value'] is not None: + metrics['objectives'].append(obj_values['value']) + if obj_values['surrogate'] is not None: + metrics['surrogates'].append(obj_values['surrogate']) + + if obj_values['value'] is not None and obj_values['surrogate'] is not None: + if 'real_vs_surrogate' not in metrics['correlations']: + metrics['correlations']['real_vs_surrogate'] = [] + metrics['correlations']['real_vs_surrogate'].append({ + 'real': obj_values['value'], + 'surrogate': obj_values['surrogate'] + }) + + if feature_vectors: + X = np.array(feature_vectors) + Y = np.array(objective_values) + Y_surrogate = np.array(surrogate_values) + + # Use improved inspection functions + metrics['distribution_analysis'] = inspect_data_distribution(X, Y, Y_surrogate) + metrics['structure_analysis'] = inspect_data_structure(X, Y, { + 'n_clusters': n_clusters, + 'correlation_threshold': correlation_threshold + }) + + # Extract model recommendations if available (from new functions) + if 'model_recommendations' in metrics['structure_analysis']: + metrics['model_recommendations'] = metrics['structure_analysis']['model_recommendations'] + + # Add objective-specific metrics + if self.objective == 'ECP': + metrics['clock_period_impact'] = {} + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + period = float(run['metrics'].get('clock_period', 0)) + if period > 0: + if period not in metrics['clock_period_impact']: + metrics['clock_period_impact'][period] = { + 'final_slack': [], + 'cts_slack': [] + } + if 'worst_slack' in run['metrics']: + metrics['clock_period_impact'][period]['final_slack'].append( + float(run['metrics']['worst_slack'])) + if 'cts_ws' in run['metrics']: + metrics['clock_period_impact'][period]['cts_slack'].append( + float(run['metrics']['cts_ws'])) + + elif self.objective == 'DWL': + metrics['wirelength_progression'] = [] + for run in log_data['runs']: + if run['success'] and 'metrics' in run: + if 'cts_wirelength' in run['metrics'] and 'total_wirelength' in run['metrics']: + metrics['wirelength_progression'].append({ + 'cts': float(run['metrics']['cts_wirelength']), + 'final': float(run['metrics']['total_wirelength']) + }) + + return metrics + + + def evaluate_models(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + kernel_type: str, preprocessing: str, acquisition: str, surrogate_weight: float) -> Dict[str, Any]: + """Step 3: Use improved model functions to evaluate parameter quality""" + model_results = {} + + # Build context from log data and metrics + context = { + 'log_data': log_data, + 'metrics': metrics, + 'design_config': self.design_config, + 'initial_params': self.initial_params, + 'model_recommendations': metrics.get('model_recommendations', {}) + } + + # Use model recommendations if available (from new functions) + if 'model_recommendations' in metrics: + kernel_type = metrics['model_recommendations'].get('kernel_type', kernel_type) + preprocessing = 'robust' if metrics['model_recommendations'].get('needs_feature_scaling', True) else 'none' + + # Call appropriate model functions with improved modeling + if self.objective == 'ECP': + model_results = evaluate_timing_model(context) + elif self.objective == 'DWL': + model_results = evaluate_wirelength_model(context) + + # Add model configuration used + model_results['configuration'] = { + 'kernel_type': kernel_type, + 'preprocessing': preprocessing, + 'acquisition': acquisition, + 'surrogate_weight': surrogate_weight + } + + return model_results + + def generate_parameters(self, log_data: Dict[str, Any], metrics: Dict[str, Any], + model_results: Dict[str, Any], num_runs: int, + selection_method: str = 'hybrid', quality_weight: float = 0.7, + uncertainty_bonus: float = 0.2, model_config: Dict[str, Any] = None) -> None: + """Step 4: Generate parameter combinations and write to CSV""" + # Get list of parameters to optimize from constraints + param_names = list(self.param_constraints.keys()) + print(f"\nGenerating parameters for {len(param_names)} variables:") + for name in param_names: + print(f" - {name}: {self.param_constraints[name]}") + + # Extract successful runs for training data + successful_params = [] + successful_objectives = [] + for run in log_data.get('runs', []): + if run.get('success', False) and 'metrics' in run: + params = {} + for param in param_names: + params[param] = float(run.get('parameters', {}).get(param, self.initial_params.get(param, 0))) + successful_params.append(params) + + obj = self._calculate_objective(run) + successful_objectives.append(obj['value'] if obj['value'] is not None else obj['surrogate']) + + print(f"Using {len(successful_params)} successful runs as training data") + + # Convert to numpy arrays + if successful_params: + X = np.array([[params[name] for name in param_names] for params in successful_params]) + y = np.array(successful_objectives) + else: + print("Warning: No successful runs, using initial parameters as base") + X = np.array([[float(self.initial_params.get(name, 0)) for name in param_names]]) + y = np.array([0.0]) + + # Get kernel type from model config + kernel_type = model_config.get('kernel_type', 'matern') if model_config else 'matern' + print(f"\nCreating surrogate model with {kernel_type} kernel") + model = create_model(X, y, kernel_type=kernel_type) + + # Generate candidates + n_candidates = num_runs * 10 + print(f"Generating {n_candidates} candidate points") + candidates = latin_hypercube(n_candidates, len(param_names)) + + # Scale candidates to parameter ranges + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + candidates[:, i] = candidates[:, i] * (max_val - min_val) + min_val + + # Get predictions + predictions, uncertainties = model.predict(candidates, return_std=True) + + # Select points + print(f"\nSelecting points using {selection_method} method") + print(f"Quality weight: {quality_weight}, Uncertainty bonus: {uncertainty_bonus}") + quality_scores = create_quality_scores(candidates, y, predictions, uncertainties) + selected_indices = select_points( + candidates, quality_scores, + method=selection_method, + n_points=num_runs, + config={"quality_weight": quality_weight, + "uncertainty_bonus": uncertainty_bonus} + ) + + selected_params = candidates[selected_indices] + + # Validate domain constraints + print("\nValidating domain constraints...") + valid_params = [] + for params in selected_params: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + else: + print("Warning: Parameter set failed domain constraints") + + print(f"Found {len(valid_params)} valid parameter sets out of {len(selected_params)}") + + # Generate more if needed + while len(valid_params) < num_runs: + needed = num_runs - len(valid_params) + print(f"Generating {needed} additional parameter sets...") + new_candidates = latin_hypercube(needed, len(param_names)) + for i, param in enumerate(param_names): + constraints = self.param_constraints[param] + min_val = float(constraints['range'][0]) + max_val = float(constraints['range'][1]) + new_candidates[:, i] = new_candidates[:, i] * (max_val - min_val) + min_val + + for params in new_candidates: + param_dict = {name: value for name, value in zip(param_names, params)} + if self._validate_domain_constraints(param_dict): + valid_params.append(param_dict) + if len(valid_params) >= num_runs: + break + + # Write to CSV + print(f"\nWriting {num_runs} parameter sets to CSV...") + self._write_params_to_csv(valid_params[:num_runs]) + + def _calculate_objective(self, run: Dict[str, Any]) -> Dict[str, float]: + """Calculate objective value and surrogate from run metrics""" + metrics = run.get('metrics', {}) + result = {'value': None, 'surrogate': None} + + if self.objective == 'ECP': + if 'clock_period' in metrics: + period = float(metrics['clock_period']) + # Real ECP from final worst slack + if 'worst_slack' in metrics: + result['value'] = period - float(metrics['worst_slack']) + # Surrogate ECP from CTS worst slack + if 'cts_ws' in metrics: + result['surrogate'] = period - float(metrics['cts_ws']) + + elif self.objective == 'DWL': + # Real wirelength from detailed route + if 'total_wirelength' in metrics: + result['value'] = float(metrics['total_wirelength']) + # Surrogate wirelength from CTS + if 'cts_wirelength' in metrics: + result['surrogate'] = float(metrics['cts_wirelength']) + + elif self.objective == 'COMBO': + # Get weights from environment variables + try: + ecp_weight = float(os.environ.get('ECP_WEIGHT')) + wl_weight = float(os.environ.get('WL_WEIGHT')) + ecp_weight_surrogate = float(os.environ.get('ECP_WEIGHT_SURROGATE')) + wl_weight_surrogate = float(os.environ.get('WL_WEIGHT_SURROGATE')) + except (ValueError, TypeError): + raise ValueError("Weights not properly set in environment variables.") + + # Calculate real ECP and WL values + ecp_value = None + wl_value = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'worst_slack' in metrics: + ecp_value = clock_period - float(metrics['worst_slack']) + if 'total_wirelength' in metrics: + wl_value = float(metrics['total_wirelength']) + + # Calculate surrogate ECP and WL values + ecp_surrogate = None + wl_surrogate = None + if 'clock_period' in metrics: + clock_period = float(metrics['clock_period']) + if 'cts_ws' in metrics: + ecp_surrogate = clock_period - float(metrics['cts_ws']) + if 'cts_wirelength' in metrics: + wl_surrogate = float(metrics['cts_wirelength']) + + # Calculate weighted objective for real values + if ecp_value is not None and wl_value is not None: + result['value'] = ecp_weight * ecp_value + wl_weight * wl_value + elif ecp_value is not None: + result['value'] = ecp_weight * ecp_value + elif wl_value is not None: + result['value'] = wl_weight * wl_value + + # Calculate weighted surrogate objective + if ecp_surrogate is not None and wl_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + wl_weight_surrogate * wl_surrogate + elif ecp_surrogate is not None: + result['surrogate'] = ecp_weight_surrogate * ecp_surrogate + elif wl_surrogate is not None: + result['surrogate'] = wl_weight_surrogate * wl_surrogate + + return result + + def _validate_domain_constraints(self, params: Dict[str, Any]) -> bool: + """Validate parameter combinations against domain constraints""" + # 1. Core utilization vs cell padding + core_util = float(params.get('core_util', 0)) + gp_pad = float(params.get('cell_pad_global', 0)) + dp_pad = float(params.get('cell_pad_detail', 0)) + + if core_util > 80 and (gp_pad > 2 or dp_pad > 2): + print(f"Domain constraint failed: core_util > 80 and gp_pad > 2 or dp_pad > 2") + return False + + # 2. TNS end percent vs place density + tns_end = float(params.get('tns', 0)) + place_density = float(params.get('lb_addon', 0)) + + if tns_end < 70 and place_density > 0.7: + print(f"Domain constraint failed: tns_end < 70 and place_density > 0.7") + return False + + # 3. CTS cluster constraints + cts_size = float(params.get('cts_size', 0)) + cts_diameter = float(params.get('cts_diameter', 0)) + + if cts_size > 30 and cts_diameter < 100: + print(f"Domain constraint failed: cts_size > 30 and cts_diameter < 100") + return False + + return True + + def _write_params_to_csv(self, params_list: List[Dict[str, Any]]) -> None: + """Write the new parameter sets to the expected CSV file for the next iteration""" + csv_file = f"designs/{self.platform}/{self.design}/{self.platform}_{self.design}.csv" + + # Ensure parameters are in correct order and properly typed + with open(csv_file, 'w', newline='\n') as f: # Explicitly use Unix line endings + writer = csv.writer(f) + # Write header in correct order + writer.writerow(self.parameter_names) + + # Write parameter rows + for params in params_list: + row = [] + for param_name in self.parameter_names: + value = params.get(param_name) + if value is None: + print(f"Warning: Missing value for parameter {param_name}") + continue + + # Apply type constraints + constraint = self.param_constraints[param_name] + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param_name} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + + except (ValueError, TypeError) as e: + print(f"Error converting {param_name} value '{value}' to {param_type}: {e}") + continue + + row.append(value) + + if len(row) == len(self.parameter_names): + writer.writerow(row) + else: + print(f"Warning: Skipping incomplete parameter set") + + print(f"New parameter sets written to {csv_file}") + + def _parse_llm_output(self, llm_response: str) -> List[Dict[str, Any]]: + """Parse the LLM's response and enforce parameter constraints""" + try: + param_sets = json.loads(llm_response) + except json.JSONDecodeError as e: + print(f"Error parsing LLM response: {e}") + return [] + + constrained_params = [] + for param_set in param_sets: + ordered_params = {} + valid = True + for param in self.parameter_names: + value = param_set.get(param) + if value is None: + print(f"Parameter '{param}' is missing in the LLM output.") + valid = False + break + + constraint = self.param_constraints.get(param) + if constraint: + param_type = constraint['type'] + param_range = constraint['range'] + + try: + # First convert to float for uniform handling + value = float(value) + + # Apply range constraints if they exist + if param_range is not None: + min_val, max_val = param_range + range_size = max_val - min_val + + # If value is too far out of range, resample uniformly + if value > max_val + range_size or value < min_val - range_size: + value = random.uniform(min_val, max_val) + print(f"Resampled {param} to {value} (was too far out of range)") + else: + # Otherwise just clamp to range + value = max(min_val, min(max_val, value)) + + # Convert to final type after range enforcement + if param_type == 'int': + value = int(round(value)) + elif param_type != 'float': + raise ValueError(f"Unsupported parameter type: {param_type}") + + ordered_params[param] = value + except (ValueError, TypeError) as e: + print(f"Parameter '{param}' has invalid value '{value}': {e}") + valid = False + break + else: + print(f"Unknown parameter '{param}' in parameter set.") + valid = False + break + + if valid and self._validate_domain_constraints(ordered_params): + constrained_params.append(ordered_params) + else: + print(f"Parameter set {ordered_params} failed validation and will be discarded.") + + return constrained_params + + def generate_initial_parameters(self, num_runs: int) -> None: + """Generate initial random parameters and write them to CSV using the same method as subsequent iterations""" + params_list = [] + for _ in range(num_runs): + params = {} + for param in self.parameter_names: + info = self.param_constraints[param] + param_type = info['type'] + min_value, max_value = info['range'] + if param_type == 'int': + value = random.randint(int(min_value), int(max_value)) + elif param_type == 'float': + value = random.uniform(min_value, max_value) + else: + continue # Skip unsupported types + params[param] = value + params_list.append(params) + + # Use the same method to write parameters to CSV + self._write_params_to_csv(params_list) + +def main(): + if len(sys.argv) not in (5, 6): + print("Usage: optimize_dual.py []") + sys.exit(1) + + platform = sys.argv[1] + design = sys.argv[2] + objective = sys.argv[3] + num_runs = int(sys.argv[4]) + num_flows = int(sys.argv[5]) if len(sys.argv) == 6 else 1 + + workflow = OptimizationWorkflow(platform, design, objective) + # Keep backward compatibility: a single flow behaves like the legacy run_iteration. + workflow.run_dual_supervised_iterations(num_runs, num_flows) + +if __name__ == "__main__": + main() diff --git a/flow-Agent/rag/README.md b/flow-Agent/rag/README.md new file mode 100644 index 0000000..8a89046 --- /dev/null +++ b/flow-Agent/rag/README.md @@ -0,0 +1 @@ +Contains code and configuration files related to the RAG framework, which is used to implement the Retrieval-Augmented Generation process. diff --git a/flow-Agent/rag/__init__.py b/flow-Agent/rag/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/flow-Agent/rag/_pycache_/README.md b/flow-Agent/rag/_pycache_/README.md new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/flow-Agent/rag/_pycache_/README.md @@ -0,0 +1 @@ + diff --git a/flow-Agent/rag/_pycache_/__init__.cpython-38.pyc b/flow-Agent/rag/_pycache_/__init__.cpython-38.pyc new file mode 100644 index 0000000..1cfa011 Binary files /dev/null and b/flow-Agent/rag/_pycache_/__init__.cpython-38.pyc differ diff --git a/flow-Agent/rag/_pycache_/index.cpython-38.pyc b/flow-Agent/rag/_pycache_/index.cpython-38.pyc new file mode 100644 index 0000000..a9a2c3d Binary files /dev/null and b/flow-Agent/rag/_pycache_/index.cpython-38.pyc differ diff --git a/flow-Agent/rag/_pycache_/util.cpython-38.pyc b/flow-Agent/rag/_pycache_/util.cpython-38.pyc new file mode 100644 index 0000000..edd8048 Binary files /dev/null and b/flow-Agent/rag/_pycache_/util.cpython-38.pyc differ diff --git a/flow-Agent/rag/build_index.py b/flow-Agent/rag/build_index.py new file mode 100644 index 0000000..e69de29 diff --git a/flow-Agent/rag/index.py b/flow-Agent/rag/index.py new file mode 100644 index 0000000..8833b20 --- /dev/null +++ b/flow-Agent/rag/index.py @@ -0,0 +1,62 @@ +import os +import pickle +import numpy as np +import pandas as pd +from sentence_transformers import SentenceTransformer +from .util import load_multiple_qa_files, prepareDocuments + +# 数据与模型路径 +BASE_DIR = os.path.dirname(__file__) +DATA_DIR = os.path.join(BASE_DIR, "..", "rag_date") +EMB_PATH = os.path.join(DATA_DIR, "embeddings.npy") +DOCS_PATH = os.path.join(DATA_DIR, "docs.pkl") + +# 默认模型路径（可修改） +DEFAULT_MODEL_PATH = "/mnt/c/Users/Public/OpenROAD-flow-scripts/orfs-agent/models/mxbai-embed-large-v1" + +# ============================================================ +# 🔹 构建并保存 Embedding 向量库 +# ============================================================ +def build_and_save_embeddings(base_dir="/mnt/e/OpenROAD-flow-scripts/orfs-agent/EDA-Corpus-main/Augmented_Data/Question-Answer", + model_name=DEFAULT_MODEL_PATH): + """ + 从 Flow / General / Tools 三个 CSV 构建向量库并保存。 + """ + print("[RAG] 正在加载 QA 文件...") + df = load_multiple_qa_files(base_dir) + + # 准备文档 + docs, docsDict = prepareDocuments(df) + + # 构建模型 + print(f"[RAG] 正在加载嵌入模型：{model_name}") + model = SentenceTransformer(model_name) + + # 生成向量 + print("[RAG] 正在生成文本向量...") + embeddings = model.encode(docs, convert_to_numpy=True, show_progress_bar=True) + + # 确保保存路径存在 + os.makedirs(DATA_DIR, exist_ok=True) + + # 保存 + np.save(EMB_PATH, embeddings) + with open(DOCS_PATH, "wb") as f: + pickle.dump((docs, docsDict), f) + + print(f"[RAG] ✅ 向量库构建完成并保存到 {DATA_DIR}") + + +# ============================================================ +# 🔹 加载已保存的向量库 +# ============================================================ +def load_embeddings_and_docs(): + if not os.path.exists(EMB_PATH) or not os.path.exists(DOCS_PATH): + raise FileNotFoundError("[RAG] 向量库文件不存在，请先运行 build_and_save_embeddings()") + + embeddings = np.load(EMB_PATH) + with open(DOCS_PATH, "rb") as f: + docs, docsDict = pickle.load(f) + + print(f"[RAG] 成功加载向量库，共 {len(docs)} 条文档。") + return embeddings, docs, docsDict \ No newline at end of file diff --git a/flow-Agent/rag/util.py b/flow-Agent/rag/util.py new file mode 100644 index 0000000..eaec640 --- /dev/null +++ b/flow-Agent/rag/util.py @@ -0,0 +1,277 @@ +import pandas as pd +import numpy as np +from sentence_transformers import SentenceTransformer, util as st_util +import os + +class modelUtility: + def __init__(self, modelName: str): + self.modelName = modelName + # ... 把你现有的 systemPrompt 和所有 ragPromptTemplate* 复制进来 ... + # (直接使用你之前提供的内容) + if modelName == "OpenROAD-Assistant/Script_Adaptor": + self.systemPrompt = """You are a tutor specializing in the knowledge of OpenROAD, the open-source EDA tool. You will be asked about general OpenROAD questions and OpenROAD Python API-related questions. +""" + else: + self.systemPrompt = """You are a OpenROAD Python code generator. You will generate the Python code to complete the task. Follow the following guidelines: +1. Only generate Python code, do not include any other text. +2. First generate ```python before the start of the Python code. +3. Generate ``` when finished the Python code. +4. If you don't know the answer, respond with: +```python +``` +""" + if "llama" not in modelName.lower() and "script_adaptor" not in modelName.lower() and "retrained" not in modelName.lower(): + self.ragPromptTemplateWithContext = """<|im_start|>system +{system_prompt}<|im_end|> +<|im_start|>user +Here are the OpenROAD APIs, You do not need to use them unless they are directly relevant to the answer: +===================== +{context} +===================== +Here is your task: +===================== +{question} +===================== + +If you define a function, you MUST actually call it in the code. +MUST NOT comment out the code that you write, especially the code you call the function.<|im_end|> +<|im_start|>assistant +""" + self.ragPromptTemplateWithoutContext = """<|im_start|>system +{system_prompt}<|im_end|> +<|im_start|>user +Here is your task: +===================== +{question} +===================== + +If you define a function, you MUST actually call it in the code. +MUST NOT comment out the code that you write, especially the code you call the function.<|im_end|> +<|im_start|>assistant +""" + self.ragWrongCodePromptTemplateWithContext = """<|im_start|>system +{system_prompt}<|im_end|> +<|im_start|>user +Here is your OpenROAD Python code generation task: +===================== +{question} +===================== + +Here is the wrong code you previously generated: +===================== +{wrongCode} +===================== + +I got the warning message when running the above wrong code: +===================== +{message} +===================== + +Here are some OpenROAD APIs, You do not need to use them unless they are directly relevant to the answer: +===================== +{context} +===================== + +The wrong code is not correct, please correct the wrong code or generate a new code to accomplish the OpenROAD Python code generation task. + +If you define a function, you MUST actually call it in the code. +MUST NOT comment out the code that you write, especially the code you call the function.<|im_end|> +<|im_start|>assistant +""" + self.ragWrongCodePromptTemplateWithoutContext = """<|im_start|>system +{system_prompt}<|im_end|> +<|im_start|>user +Here is your OpenROAD Python code generation task: +===================== +{question} +===================== + +Here is the wrong code you previously generated: +===================== +{wrongCode} +===================== + +I got the warning message when running the above wrong code: +===================== +{message} +===================== + +The wrong code is not correct, please correct the wrong code or generate a new code to accomplish the OpenROAD Python code generation task. + +If you define a function, you MUST actually call it in the code. +MUST NOT comment out the code that you write, especially the code you call the function.<|im_end|> +<|im_start|>assistant +""" + else: + self.ragPromptTemplateWithContext = """<|begin_of_text|><|start_header_id|>system<|end_header_id|> +{system_prompt}<|eot_id|> +<|start_header_id|>user<|end_header_id|> +Here are the OpenROAD APIs, You do not need to use them unless they are directly relevant to the answer: +===================== +{context} +===================== +Here is your task: +===================== +{question} +===================== + +If you define a function, you MUST actually call it in the code. +MUST NOT comment out the code that you write, especially the code you call the function.<|eot_id|> +<|start_header_id|>assistant<|end_header_id|> +""" + self.ragPromptTemplateWithoutContext = """<|begin_of_text|><|start_header_id|>system<|end_header_id|> +{system_prompt}<|eot_id|> +<|start_header_id|>user<|end_header_id|> +Here is your task: +===================== +{question} +===================== + +If you define a function, you MUST actually call it in the code. +MUST NOT comment out the code that you write, especially the code you call the function.<|eot_id|> +<|start_header_id|>assistant<|end_header_id|> +""" + self.ragWrongCodePromptTemplateWithContext = """<|begin_of_text|><|start_header_id|>system<|end_header_id|> +{system_prompt}<|eot_id|> +<|start_header_id|>user<|end_header_id|> +Here is your OpenROAD Python code generation task: +===================== +{question} +===================== + +Here is the wrong code you previously generated: +===================== +{wrongCode} +===================== + +I got the warning message when running the above wrong code: +===================== +{message} +===================== + +Here are some OpenROAD APIs, You do not need to use them unless they are directly relevant to the answer: +===================== +{context} +===================== + +The wrong code is not correct, please correct the wrong code or generate a new code to accomplish the OpenROAD Python code generation task. +If you define a function, you MUST actually call it in the code. +MUST NOT comment out the code that you write, especially the code you call the function.<|eot_id|> +<|start_header_id|>assistant<|end_header_id|> +""" + self.ragWrongCodePromptTemplateWithoutContext = """<|begin_of_text|><|start_header_id|>system<|end_header_id|> +{system_prompt}<|eot_id|> +<|start_header_id|>user<|end_header_id|> +Here is your OpenROAD Python code generation task: +===================== +{question} +===================== + +Here is the wrong code you previously generated: +===================== +{wrongCode} +===================== + +I got the warning message when running the above wrong code: +===================== +{message} +===================== + +The wrong code is not correct, please correct the wrong code or generate a new code to accomplish the OpenROAD Python code generation task. +If you define a function, you MUST actually call it in the code. +MUST NOT comment out the code that you write, especially the code you call the function.<|eot_id|> +<|start_header_id|>assistant<|end_header_id|> +""" + def isOpenROADAssistant(self): + return "OpenROAD-Assistant/Script_Adaptor" == self.modelName + +# ======================================================= +# 🔹 新增函数：支持从多个 QA 文件中加载合并数据 +# ======================================================= +def load_multiple_qa_files(base_dir): + """ + 从 base_dir 中读取 Flow.csv, General.csv, Tools.csv 三个文件并合并。 + """ + paths = [ + os.path.join(base_dir, "Flow", "Flow.csv"), + os.path.join(base_dir, "General", "General.csv"), + os.path.join(base_dir, "Tools", "Tools.csv"), + ] + + import glob + csv_paths = glob.glob(os.path.join(base_dir, "**", "*.csv"), recursive=True) + csv_paths = sorted(csv_paths) + if not csv_paths: + raise FileNotFoundError(f"[ERROR] No CSV files found under {base_dir}") + + + dfs = [] + total_rows_before = 0 + + for p in paths: + if os.path.exists(p): + try: + df = pd.read_csv(p) + dfs.append(df) + print(f"[INFO] Loaded {p} ({len(df)} rows)") + except Exception as e: + print(f"[WARN] Failed to read {p}: {e}") + else: + print(f"[WARN] File not found: {p}") + + if not dfs: + raise FileNotFoundError("[ERROR] No valid QA CSV files found in base_dir") + + df_all = pd.concat(dfs, ignore_index=True) + print(f"[INFO] Total rows before dedup: {total_rows_before}; concatenated: {len(df_all)}") + + # 不立即 drop_duplicates，先保存原始数，便于调试 + df_clean = df_all.drop_duplicates().fillna("") + print(f"[INFO] After drop_duplicates & fillna: {len(df_clean)} rows") + + return df_clean + + + +def prepareDocuments(df): + """ + 仅用于 QA 数据集。提取 Prompts 和 Answers 列，组合为文档。 + """ + documents = [] + documentsDict = {} + + if not {"Prompts", "Answers"}.issubset(df.columns): + raise ValueError("[ERROR] The input DataFrame must contain 'Prompts' and 'Answers' columns.") + + for _, row in df.iterrows(): + q, a = str(row["Prompts"]).strip(), str(row["Answers"]).strip() + if not q or not a: + continue + content = f"Q: {q}\nA: {a}" + documents.append(content) + documentsDict[content] = {"Prompts": q, "Answers": a} + + print(f"[INFO] Prepared {len(documents)} QA documents for embedding.") + return documents, documentsDict + + + +def answerWithRAG(question, embeddings, embeddingModel, allSplits, allDict, topk=10, score_threshold=0.4): + q_emb = embeddingModel.encode(question, convert_to_tensor=True).cpu() + # embeddings is a tensor (convert_to_tensor=True recommended) + scores = st_util.cos_sim(q_emb, embeddings.cpu()) # shape (1, N) + np_scores = scores.cpu().numpy().flatten() + top_idx = np.argsort(np_scores)[-topk:][::-1] + relevantDocs = [] + for idx in top_idx: + print(f"[DEBUG] RAG candidate {idx} score={np_scores[idx]:.3f}") + if np_scores[idx] < score_threshold: + break + relevantDocs.append(allSplits[idx]) + finalDocs = [] + for doc in relevantDocs: + finalDocs.append("\n".join(f"# {k} {v}" for k, v in allDict[doc].items())) + context = "" + if finalDocs: + context = "\n\n".join(finalDocs) + return context \ No newline at end of file diff --git a/flow-Agent/rag_data/RAGAPIs.csv b/flow-Agent/rag_data/RAGAPIs.csv new file mode 100644 index 0000000..0f995a1 --- /dev/null +++ b/flow-Agent/rag_data/RAGAPIs.csv @@ -0,0 +1,193 @@ +Description:,Function Name:,Parameters:,Return Type: +Get the openroad.Tech object,openroad.Tech(),,openroad.Tech +Read .lib files,openroad.Tech.readLiberty(,str(file_name), +Read .lef files,openroad.Tech.readLef(,str(file_name), +Get the openroad db via openroad.Tech object,openroad.Tech.getDB(),,odb.dbDatabase +Get the openroad.Design object,openroad.Design(,openroad.Tech,openroad.Design +Get the I/O pin placer,openroad.Design.getIOPlacer(),,ppl.IOPlacer +Use the name of the layer to get the odb.dbTechLayer object,openroad.Design.getTech().getDB().getTech().findLayer(,str(layer_name),odb.dbTechLayer +Get the parameters of the IO pin placer,ppl.IOPlacer.getParameters(,,ppl.Parameters +Set the minimum distance between each pin of the IO pin placer,ppl.Parameters.setMinDistance(,int(min_dist), +Get the setting of the minimum distance between each pin of the IO pin placer,ppl.Parameters.getMinDistance(),,int +"Set the unit for calling ppl.Parameters.setMinDistance(int) in ""number of tracks"" or in openroad's unit of the IO pin placer",ppl.Parameters.setMinDistanceInTracks(,bool(in_track), +"Check if the unit fot calling ppl.Parameters.setMinDistance(int) of the IO pin placer is in ""number of tracks"" or in openroad's unit, return True if is in ""number of tracks”",ppl.Parameters.getMinDistanceInTracks(),,bool +Get the floorplanner,openroad.Design.getFloorplan(),,ifp.InitFloorplan +"get the minimum placing unit of the design, the input is the name of the site desifned in the technology file",ifp.InitFloorplan.findSite(,str(site),odb.dbSite +"Create tracks, must call this after floorplanning",ifp.InitFloorplan.makeTracks(),, +"Perform floorplanning, utilization is in [0, 100]%. The base_site determines the single-height rows. For hybrid rows it is a site containing a row pattern.",ifp.InitFloorplan.initFloorplan(,"float(utilization), float(aspect_ratio), int(core_space_bottom), int(core_space_top), int(core_space_left), int(core_space_right), odb.dbSite", +"Perform floorplanning, the base_site determines the single-height rows. For hybrid rows it is a site containing a row pattern.",ifp.InitFloorplan.initFloorplan(,"odb.Rect(die), odb.Rect(core), odb.dbSite(base_site)", +Create an openroad.odb.Rect object,odb.Rect(,"int(x1), int(y1), int(x2), int(y2)",odb.Rect +Similar to openroad.get_db_block,openroad.Design.getBlock(),,odb.dbBlock +Get the name of the pin,openroad.Design.getITermName(,odb.dbITerm(),str +Check if a instance is a part of clock nets,openroad.Design.isInClock(,odb.dbInst(),bool +Read the Verilog files into OpenROAD,openroad.Design.readVerilog(,str(file_name), +Read the design file in DEF format (containing placement and routing information),openroad.Design.readDef(,str(file_name), +Find the top module of the Verilog file and connect all other modules. The Verilog files must be read into OpenROAD first.,openroad.Design.link(,str(design_name), +Read the design file written in OpenROAD database format,openroad.Design.readDb(,str(file_name), +Write the design file in OpenROAD database format,openroad.Design.writeDb(,str(file_name), +Change the unit from micron (um) to the unit used in OpenROAD,openroad.Design.micronToDBU(,float(coord),int +Similar to openroad.get_db_tech(),openroad.Design.getTech(),,openroad.Tech +Check is a library cell (master cell) is a buffer,openroad.Design.isBuffer(,odb.dbMaster(),bool +Check if a library cell (master cell) is an inverter,openroad.Design.isInverter(,odb.dbMaster(),bool +Check if a library cell (master cell) is a flip-flop,openroad.Design.isSequential(,odb.dbMaster(),bool +Check if a pin is connected to VDD or VSS net,openroad.Design.isInSupply(,odb.dbITerm(),bool +Get the actual physical wirelength of a routed net,openroad.Design.getNetRoutedLength(,odb.dbNet(),int +"Write DEF file, str is the name of the file",openroad.Design.writeDef(,str(file_name), +Get the openroad.Timing object,openroad.Timing(,openroad.Design,openroad.Timing +Get the sum of switching and internal power of an instance,openroad.Timing.dynamicPower(,"odb.dbInst(), openroad.Timing.getCorners()[int(index)]",float +Get the sum of wire capacitance and pin capacitance of a Net,openroad.Timing.getNetCap(,"odb.dbNet(), openroad.Timing.getCOrners()[int(index)], openroad.Timing.Max",float +Get the sum of wire capacitance and pin capacitance of a Net,openroad.Timing.getNetCap(,"odb.dbNet(), openroad.Timing.getCOrners()[int(index)], openroad.Timing.Min",float +Get the maximum rising arrival time of a pin across all corners,openroad.Timing.getPinArrival(,"odb.dbITerm(), openroad.Timing.Rise, openroad.Timing.Max",float +Get the minimum rising arrival time of a pin across all corners,openroad.Timing.getPinArrival(,"odb.dbITerm(), openroad.Timing.Rise, openroad.Timing.Min",float +Get the maximum falling arrival time of a pin across all corners,openroad.Timing.getPinArrival(,"odb.dbITerm(), openroad.Timing.Fall, openroad.Timing.Max",float +Get the minimum falling arrival time of a pin across all corners,openroad.Timing.getPinArrival(,"odb.dbITerm(), openroad.Timing.Fall, openroad.Timing.Min",float +Get the maximum rising arrival time of a port across all corners,openroad.Timing.getPinArrival(,"odb.dbBTerm(), openroad.Timing.Rise, openroad.Timing.Max",float +Get the minimum rising arrival time of a port across all corners,openroad.Timing.getPinArrival(,"odb.dbBTerm(), openroad.Timing.Rise, openroad.Timing.Min",float +Get the maximum falling arrival time of a port across all corners,openroad.Timing.getPinArrival(,"odb.dbBTerm(), openroad.Timing.Fall, openroad.Timing.Max",float +Get the minimum falling arrival time of a port across all corners,openroad.Timing.getPinArrival(,"odb.dbBTerm(), openroad.Timing.Fall, openroad.Timing.Min",float +Get the maximum rising slack of a pin across all corners ,openroad.Timing.getPinSlack(,"odb.dbITerm(), openroad.Timing.Rise, openroad.Timing.Max",float +Get the minimum rising slack of a pin across all corners ,openroad.Timing.getPinSlack(,"odb.dbITerm(), openroad.Timing.iming.Rise, openroad.Timing.Min",float +Get the maximum falling slack of a pin across all corners ,openroad.Timing.getPinSlack(,"odb.dbITerm(), openroad.Timing.Fall, openroad.Timing.Max",float +Get the minimum falling slack of a pin across all corners ,openroad.Timing.getPinSlack(,"odb.dbITerm(), openroad.Timing.Fall, openroad.Timing.Min",float +Get the maximum rising slack of a port across all corners ,openroad.Timing.getPinSlack(,"odb.dbBTerm(), openroad.Timing.Rise, openroad.Timing.Max",float +Get the minimum rising slack of a port across all corners ,openroad.Timing.getPinSlack(,"odb.dbBTerm(), openroad.Timing.Rise, openroad.Timing.Min",float +Get the maximum falling slack of a port across all corners ,openroad.Timing.getPinSlack(,"odb.dbBTerm(), openroad.Timing.Fall, openroad.Timing.Max",float +Get the minimum falling slack of a port across all corners ,openroad.Timing.getPinSlack(,"odb.dbBTerm(), openroad.Timing.Fall, openroad.Timing.Min",float +Get the minimum slew of the pin across all corners,openroad.Timing.getPinSlew(,"odb.dbITerm, openroad.Timing.Min",float +Get the maximum slew of the pin across all corners,openroad.Timing.getPinSlew(,"odb.dbITerm, openroad.Timing.Max",float +Get the minimum slew of the port across all corners,openroad.Timing.getPinSlew(,"odb.dbBTerm, openroad.Timing.Min",float +Get the maximum slew of the port across all corners,openroad.Timing.getPinSlew(,"odb.dbBTerm, openroad.Timing.Max",float +Get the maximum input capacitance of a pin,openroad.Timing.getPortCap(,"odb.ITerm, openroad.Timing.getCorners()[int(index)], openroad.Timing.Max",float +Get the minimum input capacitance of a pin,openroad.Timing.getPortCap(,"odb.ITerm, openroad.Timing.getCorners()[int(index)], openroad.Timing.Min",float +Check if the pin is the end point of a timing path,openroad.Timing.isEndpoint(,odb.ITerm(),bool +Check if the port is the end point of a timing path,openroad.Timing.isEndpoint(,odb.BTerm(),bool +"Check if the number is ""inf""",openroad.Timing.isTimeInf(,float(time),bool +Get the instance's leakage power,openroad.Timing.staticPower(,"odb.dbInst, openroad.Timing.getCorners()[int(index)]",float +Get the global placer,openroad.Design.getReplace(),,gpl.Replace +"Perform global placement (don't call this function if ""gpl.Replace.doInitialPlace()"" or ""gpl.Replace.doNesterovPlace()"" is called)",gpl.Replace.doIncrementalPlace(,int(thread), +"Perform global placement (don't call this function if ""gpl.Replace.doIncrementalPlace()"" is called)",gpl.Replace.doInitialPlace(),, +"Use ""electrostatic force equations"" to perform global placement (don't call this function if ""gpl.Replace.doIncrementalPlace()"" is called)",gpl.Replace.doNesterovPlace(,int(thread),int +Get the macro placer,openroad.Design.getMacroPlacer(),,mpl.MacroPlacer +"Run macro placement and push all macros to the design boundary, must be called after global placement",mpl.MacroPlacer.placeMacrosCornerMaxWl(),, +"Run macro placement and place all macros together, must be called after global placement",mpl.MacroPlacer.placeMacrosCornerMinWL(),, +Snap the macro to a layer,mpl.MacroPlacer.setSnapLayer(,odb.dbTechLayer, +Set the fence region as a user defined area in microns,mpl.MacroPlacer.setFenceRegion(,"float(lx), doubl(ly), float(ux), float(uy)", +Set the channel width between macros,mpl.MacroPlacer.setChannel(,"float(channel_x), float(channel_y)", +Set the halo around macros,mpl.MacroPlacer.setHalo(,"float(halo_x), float(halo_y)", +Get the openroad db,openroad.get_db(),,odb.dbDatabase +Getting openroad.Tech object via openroad.Design object. Similar to openroad.Design.getTech(),openroad.get_db_tech(),,odb.dbTech +Similar to openroad.Design.getBlock,openroad.get_db_block(),,odb.dbBlock +"Get the detailed placer, or called as legalizer",openroad.Design.getOpendp(),,dpl.Opendp +"Perform legalization, max_displacment is in sites. use zero for defaults.",dpl.Opendp.detailedPlacement(,"int(max_displacement_x), int(max_displacement_y), str(report_file_name), bool(disallow_one_site_gaps)", +Get legalization report,dpl.Opendp.reportLegalizationStats(),, +Check legalization result,dpl.Opendp.checkPlacement(,"bool(verbose), bool(disallow_one_site_gaps), str(report_file_name)", +"Place filler cells after legalization, prefix is the naming pattern of the filler cells",dpl.Opendp.fillerPlacement(,"list(odn.dbMaster), str(prefix)", +Remove filler cells,dpl.Opendp.removeFillers(),, +"Propagate the clock signal, openroad.Design.evalTclString(“create_clock -period 20 [get_ports clk] -name core_clock”) must be celled before this.","openroad.Design.evalTclString(""set_propagated_clock [core_clock]"")",, +Set the unit resistance value and unit capacitance value of the clock net,"openroad.Design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"")",, +Set the unit resistance value and unit capacitance value of regular signal net,"openroad.Design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"")",, +Get the module to perform CTS (clock tree synthesis),openroad.Design.getTritonCts(),,cts.TritonCTS +Run CTS (clock tree synthesis),cts.TritonCTS.runTritonCts(,, +Report the CTS result,cts.TritonCTS.reportCtsMetrics(,, +Get the parameter seeting of the CTS module,cts.TritonCTS.getParms(,,cts.CtsOptions +Get the character setting of the CTS module,cts.TritonCTS.getCharacterization(,,cts.TechChar +"Set the clock net by the name, return 0 if complete normally, return 1 if cannot find the clock net with the name",cts.TritonCTS.setClockNets(,str(name), +Set the available clock buffer library cells with he name,cts.TritonCTS.setBufferList(,str(buffers), +Set the rooting clock buffer (starting point) with the name,cts.TritonCTS.setRootBuffer(,str(buffers), +Set the sinking clock buffer (end point) with the name,cts.TritonCTS.setSinkBuffer(,str(buffers), +Set the reference unit for sgmenting the wire,cts.CtsOptions.setWireSegmentUnit(,, +"Get the PDN (power grid, or called power delivery network) generator",openroad.Design.getPdnGen(,,pdn.PdnGen +Get the report of current PDN generation,pdn.PdnGen.report(,, +Get all voltage domain of the design,pdn.PdnGen.getDomains(,,list(pdn.VoltageDomain) +Find the voltage domain with the name of the domain,pdn.PdnGen.findDoamin(,str(name),pdn.VoltageDomain +"Set the voltage domain of the design core, power means the ower net, ground means the ground net",pdn.PdnGen.setCoreDomain(,"odb.dbNet(power), odb.dbNet(switched_power), odb.dbNet(ground), list(odb.dbNet)", +"Build the PDN, if ""trim"" is True, then will clean up some vias and trim the shape of smoe wires. If ""trim"" is set to False, then the PDN will remain the same",pdn.PdnGen.buildGrids(,bool(trim), +Find the high level PDN grid with the name,pdn.PdnGen.findGrid(,str(name), +"Create the high level PDN grid for the macro. ""domain"" is the voltage domain. ""name"" will be the name of this PDN grid. ""starts_with"" can be one of ""pdn.GRID, pdn.POWER, or pdn.GROUND"". ""inst"" is the target macro. ""halo"" is the halo set around the macro. ""pg_pins_to_boundary"" is set to True if the VDD and VSS pins of the macro is set to be around the macro, is is set to False, then VDD and VSS pins will appear within the macro block.",pdn.PdnGen.makeInstanceGrid(,"pdn.VoltageDomain(domain), str(name), pdn.StartsWith(starts_with), odb.dbInst(inst), list(int(halo)), bool(pg_pins_to_boundary), bool(default_grid), list(odb.dbTechLayer(generate_obstructions)), bool(is_bump)", +"Create the PDN ring around the design or the macro. ""grid"" is the high level PDN grid. ""layer0"" and ""layer1"" are the two layers to place the metal stripes of the PDN ring. ""width0"" and ""spacing0"" are the settings of ""layer0"". ""width1"" and ""spacing1"" are the two settings of ""layer1"". ""starts_with"" can be one of ""pdn.GRID, pdn.POWER, or pdn.GROUND"". ""offset"" is the offset setting of the PDN ring. ""pad_offset"" is the offset of padding of the PDN ring. ""extend"" is set to False then the PDN ring will remain the same, if set to True, then it will extend to the boundary. ""pad_pin_layers"" is a list of layers that will connect to pad. ""nets"" can be an empty list.",pdn.PdnGen.makeRing(,"pdn.Grid(grid), odb.dbTechLayer(layer0), int(width0),int(spacing0), odb.dbTechLayer(layer1), int(width1), int(spacing1), pdn.StartsWith(starts_with), list(int(offset)), list(int(pad_offset)), bool(extend), list(odb.dbTechLayer(pad_pin_layers), list(odb.dbNet(nets)", +"Create the PDN stripes at the lowest metal layer and following the pin pattern of the cells. ""extend"" can be either of ""pdn.CORE, pdn.RINGS, pdn.BOUNDARY, or pdn. FIXED"". ""layer"" is the metal layer place the PDN stripes. ""width"" specifies the metal stripe width. ""grid"" is the high level PDN grid.",pdn.PdnGen.makeFollowpin(,"pdn.Grid(grid), odb.dbTechLayer(layer), int(width), pdn.ExtensionMode(extend)", +"Create the PDN stripes generating pattern. ""grid"" is the high level PDN grid. ""layer"" specifies the metal layer. ""starts_with"" can be one of ""pdn.GRID, pdn.POWER, or pdn.GROUND"". ""extend"" can be either of ""pdn.CORE, pdn.RINGS, pdn.BOUNDARY, or pdn. FIXED"". The rest are the settings of the physical dimension of the metal stripes.",pdn.PdnGen.makeStrap(,"pdn.Grid(grid), odb.dbTechLayer(layer), int(width), int(spacing), int(pitch), int(offset), int(number_of_straps), bool(snap), pdn.StartsWith(starts_with), pdn.ExtensionMode(extend), list(odb.dbNet(nets))", +"Connect the stripes between two metal layers (creating vias). ""grid"" is the high level PDN grid. ""layer0"" and ""layer1"" specify the two metal layers. ""cut_pitch_x"" and ""cut_pitch_y"" specify the cut via generating pattern. ""vias"" is a list of vis generating rules defined in the technology file. ""max_rows"" and ""max_columns"" are the settings of the numbers of rows and columns. The key and value of ""dict()"" are odb.dbTechLayer and int. ""dont_use_vias"" is the name of the name of the vis generating rule you do not want to use.",pdn.PdnGen.makeConnect(,"pdn.Grid(grid), odb.dbTechLayer(layer0), odb.dbTechLayer(layer1), int(cut_pitch_x), int(cut_pitch_y), list(odb.dbTechViaGenerateRule(vias)), list(odb.dbTechVia(techvias), int(max_rows), int(max_columns), list(odb.dbTechLayer(ongrid)), dict(), str(dont_use_vias)", +Rip up the selected VDD/VSS net,pdn.PdnGen.ripUp(,(odb.dbNet net), +Check the PDN setup at the end of all pattern are defined,pdn.PdnGen.checkSetup(,, +"Write the PDN generation result to OpenROAD database. Usually set ""add_pins"" to True. ""report_file"" specifies the name of the report file.",pdn.PdnGen.writeToDb(,"bool(add_pins), str(report_file)", +Get the PDN analysis tool,openroad.Design.getPDNSim(),, +Specifies the target VDD/VSS net,psm.PDNSim.setNet(,odb.dbNet(net), +"Analyze the PDN, if set all files to enpty strings and set ""enable_em"" to False, PDNSim will use the default setting.",psm.PDNSim.analyzePowerGrid(,"str(voltage_file), bool(enable_em), str(em_file), str(error_file)", +"Perform IR drop analysis, ""layer"" specifies the layer.",psm.PDNSim.getIRDropForLayer(,odb.dbTechLayer(layer), +Set the corner information for the PDN analysis tool.,"openroad.Design.evalTclString(f""psm::set_corner [sta::cmd_corner]"")",, +Get the global router.,openroad.Design.getGlobalRouter(),,grt.GlobalRouter +Set the lowest routing layer,grt.GlobalRouter.setMinRoutingLayer(,int(min_layer), +Set the highest routing layer,grt.GlobalRouter.setMaxRoutingLayer(,int(max_layer), +Set the lowest routing layer for clock net,grt.GlobalRouter.setMinLayerForClock(,int(min_layer), +Set the highest routing layer for clock net,grt.GlobalRouter.setMaxLayerForClock(,int(max_layer), +Set the iteration to run if facing overflow in some gcells,grt.GlobalRouter.setOverflowIterations(,int(iterations), +"Run global routing, all default values are False.",grt.GlobalRouter.globalRoute(,"bool(save_guides), bool(start_incremental), bool(end_incremental)", +Get the detailed router,openroad.Design.getTritonRoute(),,drt.TritonRoute +Run detailed routing.,drt.TritonRoute.main(),, +Get the amount of DRVs,drt.getNumDRVs(),,int +Get the parameter settings of the detailed router.,drt.ParamStruct(),,drt.ParamStruct +Number of iteraion of detailed routing. Assign an integer to this variable,drt.ParamStruct.drouteEndIter(),, +Assign boolean to this variable to enable via generating during detailed routing,drt.ParamStruct.enableViaGen(),, +Find the instance using the name of that instance,odb.dbBlock.findInst(,str(name),odb.dbInst +Get a list of all nets,odb.dbBlock.getNets(),,list(odb.dbNet) +Get a list of all I/O ports,odb.dbBlock.getBTerms(),,list(odb.dbBTerm) +Find the I/O port using the name of that I/O port,odb.dbBlock.findBTerm(,str(name),odb.dbBTerm +Get a list of all pins,odb.dbBlock.getITerms(),,list(odb.dbITerm) +Find the pin using the name of that pin,odb.dbBlock.findITerm(,str(name),odb.dbITerm +Get a list of all instances,odb.dbBlock.getInsts(),,list(odb.dbInst) +Get db unit per micron (um),odb.dbBlock.getDbUnitsPerMicron(),,int +Get the core rectangle,odb.dbBlock.getCoreArea(),,odb.Rect +Get a list of all rows in the design,odb.dbBlock.getRows(),,list(odb.dbRow) +Get the site used in this row,odb.dbRow.getSite(),,odb.dbSite +Get the bottom left x location of this rectangle,odb.Rect.xMin(),,int +Get the bottom left y location of this rectangle,odb.Rect.yMin(),,int +Get the top right x location of this rectangle,odb.Rect.xMax(),,int +Get the top right y location of this rectangle,odb.Rect.yMax(),,int +Connect pins with nets. odb.dbBlock.addGlobalConnect should be executed before calling this function,odb.dbBlock.globalConnect(),, +"Given the pattern of the instance names, connect the net to the pins of instances that match the pin pattern",odb.dbBlock.addGlobalConnect(,"odb.dbRegion(region), str(instPattern), str(pinPattern), odb.dbNet(net), bool(do_connect)", +Getting openroad.Tech object via openroad.odb.dbBlock object. Similar to openroad.Design.getTech(),odb.dbBlock.getTech(),,odb.dbTech +"Return True if the net is marked as selected, return False if the net is not marked as selected.",odb.dbNet.isSelect(),,bool +Get the name of the net,odb.dbNet.getName(),,str +"Set the wire type of the net. Input can only be one of the followings: (""NONE"", ""COVER"", ""FIXED"", ""ROUTED"", ""SHIELD"", “NOSHIELD"")",odb.dbNet.setWireType(,str, +"Get the odb.dbWireType object in string. Return value can be one of the followings: (""NONE"", ""COVER"", ""FIXED"", ""ROUTED"", ""SHIELD"", ""NOSHIELD"")",odb.dbNet.getWireType(,,str +Get the total coupling capacitance of the net,odb.dbNet.getTotalCouplingCap(),,float +Get the total capacitance of the net,odb.dbNet.getTotalCapacitance(),,float +Get the total resistance of the net,odb.dbNet.getTotalResistance(),,float +Get all pins of the net,odb.dbNet.getITerms(),,list(odb.dbITerm) +Get all pins of the instance,odb.dbInst.getITerms(),,list(odb.dbITerm) +Get the name of the instance,odb.dbInst.getName(),,str +Get the x y location as a odb.Point object of the instance. Similar to odb.dbInst.getLocation(),odb.dbInst.getOrigin(),,odb.Point +Get the x location of the odb.Point object,odb.Point.getX(),,int +Get the y location of the odb.Point object,odb.Point.getY(),,int +Set the x y location of the instance. Similar to odb.dbInst.setLocation(),odb.dbInst.setOrigin(,"int(x), int(y)", +Get the x and y location as a odb.Point object of the instance. Similar to odb.dbInst.getOrigin(),odb.dbInst.getLocation(),,odb.Point +Set the x and y location of the instance. Similar to odb.dbInst.setOrigin(),odb.dbInst.setLocation(,"int(x), int(y)", +"Get the placement status of the instance. Status can only be one of the followings: (""NONE"", ""UNPLACED"", ""SUGGESTED"", ""PLACED"", ""LOCKED"", ""FIRM"", “COVER"")",odb.dbInst.getPlacementStatus(),,str +"Set the placement status of the instance. Status can only be one of the followings: (""NONE"", ""UNPLACED"", ""SUGGESTED"", ""PLACED"", ""LOCKED"", ""FIRM"", “COVER"")",odb.dbInst.setPlacementStatus(,str, +"Get the rotation (orientation) as a string of the instance. Orient can only be one of the followings: (""R0"", ""R90"", ""R180"", ""R270"", ""MY"", ""MYR90"", ""MX"", “MXR90"")",odb.dbInst.getOrient(),,str +"Set the rotation (orientation) of the instance. Orient can only be one of the followings: (""R0"", ""R90"", ""R180"", ""R270"", ""MY"", ""MYR90"", ""MX"", “MXR90"")",odb.dbInst.setOrient(,str, +Get the dbTransform object of the instance.,odb.dbInst.getTransform(),,odb.dbTransform +Set the dbTransform object of the instance.,odb.dbInst.setTransform(,odb.dbTransform(transform), +"Get the orientation (rotation) of the transform object, odb.dbInst.getTransform() function must be called before calling this function.",odb.dbTransform.getOrient(),,odb.dbOrientType +"Get the x and y location of the transform object, odb.dbInst.getTransform() function must be called before calling this function.",odb.dbTransform.getOffset(),,odb.Point +"Update the orientation (rotation) of the transform object, odb.dbInst.getTransform() function must be called before calling this function.",odb.dbTransform.setOrient(,str, +"Update the x and y location of the transform object, odb.dbInst.getTransform() function must be called before calling this function.",odb.dbTransform.setOffset(,odb.Point(point), +"Update the x and y location and the orientation (rotation) of the transform object, odb.dbInst.getTransform() function must be called before calling this function.",odb.dbTransform.setTransform(,"str, odb.Point", +Invert the x and y location and the rotation (orientation) of the transform,odb.dbTransform.invert(),, +Set the x and y location of the point object,odb.Point(,"int(x), int(y)",odb.Point +"v=True to set the instance as a ""do not touch” or “don’t touch” type instance. Use v=False to reset the ""do not touch"" setting.",odb.dbInst.setDoNotTouch(,bool(v), +"Return True if the instance is set as ""do not touch"" instance, return False if the instance is not set as ""do not touch"" instance",odb.dbInst.isDoNotTouch(),,bool +Return True if the instance is placed.,odb.dbInst.isPlaced(),,bool +Get the net connected to this pin,odb.dbITerm.getNet(),,odb.dbNet +Return True if the pin is an output pin of the instance. Return False if the pin is not an output pin of the instance.,odb.dbITerm.isOutputSignal(),,bool +Return True if the pin is an input pin of the instance. Return False if the pin is not an input pin of the instance.,odb.dbITerm.isInputSignal(),,bool +"Get the signal type of the net. Return ""POWER"" if the net is a power (VDD) net. Return ""GROUND"" is the net is a ground (VSS) net.",odb.dbNet.getSigType(),,str +"Set the signal type of the net. Set type to ""POWER"" if the net is a power (VDD) net. Set type to ""GROUND"" is the net is a ground (VSS) net.",odb.dbNet.setSigType(,str(type), +Get the cut layer class rule of the technology layer,odb.dbTechLayer.getTechLayerCutClassRules(,,list(odb.dbTechLayerCutClassRule) +Upsize or downsize the instance with the input “master” library cell,odb.dbInst.swapMaster(,odb.dbMaster(master), +Use name to find the master cell (library cell). Return None if the name does not match any master cell.,odb.dbDatabase.findMaster(,str(name),odb.dbMaster +Create a clock signal at the clk_i port with a period of 50 ps and name it core_clk.,openroad.Design.evalTclString(“create_clock -period 50 [get_ports clk_i] -name core_clock”),, +"Return True if the net’s disconnected flag is set to True, which typically means the net is disconnected from all pins. Return False if the flag is set to False, indicating that the net has connections with pins.",odb.dbNet.isDisconnected(),,Bool +Print opcodes and data of its wire,odb.dbNet.printWire(),, +"Return True if the master is a filler cell, return False if the master is not a filler cell.",odb.dbMaster.isFiller(),,bool \ No newline at end of file diff --git a/flow-Agent/rag_data/RAGCodePiece.csv b/flow-Agent/rag_data/RAGCodePiece.csv new file mode 100644 index 0000000..fa454ad --- /dev/null +++ b/flow-Agent/rag_data/RAGCodePiece.csv @@ -0,0 +1,658 @@ +Description:,Code Piece: +Template of reading .lib (liberty) files,"from openroad import Tech +from pathlib import Path + +# Initialize OpenROAD objects and read technology files +tech = Tech() +# Set paths to library and design files +libDir = Path(""../Design/nangate45/lib"") + +# Read all liberty file from the library directories +libFiles = libDir.glob(""*.lib"") + +# Load liberty timing libraries +for libFile in libFiles: + tech.readLiberty(libFile.as_posix())" +Template of reading .lef files,"from openroad import Tech +from pathlib import Path + +# Initialize OpenROAD objects and read technology files +tech = Tech() +# Set paths to library and design files +lefDir = Path(""../Design/nangate45/lef"") +techlefDir = Path(""../Design/nangate45/lef"") + +# Read all LEF files from the library directories +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') + +# Load technology and cell LEF files +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix())" +Template of reading technology files,"from openroad import Tech +from pathlib import Path + +# Initialize OpenROAD objects and read technology files +tech = Tech() +# Set paths to library and design files +techlefDir = Path(""../Design/nangate45/lef"") + +# Read all tech led files from the library directories +techLefFiles = lefDir.glob(""*.tech.lef"") + +# Load technology and cell LEF files +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix())" +Template of reading verilog files (reading netlist file),"from openroad import Tech, Design +from pathlib import Path + +# Initialize OpenROAD objects and read technology files +tech = Tech() +# Set paths to library and design files +libDir = Path(""../Design/nangate45/lib"") +lefDir = Path(""../Design/nangate45/lef"") +techlefDir = Path(""../Design/nangate45/lef"") +designDir = Path(""../Design/"") + +design_name = ""1_synth"" +design_top_module_name = ""gcd"" + +# Read all liberty (.lib) and LEF files from the library directories +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') + +# Load liberty timing libraries +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +# Load technology and cell LEF files +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) + +# Create design and read Verilog netlist +design = Design(tech) +verilogFile = designDir/str(design_name + "".v"") +design.readVerilog(verilogFile.as_posix()) +design.link(design_top_module_name)" +Template of reading OpenROAD design file in .odb format,"from openroad import Tech, Design + +# Initialize OpenROAD objects and read technology files +tech = Tech() +# Set paths to library and design files +libDir = Path(""../Design/nangate45/lib"") +lefDir = Path(""../Design/nangate45/lef"") +techlefDir = Path(""../Design/nangate45/lef"") +designDir = Path(""../Design/"") + +design_name = ""1_synth"" +design_top_module_name = ""gcd"" + +# Read all liberty (.lib) and LEF files from the library directories +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') + +# Load liberty timing libraries +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +# Load technology and cell LEF files +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) + +# Create design and read ode file +design = Design(tech) +odbFile = designDir/str(design_name + "".odb"") +design.readDb(odbFile.as_posix())" +Template of reading DEF (.def) files,"from openroad import Tech, Design + +# Initialize OpenROAD objects and read technology files +tech = Tech() +# Set paths to library and design files +libDir = Path(""../Design/nangate45/lib"") +lefDir = Path(""../Design/nangate45/lef"") +techlefDir = Path(""../Design/nangate45/lef"") +designDir = Path(""../Design/"") + +design_name = ""1_synth"" +design_top_module_name = ""gcd"" + +# Read all liberty (.lib) and LEF files from the library directories +libFiles = libDir.glob(""*.lib"") +techLefFiles = lefDir.glob(""*.tech.lef"") +lefFiles = lefDir.glob('*.lef') + +# Load liberty timing libraries +for libFile in libFiles: + tech.readLiberty(libFile.as_posix()) +# Load technology and cell LEF files +for techLefFile in techLefFiles: + tech.readLef(techLefFile.as_posix()) +for lefFile in lefFiles: + tech.readLef(lefFile.as_posix()) + +# Create design and read def file +design = Design(tech) +defFile = designDir/str(design_name + "".def"") +design.readDef(defFile.as_posix())" +Template of creating and propagate the clock signal,"clock_period = 200 +port_name = ""port_name"" +clock_name = ""clock_name"" +# Create clock signal +design.evalTclString(""create_clock -period %s [get_ports %s] -name %s""%(clock_period, port_name, clock_name)) +# Propagate the clock signal +design.evalTclString(""set_propagated_clock [all_clocks]"")" +Template of running floorplanning with utilization rate (hight/width),"# Initialize floorplan with core and die area +floorplan = design.getFloorplan() +# Set die area to 60um x 50um +# Initialize floorplan with FreePDK45 site +site = floorplan.findSite(""FreePDK45_38x28_10R_NP_162NW_34O"") +utilization = 0.5 +aspect_ratio = 1.0 +leftSpace = design.micronToDBU(10) +rightSpace = design.micronToDBU(10) +topSpace = design.micronToDBU(10) +bottomSpace = design.micronToDBU(10) +floorplan.initFloorplan(utilization, aspect_ratio, bottomSpace, topSpace, leftSpace, rightSpace, site) +floorplan.makeTracks()" +Template of running floorplanning with specific die and core area,"import odb +# Initialize floorplan with core and die area +floorplan = design.getFloorplan() +# Set die area to 60um x 50um +die_area = odb.Rect(design.micronToDBU(0), design.micronToDBU(0), + design.micronToDBU(60), design.micronToDBU(50)) +# Set core area to 50um x 40um with 5um margins +core_area = odb.Rect(design.micronToDBU(5), design.micronToDBU(5), + design.micronToDBU(55), design.micronToDBU(45)) +# Initialize floorplan with FreePDK45 site +site = floorplan.findSite(""FreePDK45_38x28_10R_NP_162NW_34O"") +floorplan.initFloorplan(die_area, core_area, site) +floorplan.makeTracks()" +Template of placing I/O pins (ports),"# Configure and run I/O pin placement +params = design.getIOPlacer().getParameters() +params.setRandSeed(42) +params.setMinDistanceInTracks(False) +params.setMinDistance(design.micronToDBU(0)) +params.setCornerAvoidance(design.micronToDBU(0)) +# Place I/O pins on metal8 (horizontal) and metal9 (vertical) layers +design.getIOPlacer().addHorLayer(design.getTech().getDB().getTech().findLayer(""metal8"")) +design.getIOPlacer().addVerLayer(design.getTech().getDB().getTech().findLayer(""metal9"")) +IOPlacer_random_mode = True +design.getIOPlacer().runAnnealing(IOPlacer_random_mode)" +Template of running global placement,"# Configure and run global placement +gpl = design.getReplace() +gpl.setTimingDrivenMode(False) +gpl.setRoutabilityDrivenMode(True) +gpl.setUniformTargetDensityMode(True) +# Limit initial placement iterations and set density penalty +gpl.setInitialPlaceMaxIter(10) +gpl.setInitDensityPenalityFactor(0.05) +gpl.doInitialPlace(threads = 4) +gpl.doNesterovPlace(threads = 4) +gpl.reset()" +Template of running macro placer,"# Place macro blocks if present +macros = [inst for inst in design.getBlock().getInsts() if inst.getMaster().isBlock()] +if len(macros) > 0: + mpl = design.getMacroPlacer() + block = design.getBlock() + core = block.getCoreArea() + mpl.place( + num_threads = 64, + max_num_macro = len(macros)//8, + min_num_macro = 0, + max_num_inst = 0, + min_num_inst = 0, + tolerance = 0.1, + max_num_level = 2, + coarsening_ratio = 10.0, + large_net_threshold = 50, + signature_net_threshold = 50, + halo_width = 2.0, + halo_height = 2.0, + fence_lx = block.dbuToMicrons(core.xMin()), + fence_ly = block.dbuToMicrons(core.yMin()), + fence_ux = block.dbuToMicrons(core.xMax()), + fence_uy = block.dbuToMicrons(core.yMax()), + area_weight = 0.1, + outline_weight = 100.0, + wirelength_weight = 100.0, + guidance_weight = 10.0, + fence_weight = 10.0, + boundary_weight = 50.0, + notch_weight = 10.0, + macro_blockage_weight = 10.0, + pin_access_th = 0.0, + target_util = 0.25, + target_dead_space = 0.05, + min_ar = 0.33, + snap_layer = 4, + bus_planning_flag = False, + report_directory = """" + )" +Template of running detailed placement,"# Run initial detailed placement +site = design.getBlock().getRows()[0].getSite() +# Allow 1um x-displacement and 3um y-displacement +max_disp_x = int(design.micronToDBU(1)) +max_disp_y = int(design.micronToDBU(3)) +# Remove filler cells to be able to move the cells +design.getOpendp().removeFillers() +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False)" +Template of running CTS (clock tree synthesis),"# Configure and run clock tree synthesis +design.evalTclString(""set_propagated_clock [get_clocks {core_clock}]"") +# Set RC values for clock and signal nets +design.evalTclString(""set_wire_rc -clock -resistance 0.03574 -capacitance 0.07516"") +design.evalTclString(""set_wire_rc -signal -resistance 0.03574 -capacitance 0.07516"") +cts = design.getTritonCts() +parms = cts.getParms() +parms.setWireSegmentUnit(20) +# Configure clock buffers +cts.setBufferList(""BUF_X2"") +cts.setRootBuffer(""BUF_X2"") +cts.setSinkBuffer(""BUF_X2"") +cts.runTritonCts() + +# Run final detailed placement +site = design.getBlock().getRows()[0].getSite() +max_disp_x = int(design.micronToDBU(1) / site.getWidth()) +max_disp_y = int(design.micronToDBU(3) / site.getHeight()) +design.getOpendp().detailedPlacement(max_disp_x, max_disp_y, """", False)" +Template of placing filler cells,"import openroad as ord +# Insert filler cells +db = ord.get_db() +filler_masters = list() +# filler cells' naming convention +filler_cells_prefix = ""FILLCELL_"" +for lib in db.getLibs(): + for master in lib.getMasters(): + if master.getType() == ""CORE_SPACER"": + filler_masters.append(master) +if len(filler_masters) == 0: + print(""no filler cells in library!"") +else: + design.getOpendp().fillerPlacement(filler_masters = filler_masters, + prefix = filler_cells_prefix, + verbose = False)" +Template of performing power planning (creating power delivery network (PDN)) with power rings,"import pdn, odb +# Configure power delivery network +# Set up global power/ground connections +for net in design.getBlock().getNets(): + if net.getSigType() == ""POWER"" or net.getSigType() == ""GROUND"": + net.setSpecial() +VDD_net = design.getBlock().findNet(""VDD"") +VSS_net = design.getBlock().findNet(""VSS"") +switched_power = None +secondary = list() +# Create VDD/VSS nets if they don't exist +if VDD_net == None: + VDD_net = odb.dbNet_create(design.getBlock(), ""VDD"") + VDD_net.setSpecial() + VDD_net.setSigType(""POWER"") +if VSS_net == None: + VSS_net = odb.dbNet_create(design.getBlock(), ""VSS"") + VSS_net.setSpecial() + VSS_net.setSigType(""GROUND"") + +# Connect power pins to global nets +design.getBlock().addGlobalConnect(region = None, + instPattern = "".*"", + pinPattern = ""^VDD$"", + net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, + instPattern = "".*"", + pinPattern = ""^VDDPE$"", + net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, + instPattern = "".*"", + pinPattern = ""^VDDCE$"", + net = VDD_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, + instPattern = "".*"", + pinPattern = ""^VSS$"", + net = VSS_net, + do_connect = True) +design.getBlock().addGlobalConnect(region = None, + instPattern = "".*"", + pinPattern = ""^VSSE$"", + net = VSS_net, + do_connect = True) +design.getBlock().globalConnect() + +# Configure power domains +pdngen = design.getPdnGen() +pdngen.setCoreDomain(power = VDD_net, + switched_power = switched_power, + ground = VSS_net, + secondary = secondary) + +# Configure power ring dimensions +core_ring_width = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_spacing = [design.micronToDBU(2), design.micronToDBU(2)] +core_ring_core_offset = [design.micronToDBU(0) for i in range(4)] +core_ring_pad_offset = [design.micronToDBU(0) for i in range(4)] +pdn_cut_pitch = [design.micronToDBU(0) for i in range(2)] + +# Get routing layers for power ring connections +ring_connect_to_pad_layers = list() +for layer in design.getTech().getDB().getTech().getLayers(): + if layer.getType() == ""ROUTING"": + ring_connect_to_pad_layers.append(layer) + +# Create power grid for standard cells +domains = [pdngen.findDomain(""Core"")] +halo = [design.micronToDBU(0) for i in range(4)] +for domain in domains: + pdngen.makeCoreGrid(domain = domain, + name = ""top"", + starts_with = pdn.GROUND, + pin_layers = [], + generate_obstructions = [], + powercell = None, + powercontrol = None, + powercontrolnetwork = ""STAR"") + +# Get metal layers for power grid +m1 = design.getTech().getDB().getTech().findLayer(""metal1"") +m4 = design.getTech().getDB().getTech().findLayer(""metal4"") +m7 = design.getTech().getDB().getTech().findLayer(""metal7"") +m8 = design.getTech().getDB().getTech().findLayer(""metal8"") + +grid = pdngen.findGrid(""top"") +for g in grid: + # Create power rings around core area + pdngen.makeRing(grid = g, + layer0 = m7, + width0 = core_ring_width[0], + spacing0 = core_ring_spacing[0], + layer1 = m8, + width1 = core_ring_width[0], + spacing1 = core_ring_spacing[0], + starts_with = pdn.GRID, + offset = core_ring_core_offset, + pad_offset = core_ring_pad_offset, + extend = False, + pad_pin_layers = ring_connect_to_pad_layers, + nets = [], + allow_out_of_die = True) + + # Create horizontal power straps on metal1 for standard cell connections + pdngen.makeFollowpin(grid = g, + layer = m1, + width = design.micronToDBU(0.07), + extend = pdn.CORE) + + # Create vertical power straps on metal4 and metal7 + pdngen.makeStrap(grid = g, + layer = m4, + width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), + pitch = design.micronToDBU(6), + offset = design.micronToDBU(0), + number_of_straps = 0, + snap = False, + starts_with = pdn.GRID, + extend = pdn.CORE, + nets = []) + pdngen.makeStrap(grid = g, + layer = m7, + width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), + pitch = design.micronToDBU(10.8), + offset = design.micronToDBU(0), + number_of_straps = 0, + snap = False, + starts_with = pdn.GRID, + extend = pdn.RINGS, + nets = []) + pdngen.makeStrap(grid = g, + layer = m8, + width = design.micronToDBU(1.4), + spacing = design.micronToDBU(1.4), + pitch = design.micronToDBU(10.8), + offset = design.micronToDBU(0), + number_of_straps = 0, + snap = False, + starts_with = pdn.GRID, + extend = pdn.BOUNDARY, + nets = []) + + # Create via connections between power grid layers + pdngen.makeConnect(grid = g, + layer0 = m1, + layer1 = m4, + cut_pitch_x = pdn_cut_pitch[0], + cut_pitch_y = pdn_cut_pitch[1], + vias = [], + techvias = [], + max_rows = 0, + max_columns = 0, + ongrid = [], + split_cuts = dict(), + dont_use_vias = """") + pdngen.makeConnect(grid = g, + layer0 = m4, + layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], + cut_pitch_y = pdn_cut_pitch[1], + vias = [], + techvias = [], + max_rows = 0, + max_columns = 0, + ongrid = [], + split_cuts = dict(), + dont_use_vias = """") + pdngen.makeConnect(grid = g, + layer0 = m7, + layer1 = m8, + cut_pitch_x = pdn_cut_pitch[0], + cut_pitch_y = pdn_cut_pitch[1], + vias = [], + techvias = [], + max_rows = 0, + max_columns = 0, + ongrid = [], + split_cuts = dict(), + dont_use_vias = """") + +# Verify and build power grid +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes()" +Template of creating power distribute networks (PDN) for macros,"import pdn +pdngen = design.getPdnGen() +domains = [pdngen.findDomain(""Core"")] +# Create power grid for macro blocks +macros = [inst for inst in design.getBlock().getInsts() if inst.getMaster().isBlock()] +m5 = design.getTech().getDB().getTech().findLayer(""metal5"") +m6 = design.getTech().getDB().getTech().findLayer(""metal6"") +for i in range(len(macros)): + # Create power grid for each macro + for domain in domains: + pdngen.makeInstanceGrid(domain = domain, + name = ""CORE_macro_grid_"" + str(i), + starts_with = pdn.GROUND, + inst = macros[i], + halo = halo, + pg_pins_to_boundary = True, + default_grid = False, + generate_obstructions = [], + is_bump = False) + grid = pdngen.findGrid(""CORE_macro_grid_"" + str(i)) + for g in grid: + # Create power straps on metal5 and metal6 for macro connections + pdngen.makeStrap(grid = g, + layer = m5, + width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), + pitch = design.micronToDBU(6), + offset = design.micronToDBU(0), + number_of_straps = 0, + snap = True, + starts_with = pdn.GRID, + extend = pdn.CORE, + nets = []) + pdngen.makeStrap(grid = g, + layer = m6, + width = design.micronToDBU(1.2), + spacing = design.micronToDBU(1.2), + pitch = design.micronToDBU(6), + offset = design.micronToDBU(0), + number_of_straps = 0, + snap = True, + starts_with = pdn.GRID, + extend = pdn.CORE, + nets = []) + + # Create via connections between macro power grid layers + pdngen.makeConnect(grid = g, + layer0 = m4, + layer1 = m5, + cut_pitch_x = pdn_cut_pitch[0], + cut_pitch_y = pdn_cut_pitch[1], + vias = [], + techvias = [], + max_rows = 0, + max_columns = 0, + ongrid = [], + split_cuts = dict(), + dont_use_vias = """") + pdngen.makeConnect(grid = g, + layer0 = m5, + layer1 = m6, + cut_pitch_x = pdn_cut_pitch[0], + cut_pitch_y = pdn_cut_pitch[1], + vias = [], + techvias = [], + max_rows = 0, + max_columns = 0, + ongrid = [], + split_cuts = dict(), + dont_use_vias = """") + pdngen.makeConnect(grid = g, + layer0 = m6, + layer1 = m7, + cut_pitch_x = pdn_cut_pitch[0], + cut_pitch_y = pdn_cut_pitch[1], + vias = [], + techvias = [], + max_rows = 0, + max_columns = 0, + ongrid = [], + split_cuts = dict(), + dont_use_vias = """") + +# Verify and build power grid +pdngen.checkSetup() +pdngen.buildGrids(False) +pdngen.writeToDb(True, ) +pdngen.resetShapes()" +Template of performing IR (voltage) drop analysis for nodes on metal 1 grids,"import psm + +# Run static IR drop analysis +psm_obj = design.getPDNSim() +timing = Timing(design) +source_types = [psm.GeneratedSourceType_FULL, + psm.GeneratedSourceType_STRAPS, + psm.GeneratedSourceType_BUMPS] +# Analyze VDD power grid IR drop +psm_obj.analyzePowerGrid(net = design.getBlock().findNet(""VDD""), + enable_em = False, corner = timing.getCorners()[0], + use_prev_solution = False, + em_file = """", + error_file = """", + voltage_source_file = """", + voltage_file = """", + source_type = source_types[2])" +"Template of reporting internal power, switching power, and leakage power","# Report Power +design.evalTclString(""report_power"")" +Template of performing global routing,"# Configure and run global routing +# Set routing layer ranges for signal and clock nets +signal_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +signal_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() +clk_low_layer = design.getTech().getDB().getTech().findLayer(""metal1"").getRoutingLevel() +clk_high_layer = design.getTech().getDB().getTech().findLayer(""metal7"").getRoutingLevel() + +grt = design.getGlobalRouter() +grt.setMinRoutingLayer(signal_low_layer) +grt.setMaxRoutingLayer(signal_high_layer) +grt.setMinLayerForClock(clk_low_layer) +grt.setMaxLayerForClock(clk_high_layer) +grt.setAdjustment(0.5) +grt.setVerbose(True) +grt.globalRoute(True)" +Template of performing detailed routing,"import drt + +# Configure and run detailed routing +drter = design.getTritonRoute() +params = drt.ParamStruct() +params.outputMazeFile = """" +params.outputDrcFile = """" +params.outputCmapFile = """" +params.outputGuideCoverageFile = """" +params.dbProcessNode = """" +params.enableViaGen = True +params.drouteEndIter = 1 +params.viaInPinBottomLayer = """" +params.viaInPinTopLayer = """" +params.orSeed = -1 +params.orK = 0 +params.bottomRoutingLayer = ""metal1"" +params.topRoutingLayer = ""metal7"" +params.verbose = 1 +params.cleanPatches = True +params.doPa = True +params.singleStepDR = False +params.minAccessPoints = 1 +params.saveGuideUpdates = False +drter.setParams(params) +drter.main()" +Template function to horizontally flip the instance,"# This function is not provided by OpenROAD, you have to create this function. +def flipX(value): + if value == ""R0"": + return ""MX"" + elif value == ""R90"": + return ""MYR90"" + elif value == ""R180"": + return ""MY"" + elif value == ""R270"": + return ""MXR90"" + elif value == ""MY"": + return ""R180"" + elif value == ""MYR90"": + return ""R90"" + elif value == ""MX"": + return ""R0"" + elif value == ""MXR90"": + return ""R270""" +Template function to vertically flip the instance,"# This function is not provided by OpenROAD, you have to create this function. +def flipY(value): + if value == ""R0"": + return ""MY"" + elif value == ""R90"": + return ""MXR90"" + elif value == ""R180"": + return ""MX"" + elif value == ""R270"": + return ""MYR90"" + elif value == ""MY"": + return ""R0"" + elif value == ""MYR90"": + return ""R270"" + elif value == ""MX"": + return ""R180"" + elif value == ""MXR90"": + return ""R90""" +Template of getting the library cell (master cell) from the OpenROAD db,"# Get the database +db = ord.get_db() +# Define the new library cell name +new_mast_name = 'NOR_2X6' +# Check if the required library cell exists in the database +new_mast = db.findMaster(new_mast_name)" \ No newline at end of file diff --git a/flow-Agent/rag_data/RAGFLOWGUIDE.csv b/flow-Agent/rag_data/RAGFLOWGUIDE.csv new file mode 100644 index 0000000..d498d5b --- /dev/null +++ b/flow-Agent/rag_data/RAGFLOWGUIDE.csv @@ -0,0 +1,4044 @@ +FlowStage,ErrorMessage,LikelyCause,RecommendedFix,ExampleWrongCode +FILE,"[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) r",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) r",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) r",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) r",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'exportDef'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +TypeError: Design.writeDb() got an unexpected keyword argument 'overwrite'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'executeTclCommand'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) r",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) r",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) r",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) referenced +[WARNING ODB-0176] error: undefined layer (metal3) r",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'saveDef'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'saveDb'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'generateVerilog'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Tech' object has no attribute 'loadLiberty' +. Did you mean: 'readLiberty +'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[INFO ODB-0227] LEF file: ../Design/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias + + + +[INFO ODB-0227] LEF file: ../Design/nangate45/lef/fakeram45_64x21.lef, created 1 library cells +[INFO ODB-0227] LEF file: ../Design/nangate45/lef/fakeram45_256x32.lef, created 1 library ce",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[INFO ODB-0227] LEF file: ../Design/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias + + + +Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Tech' object has no attribute 'initializeLef'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 2, in +TypeError: Tech.readLiberty() got an unexpected keyword argument 'verbose'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'saveDesignDef'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'exportDb'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'runTclString' +. Did you mean: 'evalTclString'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Tech' object has no attribute 'importLiberty'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[INFO ODB-0227] LEF file: ../Design/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias + + + +Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Tech' object has no attribute 'loadLef' +. Did you mean: 'readLef'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[INFO ODB-0227] LEF file: ../Design/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias + + + +[INFO ODB-0227] LEF file: ../Design/nangate45/lef/fakeram45_64x21.lef, created 1 library cells +[INFO ODB-0227] LEF file: ../Design/nangate45/lef/fakeram45_256x32.lef, created 1 library ce",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[INFO ODB-0227] LEF file: ../Design/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias + + + +Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Tech' object has no attribute 'processLef'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'writeDefWithOptions'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'storeDatabase'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'exportVerilog'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Tech' object has no attribute 'addLiberty' +. Did you mean: 'readLiberty'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[INFO ODB-0227] LEF file: ../Design/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias + + + +[INFO ODB-0227] LEF file: ../Design/nangate45/lef/fakeram45_64x21.lef, created 1 library cells +[INFO ODB-0227] LEF file: ../Design/nangate45/lef/fakeram45_256x32.lef, created 1 library ce",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[INFO ODB-0227] LEF file: ../Design/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias + + + +[INFO ODB-0227] LEF file: ../Design/nangate45/lef/fakeram45_64x21.lef, created 1 library cells +[INFO ODB-0227] LEF file: ../Design/nangate45/lef/fakeram45_256x32.lef, created 1 library ce",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 2, in +TypeError: Tech.readLiberty() got an unexpected keyword argument 'verbose'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'saveDef'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'commitDb'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'executeVerilogCommand'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Tech' object has no attribute 'loadLef' +. Did you mean: 'readLef'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[INFO ODB-0227] LEF file: ../Design/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias + + + +[INFO ODB-0227] LEF file: ../Design/nangate45/lef/fakeram45_64x21.lef, created 1 library cells +[INFO ODB-0227] LEF file: ../Design/nangate45/lef/fakeram45_256x32.lef, created 1 library ce",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[INFO ODB-0227] LEF file: ../Design/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias + + + +[INFO ODB-0227] LEF file: ../Design/nangate45/lef/fakeram45_64x21.lef, created 1 library cells +[INFO ODB-0227] LEF file: ../Design/nangate45/lef/fakeram45_256x32.lef, created 1 library ce",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"[INFO ODB-0227] LEF file: ../Design/nangate45/lef/NangateOpenCellLibrary.tech.lef, created 22 layers, 27 vias + + + +Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Tech' object has no attribute 'loadLef' +. Did you mean: 'readLef'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'storeDef'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'saveDesign'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILE,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'executeVerilogCommand'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FLOORPLAN,"[WARNING IFP-0028] Core area lower left (5.000, 5.000) snapped to (5.130, 5.600). +[INFO IFP-0001] Added 28 rows of 262 site FreePDK45_38x28_10R_NP_162NW_34O. + +Traceback (most recent call last): + File """", line 1, in +AttributeError: 'InitFloorplan' object has no attribute 'createTrack",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FLOORPLAN,"Traceback (most recent call last): + File """", line 1, in +File ""ifp_py.py"", line 321, in initFloorplan +TypeError: Wrong number or type of arguments for overloaded function 'InitFloorplan_initFloorplan'. + Possible C/C++ prototypes are: + ifp::InitFloorplan::initFloorplan(double,doub",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FLOORPLAN,"[WARNING IFP-0028] Core area lower left (5.000, 5.000) snapped to (5.130, 5.600). +[INFO IFP-0001] Added 28 rows of 262 site FreePDK45_38x28_10R_NP_162NW_34O. + +Traceback (most recent call last): + File """", line 1, in +AttributeError: 'InitFloorplan' object has no attribute 'generateTra",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FLOORPLAN,"Traceback (most recent call last): + File """", line 1, in +File ""ifp_py.py"", line 321, in initFloorplan +TypeError: Wrong number or type of arguments for overloaded function 'InitFloorplan_initFloorplan'. + Possible C/C++ prototypes are: + ifp::InitFloorplan::initFloorplan(double,doub",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FLOORPLAN,"[WARNING IFP-0028] Core area lower left (5.000, 5.000) snapped to (5.130, 5.600). +[INFO IFP-0001] Added 28 rows of 262 site FreePDK45_38x28_10R_NP_162NW_34O. + +Traceback (most recent call last): + File """", line 1, in +AttributeError: 'InitFloorplan' object has no attribute 'setupTracks",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FLOORPLAN,"Traceback (most recent call last): + File """", line 1, in +File ""ifp_py.py"", line 321, in initFloorplan +TypeError: Wrong number or type of arguments for overloaded function 'InitFloorplan_initFloorplan'. + Possible C/C++ prototypes are: + ifp::InitFloorplan::initFloorplan(double,doub",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FLOORPLAN,"[WARNING IFP-0028] Core area lower left (5.000, 5.000) snapped to (5.130, 5.600). +[INFO IFP-0001] Added 28 rows of 262 site FreePDK45_38x28_10R_NP_162NW_34O. + +Traceback (most recent call last): + File """", line 1, in +AttributeError: 'InitFloorplan' object has no attribute 'makeTracksW",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FLOORPLAN,"Traceback (most recent call last): + File """", line 1, in +File ""ifp_py.py"", line 321, in initFloorplan +TypeError: Wrong number or type of arguments for overloaded function 'InitFloorplan_initFloorplan'. + Possible C/C++ prototypes are: + ifp::InitFloorplan::initFloorplan(double,doub",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FLOORPLAN,"[WARNING IFP-0028] Core area lower left (5.000, 5.000) snapped to (5.130, 5.600). +[INFO IFP-0001] Added 28 rows of 262 site FreePDK45_38x28_10R_NP_162NW_34O. + +Traceback (most recent call last): + File """", line 1, in +AttributeError: 'InitFloorplan' object has no attribute 'defineTrack",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FLOORPLAN,"[WARNING IFP-0028] Core area lower left (10.000, 10.000) snapped to (10.070, 11.200). +[INFO IFP-0001] Added 256 rows of 1897 site FreePDK45_38x28_10R_NP_162NW_34O. + +Traceback (most recent call last): + File """", line 1, in +AttributeError: 'InitFloorplan' object has no attribute 'estab",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FLOORPLAN,"[WARNING IFP-0028] Core area lower left (5.000, 5.000) snapped to (5.130, 5.600). +[INFO IFP-0001] Added 28 rows of 262 site FreePDK45_38x28_10R_NP_162NW_34O. + +Traceback (most recent call last): + File """", line 1, in +AttributeError: 'InitFloorplan' object has no attribute 'setupTracks",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FLOORPLAN,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'InitFloorplan' object has no attribute 'runFloorplan' +. Did you mean: 'initFloorplan'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'addHorizontalLayer'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'printConfig'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'obtainTopLayer'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Parameters' object has no attribute 'defineMinSpacing'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Parameters' object has no attribute 'configureHorizontalLength'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Parameters' object has no attribute 'configureVerticalLength'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'addVerticalLayer' +. Did you mean: 'addVerLayer'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'printConfig'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'fetchIOPlacer' +. Did you mean: 'getIOPlacer'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Parameters' object has no attribute 'configureMinDistance'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Parameters' object has no attribute 'setHorizontalLengthWithMode' +. Did you mean: 'setHorizontalLengthExtend'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Parameters' object has no attribute 'updateVerticalLength' +. Did you mean: 'getVerticalLength'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'executeAnnealing'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'printConfig'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'fetchTopLayer' +. Did you mean: 'getTopLayer +'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Parameters' object has no attribute 'setMinDistanceInTracksWithMode' +. Did you mean: 'setMinDistanceInTracks'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +TypeError: Parameters.setHorizontalLength() got an unexpected keyword argument 'mode'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Parameters' object has no attribute 'adjustVerticalLength' +. Did you mean: 'getVerticalLength'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'runAnnealingWithConfig' +. Did you mean: 'setAnnealingConfig'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'printConfig'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'retrieveIOPlacer'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Parameters' object has no attribute 'applyMinDistance' +. Did you mean: 'getMinDistance'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Parameters' object has no attribute 'updateHorizontalLength' +. Did you mean: 'getHorizontalLength'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Parameters' object has no attribute 'applyVerticalLength' +. Did you mean: 'getVerticalLength'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +TypeError: IOPlacer.runAnnealing() takes 2 positional arguments but 3 were given",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'showConfiguration'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'getUpperLayer' +. Did you mean: 'getTopLayer'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Parameters' object has no attribute 'setMinimumSpacing'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Parameters' object has no attribute 'setHorizontalLengthExtended' +. Did you mean: 'setHorizontalLengthExtend'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +TypeError: Parameters.setVerticalLength() takes 2 positional arguments but 3 were given",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'startSimulatedAnnealing'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'printConfig'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'IOPlacer' object has no attribute 'retrieveTopLayerInfo'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 2, in +TypeError: Parameters.setMinDistance() takes 2 positional arguments but 3 were given",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +TypeError: Parameters.setHorizontalLength() got an unexpected keyword argument 'scale'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IO,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Parameters' object has no attribute 'modifyVerticalLength' +. Did you mean: 'getVerticalLength'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +GPL,"[INFO GPL-0002] DBU: 2000 +[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um +[INFO GPL-0004] CoreBBox: ( 10.070 11.200 ) ( 56.430 56.000 ) um +[INFO GPL-0006] NumInstances: 503 +[INFO GPL-0007] NumPlaceInstances: 503 +[INFO GPL-0008] NumFixedInstances: 0 +[INFO GPL-0009] Nu",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +GPL,"[INFO GPL-0002] DBU: 2000 +[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um +[INFO GPL-0004] CoreBBox: ( 10.070 11.200 ) ( 56.430 56.000 ) um +[INFO GPL-0006] NumInstances: 503 +[INFO GPL-0007] NumPlaceInstances: 503 +[INFO GPL-0008] NumFixedInstances: 0 +[INFO GPL-0009] Nu",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +GPL,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Replace' object has no attribute 'executeInitialPlacement'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +GPL,"[INFO GPL-0002] DBU: 2000 +[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um +[INFO GPL-0004] CoreBBox: ( 10.070 11.200 ) ( 56.430 56.000 ) um +[INFO GPL-0006] NumInstances: 503 +[INFO GPL-0007] NumPlaceInstances: 503 +[INFO GPL-0008] NumFixedInstances: 0 +[INFO GPL-0009] Nu",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +GPL,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Replace' object has no attribute 'setBalancedTargetDensityMode' +. Did you mean: 'setUniformTargetDensityMode'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +GPL,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Replace' object has no attribute 'enableUniformDensitySetting'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +MPL,"Traceback (most recent call last): + File """", line 5, in +TypeError: MacroPlacer.placeMacro() got an unexpected keyword argument 'num_threads'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +MPL,"Traceback (most recent call last): + File """", line 5, in +TypeError: MacroPlacer.place() missing 1 required positional argument: 'max_num_macro'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +MPL,"Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Design' object has no attribute 'macroPlacer' +. Did you mean: 'getMacroPlacer'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +MPL,"Traceback (most recent call last): + File """", line 5, in +TypeError: MacroPlacer.place() missing 1 required positional argument: 'halo_height'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +MPL,"Traceback (most recent call last): + File """", line 5, in +File ""mpl_py.py"", line 238, in place +TypeError: in method 'MacroPlacer_place', argument 30 of type 'int'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +MPL,"Traceback (most recent call last): + File """", line 2, in +AttributeError: 'Design' object has no attribute 'getOpenROADMacroPlacer'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DPL,"Traceback (most recent call last): + File """", line 1, in +File ""dpl_py.py"", line 139, in detailedPlacement +TypeError: Opendp_detailedPlacement expected at most 5 arguments, got 6 +Additional information: +Wrong number or type of arguments for overloaded function 'Opendp_detailedPlacemen",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DPL,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Opendp' object has no attribute 'clearFillers'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DPL,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'dbRow' object has no attribute 'fetchSite' +. Did you mean: 'getSite'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DPL,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Opendp' object has no attribute 'clearFillerCells'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DPL,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Opendp' object has no attribute 'executePlacement' +. Did you mean: 'checkPlacement'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DPL,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Opendp' object has no attribute 'purgeFillers'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +CTS,"invalid command name ""make_clock""'",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +CTS,"Traceback (most recent call last): + +File """", line 1, in + +AttributeError +: +'TritonCTS' object has no attribute 'setBufferListWithType'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +CTS,"invalid command name ""initialize_clock""'",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +CTS,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'TritonCTS' object has no attribute 'assignBufferList' +. Did you mean: 'setBufferList'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +CTS,"wrong # args: should be ""define_clock_layer_range layers""'",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +CTS,"Traceback (most recent call last): + File """", line 1, in + +File ""dpl_py.py"", line 139, in detailedPlacement + +TypeError +: +Opendp_detailedPlacement expected at most 5 arguments, got 6 +Additional information: +Wrong number or type of arguments for overloaded function 'Opendp_detailedPlace",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +CTS,"invalid command name ""setup_clock""'",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +CTS,"Traceback (most recent call last): +File """", line 1, in + +AttributeError +: +'Opendp' object has no attribute 'advancedDetailedPlacement'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +CTS,"[ERROR STA-0562] create_clock -target is not a known keyword or flag. +'STA-0562'",OpenROAD执行阶段失败（配置或文件路径问题）,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +CTS,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'TritonCTS' object has no attribute 'configureBufferList'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +CTS,"invalid command name ""assign_clock""'",未知错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +CTS,"Traceback (most recent call last): + +File """", line 1, in + +AttributeError +: +'TritonCTS' object has no attribute 'setFinalSinkBuffer' +. Did you mean: ' +setSinkBuffer +'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILLER,"Traceback (most recent call last): + File """", line 3, in +AttributeError: 'dbMaster' object has no attribute 'getCellType'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILLER,"[INFO DPL-0001] Placed 776 filler instances. + + + + + + + +Traceback (most recent call last): + File """", line 4, in +AttributeError: 'dbInst' object has no attribute 'remove'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILLER,"Traceback (most recent call last): + File """", line 4, in +TypeError: Opendp.fillerPlacement() got an unexpected keyword argument 'filler_cell_naming_rule'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILLER,"[INFO DPL-0001] Placed 776 filler instances. + + + + + + + +Traceback (most recent call last): + File """", line 4, in +AttributeError: 'Design' object has no attribute 'removeFiller'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILLER,"Traceback (most recent call last): + File """", line 4, in +TypeError: Opendp.fillerPlacement() got an unexpected keyword argument 'filler_cells'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILLER,"[INFO DPL-0001] Placed 776 filler instances. + + + + + + + +Traceback (most recent call last): + File """", line 4, in +AttributeError: 'Design' object has no attribute 'deleteFiller'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILLER,"Traceback (most recent call last): + File """", line 4, in +AttributeError: 'Design' object has no attribute 'getOpenROADFillerCellInsert'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILLER,"[INFO DPL-0001] Placed 776 filler instances. + + + + + + + + +Traceback (most recent call last): + File """", line 5, in +AttributeError: 'dbInst' object has no attribute 'destory' +. Did you mean: 'destroy'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILLER,"Traceback (most recent call last): + File """", line 4, in +AttributeError: 'Opendp' object has no attribute 'fillerInsert'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILLER,"[INFO DPL-0001] Placed 776 filler instances. + + + + + + + +Traceback (most recent call last): + File """", line 4, in +AttributeError: 'Design' object has no attribute 'getOpenDp' +. Did you mean: 'getOpendp'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILLER,"Traceback (most recent call last): + File """", line 4, in +AttributeError: 'Opendp' object has no attribute 'fillerCellPlacement' +. Did you mean: 'fillerPlacement'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +FILLER,"[INFO DPL-0001] Placed 776 filler instances. + + + + + + + +Traceback (most recent call last): + File """", line 4, in +AttributeError: 'Design' object has no attribute 'getOpenDp' +. Did you mean: 'getOpendp'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + +0 + + + + + + +0 + + + + + + +503 + + + + + + +0 + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 2, in +AttributeError: 'PdnGen' object has no attribute 'createRing'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 74, in +AttributeError: 'PdnGen' object has no attribute",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"Traceback (most recent call last): + File """", line 4, in +AttributeError: 'dbNet' object has no attribute 'assignSigType'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """,Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'PdnGen' object has no attribute 'removeGrid'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + +0 + + + + + + +0 + + + + + + +503 + + + + + + +0 + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 46, in +AttributeError: 'PdnGen' object has no attribute 'connectVia'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 74, in +AttributeError: 'PdnGen' object has no attribute",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 33, in +AttributeError: 'PdnGen' object has no attribute 'createConnect' +. Did you mean: 'm",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 33, in +AttributeError: 'PdnGen' object has no attribute 'createConnect' +. Did you mean: 'm",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'PdnGen' object has no attribute 'disconnectGrid'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + +0 + + + + + + +0 + + + + + + +503 + + + + + + +0 + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 46, in +AttributeError: 'PdnGen' object has no attribute 'connectVia'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 74, in +AttributeError: 'PdnGen' object has no attribute",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 33, in +AttributeError: 'PdnGen' object has no attribute 'connectLayers'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 8, in +TypeError: PdnGen.makeStrap() got an unexpected keyword argument 'alignment'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"Traceback (most recent call last): + File """", line 1, in +TypeError: PdnGen.ripUp() got an unexpected keyword argument 'force'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + +0 + + + + + + +0 + + + + + + +503 + + + + + + +0 + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 3, in +AttributeError: 'PdnGen' object has no attribute 'constructRing'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 74, in +AttributeError: 'PdnGen' object has no attribute",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 33, in +AttributeError: 'PdnGen' object has no attribute 'connectLayers'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 8, in +TypeError: PdnGen.makeStrap() got an unexpected keyword argument 'optimize'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'PdnGen' object has no attribute 'removeGrid'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + +0 + + + + + + +0 + + + + + + +503 + + + + + + +0 + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 18, in +AttributeError: 'PdnGen' object has no attribute 'attachFollowp",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 74, in +AttributeError: 'PdnGen' object has no attribute",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 33, in +AttributeError: 'PdnGen' object has no attribute 'connectLayers'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 33, in +AttributeError: 'PdnGen' object has no attribute 'linkConnect' +. Did you mean: 'mak",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'PdnGen' object has no attribute 'destroyGrid'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'dbBlock' object has no attribute 'addPDNConnect'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 74, in +AttributeError: 'PdnGen' object has no attribute",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 33, in +AttributeError: 'PdnGen' object has no attribute 'establishConnectivity'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"503 + + + + + + + +0 + + + + + + + +0 + + + + + + + +503 + + + + + + + +0 + + + +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Traceback (most recent call last): + File """", line 33, in +AttributeError: 'PdnGen' object has no attribute 'linkConnect' +. Did you mean: 'mak",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +PDN,"Traceback (most recent call last): + File """", line 1, in +TypeError: PdnGen.ripUp() got an unexpected keyword argument 'mode'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +GRT,"Traceback (most recent call last): + File """", line 1, in +TypeError: GlobalRouter.setAdjustment() takes 2 positional arguments but 3 were given",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +GRT,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'GlobalRouter' object has no attribute 'executeGlobalRoute'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +GRT,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'GlobalRouter' object has no attribute 'executeGlobalRouting' +. Did you mean: 'boxToGlobalRouting'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +GRT,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'GlobalRouter' object has no attribute 'setRoutingVerbose'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +GRT,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'GlobalRouter' object has no attribute 'enableVerbosity'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +GRT,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'GlobalRouter' object has no attribute 'enableLogging'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DRT,"Traceback (most recent call last): + File """", line 1, in +NameError: name 'drt' is not defined",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DRT,"[ERROR DRT-0002] Detailed routing has not been run yet. +Traceback (most recent call last): + File """", line 1, in +File ""drt_py.py"", line 122, in getNumDRVs +RuntimeError: DRT-0002",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DRT,"Traceback (most recent call last): + File """", line 1, in +NameError: name 'drt' is not defined",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DRT,"[ERROR DRT-0002] Detailed routing has not been run yet. +Traceback (most recent call last): + File """", line 1, in +File ""drt_py.py"", line 122, in getNumDRVs +RuntimeError: DRT-0002",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DRT,"Traceback (most recent call last): + File """", line 1, in +NameError: name 'drt' is not defined",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DRT,"[ERROR DRT-0002] Detailed routing has not been run yet. +Traceback (most recent call last): + File """", line 1, in +File ""drt_py.py"", line 122, in getNumDRVs +RuntimeError: DRT-0002",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DRT,"Traceback (most recent call last): + File """", line 1, in +NameError: name 'drt' is not defined",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DRT,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'TritonRoute' object has no attribute 'retrieveNumDRVs'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DRT,"Traceback (most recent call last): + File """", line 1, in +NameError: name 'drt' is not defined",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DRT,"[ERROR DRT-0002] Detailed routing has not been run yet. +Traceback (most recent call last): + File """", line 1, in +File ""drt_py.py"", line 122, in getNumDRVs +RuntimeError: DRT-0002",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DRT,"Traceback (most recent call last): + File """", line 1, in +NameError: name 'drt' is not defined",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +DRT,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'TritonRoute' object has no attribute 'getDRVCount'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IR,"Traceback (most recent call last): + File """", line 1, in +NameError: name 'psm' is not defined",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IR,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'executeTclCommand'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IR,"Traceback (most recent call last): + File """", line 1, in +NameError: name 'psm' is not defined",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IR,"Traceback (most recent call last): + File """", line 1, in +TypeError: Design.evalTclString() got an unexpected keyword argument 'detailed'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IR,"Traceback (most recent call last): + File """", line 1, in +NameError: name 'psm' is not defined",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IR,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'executePowerReport'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IR,"Traceback (most recent call last): + File """", line 1, in +NameError: name 'psm' is not defined",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IR,"Traceback (most recent call last): + File """", line 1, in +TypeError: Design.evalTclString() got an unexpected keyword argument 'level'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IR,"Traceback (most recent call last): + File """", line 1, in +NameError: name 'psm' is not defined",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IR,"Traceback (most recent call last): + File """", line 1, in +AttributeError: 'Design' object has no attribute 'evalTclScript' +. Did you mean: 'evalTclString'?",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IR,"Traceback (most recent call last): + File """", line 1, in +NameError: name 'psm' is not defined",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, +IR,"Traceback (most recent call last): + File """", line 1, in +TypeError: Design.evalTclString() got an unexpected keyword argument 'mode'",Python语法或API调用错误,检查模块初始化顺序、输入文件路径、API调用参数是否正确。可参考相应的正确脚本示例。, diff --git a/flow-Agent/rag_data/README.md b/flow-Agent/rag_data/README.md new file mode 100644 index 0000000..456a8b8 --- /dev/null +++ b/flow-Agent/rag_data/README.md @@ -0,0 +1 @@ +Stores retrieval databases, design logs, error samples, and knowledge index files. diff --git a/flow-Agent/rag_data/docs.pkl b/flow-Agent/rag_data/docs.pkl new file mode 100644 index 0000000..6a4ac25 Binary files /dev/null and b/flow-Agent/rag_data/docs.pkl differ diff --git a/flow-Agent/rag_data/embeddings.npy b/flow-Agent/rag_data/embeddings.npy new file mode 100644 index 0000000..e070b63 Binary files /dev/null and b/flow-Agent/rag_data/embeddings.npy differ diff --git a/flow-Agent/run_all.sh b/flow-Agent/run_all.sh new file mode 100644 index 0000000..371b613 --- /dev/null +++ b/flow-Agent/run_all.sh @@ -0,0 +1,22 @@ +#!/bin/bash +# run_all.sh - sequentially run maindriver.sh for multiple (design, platform) pairs + +# define (design, platform) pairs +pairs=( + "aes asap7" + "aes sky130hd" + "ibex sky130hd" + "ibex asap7" + "jpeg sky130hd" + "jpeg asap7" +) + +# Execute each combination sequentially +for pair in "${pairs[@]}"; do + read d p <<< "$pair" + echo "===========================================" + echo "Running design: $d, platform: $p" + echo "===========================================" + ./maindriver.sh -p "$p" -d "$d" -o DWL + echo +done diff --git a/flow-Agent/stage_optimize.py b/flow-Agent/stage_optimize.py new file mode 100644 index 0000000..a52efd3 --- /dev/null +++ b/flow-Agent/stage_optimize.py @@ -0,0 +1,528 @@ +#!/usr/bin/env python3 +""" +Stage-level optimization driver for OpenROAD Flow Scripts. + +This tool executes the OpenROAD flow one stage at a time (synth → floorplan → place → cts → route → finish), +collects the resulting metrics/logs, and queries the existing ReAct framework to recommend +stage-local parameter tuning. +""" + +from __future__ import annotations + +import argparse +import json +import os +import re +import statistics +import subprocess +import sys +import textwrap +from dataclasses import dataclass, field +from pathlib import Path +from typing import Any, Dict, Iterable, List, Optional, Tuple + +from optimize import ( + OptimizationWorkflow, + process_log_file, +) + + +@dataclass +class StageDefinition: + """Metadata describing how to run and analyse a single flow stage.""" + + name: str + make_target: str + log_prefix: str + description: str + parameter_keys: List[str] = field(default_factory=list) + + +# Mapping between parameter identifiers used in OptimizationWorkflow and their make/env names. +PARAM_TO_ENV_VAR = { + "synth_flatten": "SYNTH_FLATTEN", + "core_util": "CORE_UTILIZATION", + "cell_pad_global": "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT", + "cell_pad_detail": "CELL_PAD_IN_SITES_DETAIL_PLACEMENT", + "lb_addon": "PLACE_DENSITY_LB_ADDON", + "enable_dpo": "ENABLE_DPO", + "pin_layer": "PIN_LAYER_ADJUST", + "above_layer": "ABOVE_LAYER_ADJUST", + "tns": "TNS_END_PERCENT", + "cts_size": "CTS_CLUSTER_SIZE", + "cts_diameter": "CTS_CLUSTER_DIAMETER", +} + + +def _stage_definitions() -> List[StageDefinition]: + """Return the default stage ordering and configuration.""" + return [ + StageDefinition( + name="synth", + make_target="do-synth", + log_prefix="1_", + description="Logic synthesis using Yosys; focus on timing slack and area metrics.", + parameter_keys=["synth_flatten"], + ), + StageDefinition( + name="floorplan", + make_target="do-floorplan", + log_prefix="2_", + description="Macro and core floorplanning; adjust area utilization and pin placement.", + parameter_keys=[ + "core_util", + "cell_pad_global", + "cell_pad_detail", + "lb_addon", + ], + ), + StageDefinition( + name="place", + make_target="do-place", + log_prefix="3_", + description="Global/detail placement; tune density, legalization and detail placement options.", + parameter_keys=[ + "lb_addon", + "enable_dpo", + "pin_layer", + "above_layer", + ], + ), + StageDefinition( + name="cts", + make_target="do-cts", + log_prefix="4_", + description="Clock-tree synthesis (CTS); control cluster sizing and clock routing targets.", + parameter_keys=[ + "cts_size", + "cts_diameter", + ], + ), + StageDefinition( + name="route", + make_target="do-route", + log_prefix="5_", + description="Global and detailed routing; focus on timing violations and routing congestion.", + parameter_keys=[ + "pin_layer", + "above_layer", + "tns", + ], + ), + StageDefinition( + name="finish", + make_target="do-finish", + log_prefix="6_", + description="Fill, reporting and final sign-off data generation.", + parameter_keys=[], + ), + ] + + +class StageOptimizationDriver: + """Coordinates per-stage execution, log aggregation, and ReAct-based recommendations.""" + + def __init__( + self, + platform: str, + design: str, + objective: str, + stages: Optional[Iterable[str]] = None, + max_react_steps: int = 3, + temperature: float = 0.1, + workdir: Optional[Path] = None, + dry_run: bool = False, + ) -> None: + self.workdir = Path(workdir or os.getcwd()) + self.platform = platform + self.design = design + self.objective = objective.upper() + self.max_react_steps = max_react_steps + self.temperature = temperature + self.dry_run = dry_run + + # Reuse existing workflow components (embeddings, constraints, ReAct client, etc.). + self.workflow = OptimizationWorkflow(platform, design, objective) + self.react = self.workflow.react_framework + self.initial_params = self.workflow.initial_params + self.param_constraints = self.workflow.param_constraints + + # Track per-stage overrides/recommendations. + self.stage_overrides: Dict[str, Dict[str, Any]] = {} + self.stage_recommendations: Dict[str, Dict[str, Any]] = {} + + stage_list = _stage_definitions() + if stages: + stage_filter = {name.lower() for name in stages} + stage_list = [sd for sd in stage_list if sd.name.lower() in stage_filter] + missing = stage_filter.difference({sd.name.lower() for sd in stage_list}) + if missing: + raise ValueError(f"Unknown stages requested: {', '.join(sorted(missing))}") + + self.stage_sequence = stage_list + + # ------------------------------------------------------------------ CLI helpers + def run(self) -> None: + for stage in self.stage_sequence: + self._execute_stage(stage) + + self._print_summary() + + # ------------------------------------------------------------------ Execution + def _execute_stage(self, stage: StageDefinition) -> None: + print(f"\n=== Stage: {stage.name.upper()} ===") + print(stage.description) + + overrides = self.stage_overrides.get(stage.name, {}) + if overrides: + print("Applying overrides:", " ".join(f"{k}={v}" for k, v in overrides.items())) + + command = ["make", stage.make_target] + for env_var, value in overrides.items(): + command.append(f"{env_var}={value}") + + if self.dry_run: + print("(dry-run) Skipping execution:", " ".join(command)) + else: + print("Running:", " ".join(command)) + try: + subprocess.run( + command, + cwd=self.workdir, + check=True, + ) + except subprocess.CalledProcessError as exc: + print(f"[ERROR] Stage '{stage.name}' execution failed with exit code {exc.returncode}") + raise + + stage_data = self._collect_stage_data(stage) + parameter_info = self._get_stage_parameter_info(stage) + + if not parameter_info: + print("No adjustable parameters registered for this stage; skipping ReAct recommendation.") + return + + react_prompt = self._build_stage_prompt(stage, stage_data, parameter_info) + tools = self._build_stage_tools(stage_data, parameter_info) + + print("[INFO] Requesting ReAct recommendations...") + react_result = self.react.run_react_cycle( + initial_prompt=react_prompt, + available_tools=tools, + max_steps=self.max_react_steps, + temperature=self.temperature, + ) + + final_answer = react_result.get("final_answer", "") + recommendations = self._parse_stage_recommendations(stage, final_answer, parameter_info) + if recommendations: + self.stage_recommendations[stage.name] = recommendations + print("[INFO] Recommended adjustments:") + for env_var, value in recommendations.items(): + print(f" - {env_var} := {value}") + else: + print("[WARN] No actionable recommendations parsed from ReAct response.") + + # ------------------------------------------------------------------ Data aggregation + def _collect_stage_data(self, stage: StageDefinition) -> Dict[str, Any]: + log_dir = self.workdir / "logs" + log_files = sorted(log_dir.glob(f"{stage.log_prefix}*.log")) + json_files = sorted(log_dir.glob(f"{stage.log_prefix}*.json")) + + log_summaries = [] + aggregated_metrics: Dict[str, List[float]] = {} + errors: List[str] = [] + + for log_file in log_files: + summary = process_log_file(str(log_file)) + summary["path"] = str(log_file) + log_summaries.append(summary) + + for metric_name, value in summary.get("metrics", {}).items(): + try: + aggregated_metrics.setdefault(metric_name, []).append(float(value)) + except (TypeError, ValueError): + continue + + errors.extend(summary.get("errors", [])) + + aggregated = { + metric: { + "mean": statistics.mean(values) if values else None, + "min": min(values) if values else None, + "max": max(values) if values else None, + "latest": values[-1] if values else None, + "samples": len(values), + } + for metric, values in aggregated_metrics.items() + } + + json_payloads: List[Tuple[str, Any]] = [] + for json_file in json_files: + try: + with open(json_file, "r", encoding="utf-8") as f: + data = json.load(f) + json_payloads.append((str(json_file), data)) + except Exception as exc: # noqa: BLE001 + errors.append(f"Failed to parse {json_file}: {exc}") + + recent_log_snippet = "" + if log_files: + recent_log_snippet = self._tail_file(log_files[-1], max_lines=40) + + return { + "logs": log_summaries, + "metrics": aggregated, + "json": json_payloads, + "errors": errors, + "recent_log_snippet": recent_log_snippet, + } + + def _get_stage_parameter_info(self, stage: StageDefinition) -> List[Dict[str, Any]]: + info: List[Dict[str, Any]] = [] + for param_key in stage.parameter_keys: + env_var = PARAM_TO_ENV_VAR.get(param_key) + constraint = self.param_constraints.get(param_key) + if env_var is None or constraint is None: + continue + + current_value = self._current_env_value(stage.name, env_var, constraint) + info.append( + { + "param_key": param_key, + "env_var": env_var, + "type": constraint.get("type"), + "range": constraint.get("range"), + "current_value": current_value, + } + ) + + return info + + # ------------------------------------------------------------------ Prompt + tools + def _build_stage_prompt( + self, + stage: StageDefinition, + stage_data: Dict[str, Any], + parameter_info: List[Dict[str, Any]], + ) -> str: + metrics_lines = [] + for name, stats in stage_data["metrics"].items(): + metrics_lines.append( + f"- {name}: latest={stats['latest']} mean={stats['mean']} min={stats['min']} max={stats['max']} (samples={stats['samples']})" + ) + metrics_text = "\n".join(metrics_lines) if metrics_lines else "No metrics captured for this stage." + + parameters_text = json.dumps(parameter_info, indent=2) + + errors_text = "\n".join(stage_data.get("errors", [])) or "No errors captured." + log_tail = stage_data.get("recent_log_snippet", "").strip() or "(no log excerpt available)" + + prompt = textwrap.dedent( + f""" + You are assisting with stage-specific optimization of the OpenROAD flow. + + Stage: {stage.name.upper()} + Platform: {self.platform} + Design: {self.design} + Objective: {self.objective} + + Stage description: + {stage.description} + + Recent metrics: + {metrics_text} + + Errors (if any): + {errors_text} + + Recent log excerpt: + ``` + {log_tail} + ``` + + Adjustable parameters for this stage (env vars with ranges and current values): + {parameters_text} + + Requirements: + - Suggest updated values only for the listed parameters. + - Keep all values within the specified ranges and respect their types. + - Focus on improving the stage metrics relevant to the {self.objective} objective. + - Return concise recommendations ready to be passed back to `make` as VAR=value overrides. + + Final Answer format (must be JSON): + Final Answer: {{"parameters": {{"ENV_VAR": value, ...}}, "notes": "short justification"}} + """ + ).strip() + return prompt + + def _build_stage_tools( + self, + stage_data: Dict[str, Any], + parameter_info: List[Dict[str, Any]], + ) -> Dict[str, Any]: + return { + "list_parameters": lambda _: json.dumps(parameter_info, indent=2), + "show_metrics": lambda _: json.dumps(stage_data.get("metrics", {}), indent=2), + "show_errors": lambda _: "\n".join(stage_data.get("errors", [])) or "No errors recorded.", + "show_log_tail": lambda _: stage_data.get("recent_log_snippet", "") or "No log excerpt.", + } + + # ------------------------------------------------------------------ Parsing + helpers + def _parse_stage_recommendations( + self, + stage: StageDefinition, + final_answer: str, + parameter_info: List[Dict[str, Any]], + ) -> Dict[str, Any]: + if not final_answer or "Final Answer" not in final_answer: + return {} + + match = re.search(r"\{.*\}", final_answer, re.DOTALL) + if not match: + return {} + + try: + payload = json.loads(match.group()) + except json.JSONDecodeError: + return {} + + raw_params = payload.get("parameters", payload) + if not isinstance(raw_params, dict): + return {} + + valid_envs = {info["env_var"] for info in parameter_info} + key_to_env = {info["param_key"]: info["env_var"] for info in parameter_info} + recommendations: Dict[str, Any] = {} + + for key, value in raw_params.items(): + env_var = key if key in valid_envs else key_to_env.get(key.lower()) or key_to_env.get(key) + if env_var not in valid_envs: + continue + + constraint = self._constraint_for_env(env_var, parameter_info) + coerced = self._coerce_to_constraint(value, constraint) + if coerced is not None: + recommendations[env_var] = coerced + + return recommendations + + def _constraint_for_env(self, env_var: str, parameter_info: List[Dict[str, Any]]) -> Optional[Dict[str, Any]]: + for info in parameter_info: + if info["env_var"] == env_var: + return { + "type": info.get("type"), + "range": info.get("range"), + } + return None + + def _coerce_to_constraint(self, value: Any, constraint: Optional[Dict[str, Any]]) -> Optional[Any]: + if constraint is None: + return value + + value_type = constraint.get("type") + value_range = constraint.get("range") + + try: + if value_type == "int": + coerced: Any = int(round(float(value))) + elif value_type == "float": + coerced = float(value) + else: + coerced = value + except (TypeError, ValueError): + return None + + if value_range and len(value_range) == 2: + min_val, max_val = value_range + if isinstance(coerced, (int, float)): + coerced = max(min_val, min(max_val, coerced)) + + return coerced + + def _current_env_value(self, stage_name: str, env_var: str, constraint: Dict[str, Any]) -> Any: + if stage_name in self.stage_overrides and env_var in self.stage_overrides[stage_name]: + return self.stage_overrides[stage_name][env_var] + + raw_value = self.initial_params.get(env_var) + if raw_value is None: + raw_value = os.environ.get(env_var) + + if raw_value is None: + return None + + return self._coerce_to_constraint(raw_value, constraint) + + @staticmethod + def _tail_file(path: Path, max_lines: int = 40) -> str: + try: + with open(path, "r", encoding="utf-8", errors="ignore") as f: + lines = f.readlines() + return "".join(lines[-max_lines:]) + except OSError: + return "" + + def _print_summary(self) -> None: + if not self.stage_recommendations: + print("\nNo stage recommendations were produced.") + return + + print("\n=== Stage Recommendations Summary ===") + for stage_name, params in self.stage_recommendations.items(): + print(f"{stage_name.upper()}:") + for env_var, value in params.items(): + print(f" - {env_var} := {value}") + + +def parse_args(argv: Optional[List[str]] = None) -> argparse.Namespace: + parser = argparse.ArgumentParser( + description="Run stage-by-stage optimization flow with ReAct recommendations.", + ) + parser.add_argument("platform", help="PDK/platform name (e.g. asap7, sky130hd).") + parser.add_argument("design", help="Design name (e.g. aes, ibex).") + parser.add_argument("objective", help="Optimization objective (ECP, DWL, COMBO).") + parser.add_argument( + "--stages", + nargs="+", + default=None, + help="Subset of stages to run (default: all). Options: synth floorplan place cts route finish.", + ) + parser.add_argument( + "--max-react-steps", + type=int, + default=3, + help="Maximum reasoning steps for the ReAct loop.", + ) + parser.add_argument( + "--temperature", + type=float, + default=0.1, + help="Sampling temperature for the LLM.", + ) + parser.add_argument( + "--dry-run", + action="store_true", + help="Show the make commands without executing them.", + ) + + return parser.parse_args(argv) + + +def main(argv: Optional[List[str]] = None) -> None: + args = parse_args(argv) + + driver = StageOptimizationDriver( + platform=args.platform, + design=args.design, + objective=args.objective, + stages=args.stages, + max_react_steps=args.max_react_steps, + temperature=args.temperature, + dry_run=args.dry_run, + ) + driver.run() + + +if __name__ == "__main__": + main() + diff --git a/flow-Agent/stage_override.py b/flow-Agent/stage_override.py new file mode 100644 index 0000000..e5a11f2 --- /dev/null +++ b/flow-Agent/stage_override.py @@ -0,0 +1,255 @@ +#!/usr/bin/env python3 +""" +Utility to run stage_optimize.py with explicit per-stage parameter overrides. + +Overrides can be provided via JSON files or inline CLI expressions of the form +`stage.parameter=value`. Parameter tokens may use either the logical parameter +keys (e.g. `core_util`) or their corresponding environment variables +(`CORE_UTILIZATION`). Values are coerced using JSON parsing semantics, so bare +numbers/booleans/null work without quoting while opaque strings can be wrapped +in quotes if needed. +""" + +from __future__ import annotations + +import argparse +import json +import sys +from pathlib import Path +from typing import Any, Dict, Mapping + +from stage_optimize import ( + PARAM_TO_ENV_VAR, + StageOptimizationDriver, + StageDefinition, + _stage_definitions, +) + + +StageOverrideMap = Dict[str, Dict[str, Any]] + + +def _build_stage_lookup() -> Dict[str, StageDefinition]: + return {stage.name.lower(): stage for stage in _stage_definitions()} + + +def _stage_env_vars(stage: StageDefinition) -> Dict[str, None]: + envs: Dict[str, None] = {} + for key in stage.parameter_keys: + env_var = PARAM_TO_ENV_VAR.get(key) + if env_var: + envs[env_var] = None + return envs + + +def _build_env_aliases() -> Dict[str, str]: + aliases: Dict[str, str] = {} + for key, env_var in PARAM_TO_ENV_VAR.items(): + aliases[key.lower()] = env_var + aliases[env_var.lower()] = env_var + return aliases + + +STAGE_LOOKUP = _build_stage_lookup() +ENV_ALIASES = _build_env_aliases() + + +def _resolve_stage(name: str) -> StageDefinition: + lookup_key = name.strip().lower() + if lookup_key not in STAGE_LOOKUP: + raise ValueError(f"Unknown stage '{name}'. Valid stages: {', '.join(sorted(STAGE_LOOKUP))}") + return STAGE_LOOKUP[lookup_key] + + +def _normalize_param(token: str) -> str: + if not token: + raise ValueError("Empty parameter override key encountered.") + alias = ENV_ALIASES.get(token.strip().lower()) + if alias is None: + valid = ", ".join(sorted(set(ENV_ALIASES.values()))) + raise ValueError(f"Unknown parameter '{token}'. Valid options include: {valid}") + return alias + + +def _parse_scalar(raw_value: str) -> Any: + text = raw_value.strip() + if not text: + return "" + try: + return json.loads(text) + except json.JSONDecodeError: + return text + + +def _load_file_overrides(path: Path) -> StageOverrideMap: + if not path.is_file(): + raise ValueError(f"Override file '{path}' does not exist.") + + try: + payload = json.loads(path.read_text(encoding="utf-8")) + except json.JSONDecodeError as exc: + raise ValueError(f"Failed to parse overrides file '{path}': {exc}") from exc + + if not isinstance(payload, Mapping): + raise ValueError(f"Overrides file '{path}' must contain a JSON object at the top level.") + + return _normalize_stage_mapping(payload, source=str(path)) + + +def _normalize_stage_mapping(data: Mapping[str, Any], *, source: str) -> StageOverrideMap: + overrides: StageOverrideMap = {} + for stage_name, params in data.items(): + stage = _resolve_stage(stage_name) + stage_envs = _stage_env_vars(stage) + if not params: + continue + if not isinstance(params, Mapping): + raise ValueError( + f"{source}: stage '{stage.name}' overrides must be an object of ENV=value entries." + ) + stage_overrides = overrides.setdefault(stage.name, {}) + for param_key, value in params.items(): + env_var = _normalize_param(param_key) + if env_var not in stage_envs: + valid = ", ".join(stage_envs.keys()) or "(no adjustable parameters)" + raise ValueError( + f"{source}: parameter '{env_var}' is not adjustable for stage '{stage.name}'. " + f"Valid parameters: {valid}" + ) + stage_overrides[env_var] = value + return overrides + + +def _parse_inline_overrides(values: Any) -> StageOverrideMap: + overrides: StageOverrideMap = {} + for expr in values or []: + if "=" not in expr: + raise ValueError( + f"Invalid inline override '{expr}'. Expected format 'stage.param=value'." + ) + lhs, rhs = expr.split("=", 1) + if "." not in lhs: + raise ValueError( + f"Invalid inline override '{expr}'. Expected 'stage.param=value' format." + ) + stage_token, param_token = lhs.split(".", 1) + stage = _resolve_stage(stage_token) + env_var = _normalize_param(param_token) + + stage_envs = _stage_env_vars(stage) + if env_var not in stage_envs: + valid = ", ".join(stage_envs.keys()) or "(no adjustable parameters)" + raise ValueError( + f"Inline override '{expr}' targets '{env_var}' which is not adjustable during stage " + f"'{stage.name}'. Valid parameters: {valid}" + ) + + value = _parse_scalar(rhs) + overrides.setdefault(stage.name, {})[env_var] = value + return overrides + + +def _merge_overrides(target: StageOverrideMap, addition: StageOverrideMap) -> None: + for stage, params in addition.items(): + if not params: + continue + target.setdefault(stage, {}).update(params) + + +def run_with_overrides(args: argparse.Namespace) -> None: + overrides: StageOverrideMap = {} + + if args.overrides_file: + for file_path in args.overrides_file: + file_overrides = _load_file_overrides(file_path) + _merge_overrides(overrides, file_overrides) + + inline_overrides = _parse_inline_overrides(args.override) + _merge_overrides(overrides, inline_overrides) + + if not overrides: + raise ValueError("No overrides provided. Use --overrides-file or --override.") + + print("Loaded stage overrides:") + for stage in sorted(overrides): + for env_var, value in overrides[stage].items(): + print(f" {stage}.{env_var} = {value}") + + driver = StageOptimizationDriver( + platform=args.platform, + design=args.design, + objective=args.objective, + stages=args.stages, + max_react_steps=args.max_react_steps, + temperature=args.temperature, + dry_run=args.dry_run, + workdir=args.workdir, + ) + driver.stage_overrides = overrides + driver.run() + + +def build_parser() -> argparse.ArgumentParser: + parser = argparse.ArgumentParser( + description="Apply explicit parameter overrides when running stage_optimize.py." + ) + parser.add_argument("platform", help="PDK/platform name (e.g. asap7, sky130hd).") + parser.add_argument("design", help="Design name (e.g. aes, ibex).") + parser.add_argument("objective", help="Optimization objective (ECP, DWL, COMBO).") + parser.add_argument( + "--stages", + nargs="+", + default=None, + help="Subset of stages to run (default: all). Options: synth floorplan place cts route finish.", + ) + parser.add_argument( + "--max-react-steps", + type=int, + default=3, + help="Maximum reasoning steps for the ReAct loop.", + ) + parser.add_argument( + "--temperature", + type=float, + default=0.1, + help="Sampling temperature for the LLM.", + ) + parser.add_argument( + "--dry-run", + action="store_true", + help="Show the make commands without executing them.", + ) + parser.add_argument( + "--workdir", + type=Path, + default=None, + help="Flow workspace root (default: current working directory).", + ) + parser.add_argument( + "-f", + "--overrides-file", + action="append", + type=Path, + help="Path to a JSON file describing stage overrides.", + ) + parser.add_argument( + "-o", + "--override", + action="append", + default=[], + help="Inline override in the form 'stage.parameter=value'. Repeatable.", + ) + return parser + + +def main(argv: Any = None) -> None: + parser = build_parser() + args = parser.parse_args(argv) + try: + run_with_overrides(args) + except ValueError as exc: + parser.error(str(exc)) + + +if __name__ == "__main__": + main() diff --git a/flow-Agent/test_rag.py b/flow-Agent/test_rag.py new file mode 100644 index 0000000..5914d10 --- /dev/null +++ b/flow-Agent/test_rag.py @@ -0,0 +1,63 @@ +import os +import torch +from sentence_transformers import SentenceTransformer +from rag.index import load_embeddings_and_docs, build_and_save_embeddings +from rag.util import answerWithRAG +from pathlib import Path + +def test_rag(query): + """ + Test the RAG retrieval and response functions. + """ + print("=" * 60) + print("[TEST] Starting RAG Functionality Test") + print("=" * 60) + + # Make sure RAGData exists + if not os.path.exists("rag_date"): + os.makedirs("rag_date", exist_ok=True) + + # Step 1: Build if the embeddings do not exist + emb_path = os.path.join("rag_date", "embeddings.npy") + docs_path = os.path.join("rag_date", "docs.pkl") + + if not os.path.exists(emb_path) or not os.path.exists(docs_path): + print("[INFO] Embeddings not found, building new ones...") + build_and_save_embeddings() + else: + print("[INFO] Embeddings found, skipping build step.") + + # Step 2: Load vector library + print("[INFO] Loading embeddings and documents...") + embeddings_np, docs, docsDict = load_embeddings_and_docs() + embeddings = torch.tensor(embeddings_np) + + # Step 3: Load model + print("[INFO] Loading embedding model...") + model_path = Path(__file__).parent / "models" / "mxbai-embed-large-v1" + + # Key: Switch to the absolute path + model_path = model_path.resolve() + + print("[DEBUG] Using absolute model path:", model_path) + + embeddingModel = SentenceTransformer(str(model_path)) + + # Step 4: Questions and perform the RAG retrieval + print("=" * 60) + print(f"[QUERY] {query}") + print("=" * 60) + answer = answerWithRAG(query, embeddings, embeddingModel, docs, docsDict) + + # Step 5: Output results + print("\n[ANSWER CONTEXT]") + print("-" * 60) + print(answer if answer else "No relevant context found.") + print("-" * 60) + + print("[TEST] RAG test completed successfully.") + + +if __name__ == "__main__": + # You can freely modify the query to test different questions + test_rag("Please analyze the data and provide insights on:1. Key patterns in successful vs unsuccessful runs.2. Parameter ranges that appear promising.3. Any timing or wirelength trends.4. Recommendations for subsequent runs.")