@@ -1413,22 +1413,21 @@ module MakeImpl<InputSig Lang> {
14131413 )
14141414 }
14151415
1416- pragma [ nomagic ]
1417- private predicate flowIntoCallApaCallContextReduced (
1418- DataFlowCall call , DataFlowCallable c , ArgNodeEx arg , ParamNodeEx p ,
1419- boolean allowsFieldFlow , ApApprox apa , CcCall outercc
1416+ bindingset [ call , ctx ]
1417+ pragma [ inline_late ]
1418+ private DataFlowCallable viableImplCallContextReducedInlineLate (
1419+ DataFlowCall call , CcCall ctx
14201420 ) {
1421- c = viableImplCallContextReduced ( call , outercc ) and
1422- flowIntoCallApa ( call , c , arg , p , allowsFieldFlow , apa )
1421+ result = viableImplCallContextReduced ( call , ctx )
14231422 }
14241423
1425- bindingset [ arg, outercc ]
1424+ bindingset [ arg, ctx ]
14261425 pragma [ inline_late]
1427- private predicate viableImplArgNotCallContextReduced (
1428- DataFlowCall call , ArgNodeEx arg , Cc outercc
1426+ private DataFlowCallable viableImplCallContextReducedInlineLate (
1427+ DataFlowCall call , ArgNodeEx arg , CcCall ctx
14291428 ) {
14301429 call = arg .getCall ( ) and
1431- viableImplNotCallContextReduced ( call , outercc )
1430+ result = viableImplCallContextReducedInlineLate ( call , ctx )
14321431 }
14331432
14341433 bindingset [ call]
@@ -1440,6 +1439,21 @@ module MakeImpl<InputSig Lang> {
14401439 flowIntoCallApa ( call , c , arg , p , allowsFieldFlow , apa )
14411440 }
14421441
1442+ bindingset [ call, ctx]
1443+ pragma [ inline_late]
1444+ private predicate viableImplNotCallContextReducedInlineLate ( DataFlowCall call , Cc ctx ) {
1445+ viableImplNotCallContextReduced ( call , ctx )
1446+ }
1447+
1448+ bindingset [ arg, outercc]
1449+ pragma [ inline_late]
1450+ private predicate viableImplArgNotCallContextReduced (
1451+ DataFlowCall call , ArgNodeEx arg , Cc outercc
1452+ ) {
1453+ call = arg .getCall ( ) and
1454+ viableImplNotCallContextReducedInlineLate ( call , outercc )
1455+ }
1456+
14431457 pragma [ nomagic]
14441458 private predicate fwdFlowIn (
14451459 DataFlowCall call , ParamNodeEx p , FlowState state , Cc outercc , CcCall innercc ,
@@ -1448,27 +1462,35 @@ module MakeImpl<InputSig Lang> {
14481462 exists ( ArgNodeEx arg , boolean allowsFieldFlow , DataFlowCallable inner |
14491463 fwdFlow ( arg , state , outercc , summaryCtx , argT , argAp , t , ap , apa ) and
14501464 (
1451- flowIntoCallApaCallContextReduced ( call , inner , arg , p , allowsFieldFlow , apa , outercc )
1465+ inner = viableImplCallContextReducedInlineLate ( call , arg , outercc )
14521466 or
1453- viableImplArgNotCallContextReduced ( call , arg , outercc ) and
1454- flowIntoCallApaInlineLate ( call , inner , arg , p , allowsFieldFlow , apa )
1455- )
1467+ viableImplArgNotCallContextReduced ( call , arg , outercc )
1468+ ) and
1469+ flowIntoCallApaInlineLate ( call , inner , arg , p , allowsFieldFlow , apa )
14561470 |
14571471 innercc = getCallContextCall ( call , inner ) and
14581472 if allowsFieldFlow = false then ap instanceof ApNil else any ( )
14591473 )
14601474 }
14611475
1462- pragma [ nomagic]
1463- private predicate flowOutOfCallApaCallContextReduced (
1476+ bindingset [ ctx, result ]
1477+ pragma [ inline_late]
1478+ private DataFlowCallable viableImplCallContextReducedReverseInlineLate (
1479+ DataFlowCall call , CcNoCall ctx
1480+ ) {
1481+ result = viableImplCallContextReducedReverse ( call , ctx )
1482+ }
1483+
1484+ bindingset [ call]
1485+ pragma [ inline_late]
1486+ private predicate flowOutOfCallApaInlineLate (
14641487 DataFlowCall call , DataFlowCallable c , RetNodeEx ret , NodeEx out , boolean allowsFieldFlow ,
1465- ApApprox apa , CcNoCall innercc
1488+ ApApprox apa
14661489 ) {
1467- flowOutOfCallApa ( call , c , ret , _, out , allowsFieldFlow , apa ) and
1468- c = viableImplCallContextReducedReverse ( call , innercc )
1490+ flowOutOfCallApa ( call , c , ret , _, out , allowsFieldFlow , apa )
14691491 }
14701492
1471- bindingset [ ret, apa, innercc]
1493+ bindingset [ c , ret, apa, innercc]
14721494 pragma [ inline_late]
14731495 pragma [ noopt]
14741496 private predicate flowOutOfCallApaNotCallContextReduced (
@@ -1490,9 +1512,10 @@ module MakeImpl<InputSig Lang> {
14901512 DataFlowCallable inner
14911513 |
14921514 fwdFlow ( ret , state , innercc , summaryCtx , argT , argAp , t , ap , apa ) and
1515+ inner = ret .getEnclosingCallable ( ) and
14931516 (
1494- flowOutOfCallApaCallContextReduced ( call , inner , ret , out , allowsFieldFlow , apa ,
1495- innercc )
1517+ inner = viableImplCallContextReducedReverseInlineLate ( call , innercc ) and
1518+ flowOutOfCallApaInlineLate ( call , inner , ret , out , allowsFieldFlow , apa )
14961519 or
14971520 flowOutOfCallApaNotCallContextReduced ( call , inner , ret , out , allowsFieldFlow , apa ,
14981521 innercc )
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