diff --git a/configs/config.lenovo_thinkpad_t460s_edk2 b/configs/config.lenovo_thinkpad_t460s_edk2
new file mode 100644
index 00000000000..d2d3ba30aa8
--- /dev/null
+++ b/configs/config.lenovo_thinkpad_t460s_edk2
@@ -0,0 +1,23 @@
+CONFIG_LOCALVERSION="v0.9.0-rc1"
+CONFIG_CCACHE=y
+# CONFIG_COLLECT_TIMESTAMPS is not set
+CONFIG_NO_STAGE_CACHE=y
+CONFIG_VENDOR_LENOVO=y
+CONFIG_FMDFILE="src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/board.fmd"
+# CONFIG_NO_POST is not set
+# CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_DUAL is not set
+# CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_QUAD is not set
+CONFIG_IFD_BIN_PATH="ifd.bin"
+CONFIG_ME_BIN_PATH="me.bin"
+CONFIG_GBE_BIN_PATH="gbe.bin"
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_BOARD_LENOVO_T460S=y
+CONFIG_PAYLOAD_EDK2=y
+CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_HAVE_GBE_BIN=y
+# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_EDK2_CBMEM_LOGGING=y
+# CONFIG_TPM2 is not set
+CONFIG_TPM1=y
+CONFIG_TPM=y
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
index 577cafe87c1..74d58bcb750 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
@@ -23,6 +23,10 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 
+config BOARD_LENOVO_T460S
+	bool
+	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+
 config BOARD_LENOVO_T480
 	bool
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
@@ -38,6 +42,7 @@ config MAINBOARD_DIR
 	default "lenovo/sklkbl_thinkpad"
 
 config VARIANT_DIR
+	default "t460s" if BOARD_LENOVO_T460S
 	default "t480" if BOARD_LENOVO_T480
 	default "t480s" if BOARD_LENOVO_T480S
 
@@ -45,6 +50,12 @@ config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config MAINBOARD_PART_NUMBER
+	default "T460s" if BOARD_LENOVO_T480S
+	default "T480" if BOARD_LENOVO_T480
+	default "T480s" if BOARD_LENOVO_T480S
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "T460s" if BOARD_LENOVO_T480S
 	default "T480" if BOARD_LENOVO_T480
 	default "T480s" if BOARD_LENOVO_T480S
 
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
index abc273f387e..029849d2594 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
@@ -5,3 +5,6 @@ config BOARD_LENOVO_T480
 
 config BOARD_LENOVO_T480S
 	bool "ThinkPad T480s"
+
+config BOARD_LENOVO_T460S
+	bool "ThinkPad T460s"
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
index 7122a232b44..fdf7779d0b5 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
@@ -19,3 +19,14 @@ spd_$(1).bin-type := raw
 endef
 $(foreach n,$(SPD_BINS),$(eval $(call SPD_template,$(n))))
 endif
+
+# Add files spd_0.bin to spd_9.bin to the cbfs image
+ifeq ($(CONFIG_BOARD_LENOVO_T480S),y)
+SPD_BINS := $(shell seq 0 9)
+define SPD_template
+cbfs-files-y += spd_$(1).bin
+spd_$(1).bin-file := variants/$(VARIANT_DIR)/spd/spd_$(1).bin
+spd_$(1).bin-type := raw
+endef
+$(foreach n,$(SPD_BINS),$(eval $(call SPD_template,$(n))))
+endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
index dab7c9b6057..571536de726 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
@@ -9,6 +9,7 @@ chip soc/intel/skylake
         register "PmConfigSlpAMinAssert" = "3"          # 2s
 
 	device domain 0 on
+		subsystemid 0x17aa 0x225d inherit
 		device ref igpu on
 			register "gfx" = "GMA_STATIC_DISPLAYS(0)"
 			register "panel_cfg" = "{
@@ -23,10 +24,10 @@ chip soc/intel/skylake
 		device ref sa_thermal on end
 		device ref thermal on end
 		device ref south_xhci on end
-		device ref sata on
-			register "SataPortsEnable[2]" = "1"
-			register "SataPortsDevSlp[2]" = "1"
-		end
+		# device ref sata on
+		# 	register "SataPortsEnable[2]" = "1"
+		# 	register "SataPortsDevSlp[2]" = "1"
+		# end
 		device ref lpc_espi on
 			register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/board.fmd b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/board.fmd
new file mode 100644
index 00000000000..f1f7679a4ac
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/board.fmd
@@ -0,0 +1,40 @@
+FLASH 16M {
+	SI_ALL 7M {
+		SI_DESC 4K
+		SI_ME
+	}
+
+	RW_MISC 424K {
+		UNIFIED_MRC_CACHE(PRESERVE) 128K {
+			RECOVERY_MRC_CACHE 64K
+			RW_MRC_CACHE 64K
+		}
+		SMMSTORE(PRESERVE) 256K
+		RW_SHARED 0x4000 {
+			SHARED_DATA@0x0 0x2000
+			VBLOCK_DEV@0x2000 0x2000
+		}
+		RW_NVRAM(PRESERVE) 24K
+	}
+
+	CONSOLE 0x20000
+
+	BOOTSPLASH(CBFS) 1M
+
+	RW_SECTION_A {
+		VBLOCK_A 0x2000
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 0x100
+	}
+
+	WP_RO@0xC00000 0x400000 {
+		RO_VPD(PRESERVE)@0x0 0x4000
+		RO_SECTION@0x4000 0x3fc000 {
+			FMAP@0x0 0x800
+			RO_FRID@0x800 0x100
+			RO_FRID_PAD@0x900 0x700
+			GBB@0x1000 0x3000
+			COREBOOT(CBFS)@0x4000 0x3f8000
+		}
+	}
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/data.vbt
new file mode 100644
index 00000000000..c40432583a9
Binary files /dev/null and b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/data.vbt differ
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/gma-mainboard.ads
new file mode 100644
index 00000000000..fcfbd75a926
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (eDP,
+      DP1,
+      DP2,
+      HDMI1,
+      HDMI2,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/gpio.c
new file mode 100644
index 00000000000..74ab53181ab
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/gpio.c
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "../../gpio.h"
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* RCIN# */
+	_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* LAD0 */
+	_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* LAD1 */
+	_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* LAD2 */
+	_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* LAD3 */
+	_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* LFRAME# */
+	_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SERIRQ */
+	_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* PIRQA# */
+	_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* CLKRUN# */
+	_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* CLKOUT_LPC0 */
+	_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* CLKOUT_LPC1 */
+	_PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* PME# */
+	_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SUSWARN#/SUSPWRDNACK */
+	_PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SUS_STAT# */
+	_PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SUS_ACK# */
+	_PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+
+	/* ------- GPIO Group GPP_B ------- */
+	_PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* CORE_VID0 */
+	_PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* CORE_VID1 */
+	_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SRCCLKREQ0# */
+	_PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SRCCLKREQ1# */
+	_PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SRCCLKREQ2# */
+	_PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SRCCLKREQ3# */
+	_PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SRCCLKREQ4# */
+	_PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SRCCLKREQ5# */
+	_PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* EXT_PWR_GATE# */
+	_PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SLP_S0# */
+	_PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* PLTRST# */
+	_PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SPKR */
+	_PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SMBCLK */
+	_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SMBDATA */
+	_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SML0CLK */
+	_PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* SML0DATA */
+	_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	/* GPP_C6 - RESERVED */
+	/* GPP_C7 - RESERVED */
+	_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+
+	/* ------- GPIO Group GPP_D ------- */
+	_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+
+	/* ------- GPIO Group GPP_E ------- */
+	_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),	/* SATAXPCIE1 */
+	_PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SATA_DEVSLP1 */
+	_PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* USB2_OC0# */
+	_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* USB2_OC1# */
+	_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* USB2_OC2# */
+	_PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDPB_HPD0 */
+	_PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDPC_HPD1 */
+	_PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* EDP_HPD */
+	_PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* DDPB_CTRLCLK */
+	_PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* DDPB_CTRLDATA */
+	_PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* DDPC_CTRLCLK */
+	_PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* DDPC_CTRLDATA */
+	_PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	_PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* BATLOW# */
+	_PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* ACPRESENT */
+	_PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* LAN_WAKE# */
+	_PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),	/* PWRBTN# */
+	_PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SLP_S3# */
+	_PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SLP_S4# */
+	_PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SLP_A# */
+	_PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SUSCLK */
+	_PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SLP_WLAN# */
+	_PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* SLP_S5# */
+	_PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* LANPHYPC */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_F ------- */
+	_PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* I2C4_SDA */
+	_PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* I2C4_SCL */
+	_PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_F23, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),	/* GPIO */
+
+	/* ------- GPIO Group GPP_G ------- */
+	_PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),	/* GPIO */
+};
+
+void variant_config_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/hda_verb.c
new file mode 100644
index 00000000000..2f12b22977e
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/hda_verb.c
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	// Realtek ALC293
+	0x10ec0293, // Vendor/Device ID
+	0x17aa2233, // Subsystem ID
+	11,         // Number of initialization verbs
+
+	AZALIA_SUBVENDOR(0, 0x17aa2233),
+
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_MIC_IN,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		3, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000), // undefined / reserved
+
+	AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_SPEAKER,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+
+	AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT,
+		AZALIA_HP_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		4, 0
+	)),
+
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), // not connected
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), // not connected
+
+	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT,
+		AZALIA_MIC_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		2, 0
+	)),
+
+	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), // not connected
+
+	AZALIA_PIN_CFG(0, 0x1d, 0x40738105), // passthrough modem hand?
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), // not connected
+
+	// Intel Skylake HDMI Audio
+	0x80862809, // HDMI Codec Vendor ID
+	0x80860101, // Subsystem ID
+	4,
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/memory_init_params.c
new file mode 100644
index 00000000000..5252a402f93
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/memory_init_params.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/romstage.h>
+#include <spd_bin.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+	mem_cfg->DqPinsInterleaved = true;			/* DDR_DQ in interleave mode */
+	mem_cfg->CaVrefConfig      = 2;				/* VREF_CA to CH_A and VREF_DQ_B to CH_B */
+	mem_cfg->MemorySpdDataLen  = CONFIG_DIMM_SPD_SIZE;
+
+	/* Get SPD for memory slots */
+	struct spd_block blk = { .addr_map = { 0x50, 0x51, } };
+	get_spd_smbus(&blk);
+	dump_spd_info(&blk);
+
+	mem_cfg->MemorySpdPtr00    = (uintptr_t)blk.spd_array[0];
+	mem_cfg->MemorySpdPtr10    = (uintptr_t)blk.spd_array[1];
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/overridetree.cb
new file mode 100644
index 00000000000..cf5c47a4dff
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t460s/overridetree.cb
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	device domain 0 on
+		device ref sata on
+			register "SataPortsEnable[1]" = "1"
+			register "SataPortsDevSlp[1]" = "1"
+		end
+
+		# USB port map
+		device ref south_xhci on
+		    register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC0), // Right USB-A
+				[1] = USB2_PORT_MID(OC1), // Left USB-A
+				[2] = USB2_PORT_MID(OC_SKIP), // Smartcard
+				[3] = USB2_PORT_MID(OC_SKIP), // USB-C or WWAN
+				[4] = USB2_PORT_MID(OC_SKIP), // Webcam
+				[5] = USB2_PORT_MID(OC_SKIP), // WLAN Bluetooth
+				[6] = USB2_PORT_MID(OC_SKIP),
+				[7] = USB2_PORT_MID(OC_SKIP),
+				[8] = USB2_PORT_MID(OC_SKIP),
+				[9] = USB2_PORT_MID(OC_SKIP),
+		    }"
+
+		    register "usb3_ports" = "{
+	            [0] = USB3_PORT_DEFAULT(OC0), // Right USB-A
+	            [1] = USB3_PORT_DEFAULT(OC1), // Left USB-A
+	            [2] = USB3_PORT_DEFAULT(OC_SKIP), // maybe unused
+	            [3] = USB3_PORT_DEFAULT(OC_SKIP), // maybe USB-C
+		    }"
+		end
+
+		# PCIe configuration:
+		
+		# SD Card reader (Realtek RTS522A) on RP1
+		device ref pcie_rp1 on
+			register "PcieRpClkReqSupport[0]" = "0"
+			register "PcieRpClkReqNumber[0]" = "0"
+			register "PcieRpClkSrcNumber[0]" = "0"
+			register "PcieRpAdvancedErrorReporting[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
+		end
+
+		device generic 0 alias dgpu off end
+
+		# WLAN (Intel 8260) on RP3
+		device ref pcie_rp3 on
+			register "PcieRpClkReqSupport[2]" = "0"
+			register "PcieRpClkReqNumber[2]" = "1"
+			register "PcieRpClkSrcNumber[2]" = "1"
+			register "PcieRpAdvancedErrorReporting[2]" = "1"
+			register "PcieRpLtrEnable[2]" = "1"
+		end
+
+		# NVMe SSD on RP5
+		device ref pcie_rp5 on
+			register "PcieRpClkReqSupport[4]" = "0"
+			register "PcieRpClkReqNumber[4]" = "5"
+			register "PcieRpClkSrcNumber[4]" = "5"
+			register "PcieRpAdvancedErrorReporting[4]" = "1"
+			register "PcieRpLtrEnable[4]" = "1"
+		end
+
+		# Ethernet 
+		device ref gbe on
+			register "LanClkReqSupported"			= "0"
+			register "LanClkReqNumber"			= "2"
+			register "EnableLanLtr"				= "1"
+			register "EnableLanK1Off"			= "1"
+		end
+
+	end
+end