From 3f10e9cdd11bbed7033125a2eb09ab002dbb647d Mon Sep 17 00:00:00 2001 From: iverly Date: Mon, 28 Feb 2022 11:27:35 +0100 Subject: [PATCH 1/6] feat: add shr/shl instructions --- src/main.rs | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/src/main.rs b/src/main.rs index 3bfa147..ed9a98b 100644 --- a/src/main.rs +++ b/src/main.rs @@ -28,6 +28,8 @@ enum OpCode { STW = 0x01, ADD = 0x02, XOR = 0x03, + SHR = 0x04, + SHL = 0x05, } impl OpCode { @@ -37,6 +39,8 @@ impl OpCode { 0x01 => OpCode::STW, 0x02 => OpCode::ADD, 0x03 => OpCode::XOR, + 0x04 => OpCode::SHR, + 0x05 => OpCode::SHL, _ => panic!("Unknown opcode {:?}", opcode), } } @@ -49,6 +53,14 @@ fn xor(op0: u32, op1: u32) -> u32 { op0 ^ op1 } +fn shr(op0: u32, op1: u8) -> u32 { + op0 >> op1 +} + +fn shl(op0: u32, op1: u8) -> u32 { + op0 << op1 +} + fn main() { // ADD R1, R3 -> Opcode is 2 (ADD), op0 is 1 (R1) and op1 is 3 (R3) // The first 6 bits of the instruction are the opcode (2): 0b000010 @@ -78,6 +90,8 @@ fn main() { match decoded_instruction.opcode { OpCode::ADD => r1 = add(r1, r3), OpCode::XOR => r1 = xor(r1, r3), + OpCode::SHL => r1 = shr(r1, decoded_instruction.op1), + OpCode::SHR => r1 = shl(r1, decoded_instruction.op1), _ => panic!("Unknown opcode {:?}", decoded_instruction.opcode), } @@ -140,4 +154,24 @@ mod tests { assert_eq!(insn.op0, 5); assert_eq!(insn.op1, 0); } + + #[test] + fn test_instruction_disassemble_shr_r1_r0() { + let insn_bytes: u32 = 0x0804; + let insn = Instruction::disassemble(insn_bytes); + + assert_eq!(insn.opcode, OpCode::SHR); + assert_eq!(insn.op0, 0); + assert_eq!(insn.op1, 1); + } + + #[test] + fn test_instruction_disassemble_shl_r6_r2() { + let insn_bytes: u32 = 0x1185; + let insn = Instruction::disassemble(insn_bytes); + + assert_eq!(insn.opcode, OpCode::SHL); + assert_eq!(insn.op0, 6); + assert_eq!(insn.op1, 2); + } } From b9032858f03427a3ddb03e98441b3de4b96fa61d Mon Sep 17 00:00:00 2001 From: iverly Date: Mon, 28 Feb 2022 11:40:22 +0100 Subject: [PATCH 2/6] feat: add more test for shr/shl --- src/main.rs | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/src/main.rs b/src/main.rs index ed9a98b..0f716d0 100644 --- a/src/main.rs +++ b/src/main.rs @@ -103,7 +103,7 @@ fn main() { #[cfg(test)] mod tests { - use crate::{Instruction, OpCode}; + use crate::{Instruction, OpCode, shl, shr}; #[test] fn test_instruction_disassemble_add_r1_r3() { @@ -174,4 +174,38 @@ mod tests { assert_eq!(insn.op0, 6); assert_eq!(insn.op1, 2); } + + #[test] + fn test_function_shl() { + let op0: u32 = 0x05; + let op1: u8 = 0x01; + let result = shl(op0, op1); + + assert_eq!(result, 0x0A); + } + + #[test] + fn test_function_shr() { + let op0: u32 = 0x10; + let op1: u8 = 0x03; + let result = shr(op0, op1); + + assert_eq!(result, 0x02); + } + + #[test] + #[should_panic] + fn test_function_shl_should_panic_overflow() { + let op0: u32 = 0x05; + let op1: u8 = 0x30; + shl(op0, op1); + } + + #[test] + #[should_panic] + fn test_function_shr_should_panic_overflow() { + let op0: u32 = 0x10; + let op1: u8 = 0x28; + shr(op0, op1); + } } From bec965e61d2afe4b331d31f9a3d43b1f8f41b17c Mon Sep 17 00:00:00 2001 From: iverly Date: Mon, 28 Feb 2022 11:46:17 +0100 Subject: [PATCH 3/6] docs(readme): add shr/shl instructions --- README.md | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/README.md b/README.md index 7c6ab92..8640182 100644 --- a/README.md +++ b/README.md @@ -49,9 +49,11 @@ The `do-core1` is a [load-store](https://en.wikipedia.org/wiki/Load%E2%80%93stor architecture and supports the following instructions: -| Opcode | Instruction | Description | -|--------|--------------|------------------------------------------------------------------------------------------------| -| `0x00` | `LDW Rn, Rm` | **L**oa**D** **W**ord: Load the 32-bit value at the memory address contained in `Rm` into `Rn` | -| `0x01` | `STW Rn, Rm` | **ST**ore **W**ord: Store the 32-bit value from `Rn` into the memory address contained in `Rm` | -| `0x02` | `ADD Rn, Rm` | **ADD**: Add the value contained in `Rm` into `Rn` (`Rn = Rn + Rm`) | -| `0x03` | `XOR Rn, Rm` | e**X**clusive **OR**: Perform a bitwise exclusive OR between `Rn` and `Rm` (`Rn = Rn ^ Rm`) | +| Opcode | Instruction | Description | +|--------|-----------------|------------------------------------------------------------------------------------------------| +| `0x00` | `LDW Rn, Rm` | **L**oa**D** **W**ord: Load the 32-bit value at the memory address contained in `Rm` into `Rn` | +| `0x01` | `STW Rn, Rm` | **ST**ore **W**ord: Store the 32-bit value from `Rn` into the memory address contained in `Rm` | +| `0x02` | `ADD Rn, Rm` | **ADD**: Add the value contained in `Rm` into `Rn` (`Rn = Rn + Rm`) | +| `0x03` | `XOR Rn, Rm` | e**X**clusive **OR**: Perform a bitwise exclusive OR between `Rn` and `Rm` (`Rn = Rn ^ Rm`) | +| `0x04` | `SHR Rn, Count` | **SH**ift **R**ight: Perform a right shift in `Rn` on `Count` bits (`Rn = Rn >> Count`) | +| `0x05` | `SHL Rn, Count` | **SH**ift **L**eft: Perform a left shift in `Rn` on `Count` bits (`Rn = Rn << Count`) | From fbcd1980e494f1e65657672d591f7dffd3bf5f0d Mon Sep 17 00:00:00 2001 From: iverly Date: Mon, 28 Feb 2022 12:18:46 +0100 Subject: [PATCH 4/6] feat: add cli with args parser --- Cargo.lock | 233 ++++++++++++++++++++++++++++++++++++++++++++++++++++ Cargo.toml | 1 + src/main.rs | 14 +++- 3 files changed, 247 insertions(+), 1 deletion(-) diff --git a/Cargo.lock b/Cargo.lock index d8530d9..7c1d572 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1,5 +1,238 @@ # This file is automatically @generated by Cargo. # It is not intended for manual editing. +version = 3 + +[[package]] +name = "atty" +version = "0.2.14" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d9b39be18770d11421cdb1b9947a45dd3f37e93092cbf377614828a319d5fee8" +dependencies = [ + "hermit-abi", + "libc", + "winapi", +] + +[[package]] +name = "autocfg" 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disassembler. fn disassemble(insn: u32) -> Instruction { @@ -72,7 +83,8 @@ fn main() { // 0001 1000 0100 0010 // 1 8 4 2 // 0b0001100001000010 = 0x1842 - let insn: u32 = 0x1842; + let args: DoCoreArgs = DoCoreArgs::parse(); + let insn: u32 = u32::from_str_radix(args.insn.trim_start_matches("0x"), 16).unwrap(); let mut r1: u32 = 20; let r3: u32 = 12; From 02fb619c46ec7b8807f798cede59420a978b78a2 Mon Sep 17 00:00:00 2001 From: iverly Date: Mon, 28 Feb 2022 13:16:37 +0100 Subject: [PATCH 5/6] fix(warn): allow dead_code on Instruction struct --- src/main.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main.rs b/src/main.rs index 8421f4d..9ebb58b 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,5 +1,6 @@ use clap::Parser; +#[allow(dead_code)] #[derive(Debug)] struct Instruction { opcode: OpCode, From 0b0f00eefa66b6a5b6d36f18e64b5c148bd8a41e Mon Sep 17 00:00:00 2001 From: iverly Date: Mon, 28 Feb 2022 13:37:05 +0100 Subject: [PATCH 6/6] feat(docs): add cargo docs --- src/main.rs | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/src/main.rs b/src/main.rs index 9ebb58b..c0d86bb 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,24 +1,30 @@ use clap::Parser; +/// Represent an instruction +/// with an opcode and two operands #[allow(dead_code)] #[derive(Debug)] struct Instruction { + /// the operation code opcode: OpCode, + /// the first operand op0: u8, + /// the second operand op1: u8, } -// Simple cli to execute an instruction from the do-core1 +/// Simple cli to execute an instruction from the do-core1 #[derive(Parser, Debug)] #[clap(author, version, about, long_about = None)] struct DoCoreArgs { - /// Instruction to execute + /// Instruction to execute (eg. 0x1842) #[clap(short, long)] insn: String, } impl Instruction { - // Instruction constructor, a.k.a. disassembler. + /// Instruction constructor, a.k.a. disassembler. + /// Take an instruction code as u32 and return an Instruction instance fn disassemble(insn: u32) -> Instruction { // Keep the first 6 bits only let opcode = OpCode::from_u8((insn & 0x3f) as u8); @@ -33,6 +39,7 @@ impl Instruction { } } +/// Represent an operation code from the do-core #[allow(dead_code)] #[derive(Debug, PartialEq)] enum OpCode { @@ -45,6 +52,7 @@ enum OpCode { } impl OpCode { + /// Convert an u8 to an OpCode, panic if it's not a valid OpCode fn from_u8(opcode: u8) -> OpCode { match opcode { 0x00 => OpCode::LDW, @@ -57,33 +65,29 @@ impl OpCode { } } } + +/// Returns the result of the addition of the two parameters fn add(op0: u32, op1: u32) -> u32 { op0 + op1 } +/// Return the XOR operation of the two parameters fn xor(op0: u32, op1: u32) -> u32 { op0 ^ op1 } +/// Return the right shift operation of the two parameters fn shr(op0: u32, op1: u8) -> u32 { op0 >> op1 } +/// Return the left shift operation of the two parameters fn shl(op0: u32, op1: u8) -> u32 { op0 << op1 } +/// Launch the cli, parse the arguments and execute the instruction fn main() { - // ADD R1, R3 -> Opcode is 2 (ADD), op0 is 1 (R1) and op1 is 3 (R3) - // The first 6 bits of the instruction are the opcode (2): 0b000010 - // Bits 6 to 10 are for op0 (1): 0b000001 - // Bits 11 to 15 are for op1 (3): 0b000011 - // The instruction for ADD R1, R3 is: 00011 | 00001 | 000010, i.e. 0b0001100001000010 - // - // When splitting this binary representation in groups of 4 bits, this looks like: - // 0001 1000 0100 0010 - // 1 8 4 2 - // 0b0001100001000010 = 0x1842 let args: DoCoreArgs = DoCoreArgs::parse(); let insn: u32 = u32::from_str_radix(args.insn.trim_start_matches("0x"), 16).unwrap(); let mut r1: u32 = 20;