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Merge: CNB102: dpll: update dpll to the v6.17
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-10/-/merge_requests/1726 JIRA: https://issues.redhat.com/browse/RHEL-126529 Dpll update to version v6.18-rc3 Signed-off-by: Petr Oros <poros@redhat.com> Approved-by: Murphy Zhou <xzhou@redhat.com> Approved-by: Michal Schmidt <mschmidt@redhat.com> Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com> Merged-by: CKI GitLab Kmaint Pipeline Bot <26919896-cki-kmaint-pipeline-bot@users.noreply.gitlab.com>
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‎Documentation/driver-api/dpll.rst‎

Lines changed: 62 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -179,29 +179,47 @@ Phase offset measurement and adjustment
179179
Device may provide ability to measure a phase difference between signals
180180
on a pin and its parent dpll device. If pin-dpll phase offset measurement
181181
is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET``
182-
attribute for each parent dpll device.
182+
attribute for each parent dpll device. The reported phase offset may be
183+
computed as the average of prior values and the current measurement, using
184+
the following formula:
185+
186+
.. math::
187+
curr\_avg = prev\_avg * \frac{2^N-1}{2^N} + new\_val * \frac{1}{2^N}
188+
189+
where `curr_avg` is the current reported phase offset, `prev_avg` is the
190+
previously reported value, `new_val` is the current measurement, and `N` is
191+
the averaging factor. Configured averaging factor value is provided with
192+
``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attribute of a device and value change can
193+
be requested with the same attribute with ``DPLL_CMD_DEVICE_SET`` command.
194+
195+
================================== ======================================
196+
``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attr configured value of phase offset
197+
averaging factor
198+
================================== ======================================
183199

184200
Device may also provide ability to adjust a signal phase on a pin.
185-
If pin phase adjustment is supported, minimal and maximal values that pin
186-
handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond
187-
with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX``
201+
If pin phase adjustment is supported, minimal and maximal values and
202+
granularity that pin handle shall be provided to the user on
203+
``DPLL_CMD_PIN_GET`` respond with ``DPLL_A_PIN_PHASE_ADJUST_MIN``,
204+
``DPLL_A_PIN_PHASE_ADJUST_MAX`` and ``DPLL_A_PIN_PHASE_ADJUST_GRAN``
188205
attributes. Configured phase adjust value is provided with
189206
``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be
190207
requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.
191208

192-
=============================== ======================================
193-
``DPLL_A_PIN_ID`` configured pin id
194-
``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
195-
``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
196-
``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
197-
adjustment on parent dpll device
198-
``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting
199-
configuration on given parent dpll
200-
device
201-
``DPLL_A_PIN_PARENT_ID`` parent dpll device id
202-
``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
203-
between a pin and parent dpll device
204-
=============================== ======================================
209+
================================ ==========================================
210+
``DPLL_A_PIN_ID`` configured pin id
211+
``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attr granularity of phase adjustment value
212+
``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
213+
``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
214+
``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
215+
adjustment on parent dpll device
216+
``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting
217+
configuration on given parent dpll
218+
device
219+
``DPLL_A_PIN_PARENT_ID`` parent dpll device id
220+
``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
221+
between a pin and parent dpll device
222+
================================ ==========================================
205223

206224
All phase related values are provided in pico seconds, which represents
207225
time difference between signals phase. The negative value means that
@@ -253,6 +271,31 @@ the pin.
253271
``DPLL_A_PIN_ESYNC_PULSE`` pulse type of Embedded SYNC
254272
========================================= =================================
255273

274+
Reference SYNC
275+
==============
276+
277+
The device may support the Reference SYNC feature, which allows the combination
278+
of two inputs into a input pair. In this configuration, clock signals
279+
from both inputs are used to synchronize the DPLL device. The higher frequency
280+
signal is utilized for the loop bandwidth of the DPLL, while the lower frequency
281+
signal is used to syntonize the output signal of the DPLL device. This feature
282+
enables the provision of a high-quality loop bandwidth signal from an external
283+
source.
284+
285+
A capable input provides a list of inputs that can be bound with to create
286+
Reference SYNC. To control this feature, the user must request a desired
287+
state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or
288+
``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. An input pin can be
289+
bound to only one other pin at any given time.
290+
291+
============================== ==========================================
292+
``DPLL_A_PIN_REFERENCE_SYNC`` nested attribute for providing info or
293+
requesting configuration of the Reference
294+
SYNC feature
295+
``DPLL_A_PIN_ID`` target pin id for Reference SYNC feature
296+
``DPLL_A_PIN_STATE`` state of Reference SYNC connection
297+
============================== ==========================================
298+
256299
Configuration commands group
257300
============================
258301

@@ -343,6 +386,8 @@ according to attribute purpose.
343386
frequencies
344387
``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency
345388
``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency
389+
``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attr granularity of phase
390+
adjustment value
346391
``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase
347392
adjustment
348393
``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase

‎Documentation/netlink/specs/dpll.yaml‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -315,6 +315,10 @@ attribute-sets:
315315
If enabled, dpll device shall monitor and notify all currently
316316
available inputs for changes of their phase offset against the
317317
dpll device.
318+
-
319+
name: phase-offset-avg-factor
320+
type: u32
321+
doc: Averaging factor applied to calculation of reported phase offset.
318322
-
319323
name: pin
320324
enum-name: dpll_a_pin
@@ -428,6 +432,21 @@ attribute-sets:
428432
doc: |
429433
A ratio of high to low state of a SYNC signal pulse embedded
430434
into base clock frequency. Value is in percents.
435+
-
436+
name: reference-sync
437+
type: nest
438+
multi-attr: true
439+
nested-attributes: reference-sync
440+
doc: |
441+
Capable pin provides list of pins that can be bound to create a
442+
reference-sync pin pair.
443+
-
444+
name: phase-adjust-gran
445+
type: u32
446+
doc: |
447+
Granularity of phase adjustment, in picoseconds. The value of
448+
phase adjustment must be a multiple of this granularity.
449+
431450
-
432451
name: pin-parent-device
433452
subset-of: pin
@@ -458,6 +477,14 @@ attribute-sets:
458477
name: frequency-min
459478
-
460479
name: frequency-max
480+
-
481+
name: reference-sync
482+
subset-of: pin
483+
attributes:
484+
-
485+
name: id
486+
-
487+
name: state
461488

462489
operations:
463490
enum-name: dpll_cmd
@@ -506,6 +533,7 @@ operations:
506533
- clock-id
507534
- type
508535
- phase-offset-monitor
536+
- phase-offset-avg-factor
509537

510538
dump:
511539
reply: *dev-attrs
@@ -523,6 +551,7 @@ operations:
523551
attributes:
524552
- id
525553
- phase-offset-monitor
554+
- phase-offset-avg-factor
526555
-
527556
name: device-create-ntf
528557
doc: Notification about device appearing
@@ -582,6 +611,8 @@ operations:
582611
reply: &pin-attrs
583612
attributes:
584613
- id
614+
- module-name
615+
- clock-id
585616
- board-label
586617
- panel-label
587618
- package-label
@@ -591,13 +622,15 @@ operations:
591622
- capabilities
592623
- parent-device
593624
- parent-pin
625+
- phase-adjust-gran
594626
- phase-adjust-min
595627
- phase-adjust-max
596628
- phase-adjust
597629
- fractional-frequency-offset
598630
- esync-frequency
599631
- esync-frequency-supported
600632
- esync-pulse
633+
- reference-sync
601634

602635
dump:
603636
request:
@@ -625,6 +658,7 @@ operations:
625658
- parent-pin
626659
- phase-adjust
627660
- esync-frequency
661+
- reference-sync
628662
-
629663
name: pin-create-ntf
630664
doc: Notification about pin appearing

‎drivers/dpll/dpll_core.c‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -506,6 +506,7 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module *module,
506506
refcount_set(&pin->refcount, 1);
507507
xa_init_flags(&pin->dpll_refs, XA_FLAGS_ALLOC);
508508
xa_init_flags(&pin->parent_refs, XA_FLAGS_ALLOC);
509+
xa_init_flags(&pin->ref_sync_pins, XA_FLAGS_ALLOC);
509510
ret = xa_alloc_cyclic(&dpll_pin_xa, &pin->id, pin, xa_limit_32b,
510511
&dpll_pin_xa_id, GFP_KERNEL);
511512
if (ret < 0)
@@ -514,6 +515,7 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module *module,
514515
err_xa_alloc:
515516
xa_destroy(&pin->dpll_refs);
516517
xa_destroy(&pin->parent_refs);
518+
xa_destroy(&pin->ref_sync_pins);
517519
dpll_pin_prop_free(&pin->prop);
518520
err_pin_prop:
519521
kfree(pin);
@@ -595,6 +597,7 @@ void dpll_pin_put(struct dpll_pin *pin)
595597
xa_erase(&dpll_pin_xa, pin->id);
596598
xa_destroy(&pin->dpll_refs);
597599
xa_destroy(&pin->parent_refs);
600+
xa_destroy(&pin->ref_sync_pins);
598601
dpll_pin_prop_free(&pin->prop);
599602
kfree_rcu(pin, rcu);
600603
}
@@ -659,11 +662,26 @@ dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,
659662
}
660663
EXPORT_SYMBOL_GPL(dpll_pin_register);
661664

665+
static void dpll_pin_ref_sync_pair_del(u32 ref_sync_pin_id)
666+
{
667+
struct dpll_pin *pin, *ref_sync_pin;
668+
unsigned long i;
669+
670+
xa_for_each(&dpll_pin_xa, i, pin) {
671+
ref_sync_pin = xa_load(&pin->ref_sync_pins, ref_sync_pin_id);
672+
if (ref_sync_pin) {
673+
xa_erase(&pin->ref_sync_pins, ref_sync_pin_id);
674+
__dpll_pin_change_ntf(pin);
675+
}
676+
}
677+
}
678+
662679
static void
663680
__dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,
664681
const struct dpll_pin_ops *ops, void *priv, void *cookie)
665682
{
666683
ASSERT_DPLL_PIN_REGISTERED(pin);
684+
dpll_pin_ref_sync_pair_del(pin->id);
667685
dpll_xa_ref_pin_del(&dpll->pin_refs, pin, ops, priv, cookie);
668686
dpll_xa_ref_dpll_del(&pin->dpll_refs, dpll, ops, priv, cookie);
669687
if (xa_empty(&pin->dpll_refs))
@@ -783,6 +801,33 @@ void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin,
783801
}
784802
EXPORT_SYMBOL_GPL(dpll_pin_on_pin_unregister);
785803

804+
/**
805+
* dpll_pin_ref_sync_pair_add - create a reference sync signal pin pair
806+
* @pin: pin which produces the base frequency
807+
* @ref_sync_pin: pin which produces the sync signal
808+
*
809+
* Once pins are paired, the user-space configuration of reference sync pair
810+
* is possible.
811+
* Context: Acquires a lock (dpll_lock)
812+
* Return:
813+
* * 0 on success
814+
* * negative - error value
815+
*/
816+
int dpll_pin_ref_sync_pair_add(struct dpll_pin *pin,
817+
struct dpll_pin *ref_sync_pin)
818+
{
819+
int ret;
820+
821+
mutex_lock(&dpll_lock);
822+
ret = xa_insert(&pin->ref_sync_pins, ref_sync_pin->id,
823+
ref_sync_pin, GFP_KERNEL);
824+
__dpll_pin_change_ntf(pin);
825+
mutex_unlock(&dpll_lock);
826+
827+
return ret;
828+
}
829+
EXPORT_SYMBOL_GPL(dpll_pin_ref_sync_pair_add);
830+
786831
static struct dpll_device_registration *
787832
dpll_device_registration_first(struct dpll_device *dpll)
788833
{

‎drivers/dpll/dpll_core.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,8 +49,8 @@ struct dpll_device {
4949
* @module: module of creator
5050
* @dpll_refs: hold referencees to dplls pin was registered with
5151
* @parent_refs: hold references to parent pins pin was registered with
52+
* @ref_sync_pins: hold references to pins for Reference SYNC feature
5253
* @prop: pin properties copied from the registerer
53-
* @rclk_dev_name: holds name of device when pin can recover clock from it
5454
* @refcount: refcount
5555
* @rcu: rcu_head for kfree_rcu()
5656
*
@@ -66,6 +66,7 @@ struct dpll_pin {
6666
struct module *module;
6767
struct xarray dpll_refs;
6868
struct xarray parent_refs;
69+
struct xarray ref_sync_pins;
6970
struct dpll_pin_properties prop;
7071
refcount_t refcount;
7172
struct rcu_head rcu;

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